From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, mtosatti@redhat.com, seanjc@google.com,
likexu@tencent.com, xiangfeix.ma@intel.com
Subject: [PATCH] i386: Disable BTS and PEBS
Date: Mon, 18 Jul 2022 11:22:06 +0800 [thread overview]
Message-ID: <20220718032206.34488-1-zhenzhong.duan@intel.com> (raw)
Since below KVM commit, KVM hided BTS as it's not supported yet.
b9181c8ef356 ("KVM: x86/pmu: Avoid exposing Intel BTS feature")
After below KVM commit, it gave control of MSR_IA32_MISC_ENABLES to userspace.
9fc222967a39 ("KVM: x86: Give host userspace full control of MSR_IA32_MISC_ENABLES")
So qemu takes the responsibility to hide BTS.
Without fix, we get below warning in guest kernel:
[] unchecked MSR access error: WRMSR to 0x1d9 (tried to write 0x00000000000001c0) at rIP: 0xffffffffaa070644 (native_write_msr+0x4/0x20)
[] Call Trace:
[] <TASK>
[] intel_pmu_enable_bts+0x5d/0x70
[] bts_event_add+0x77/0x90
[] event_sched_in.isra.135+0x99/0x1e0
Tested-by: Xiangfei Ma <xiangfeix.ma@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
target/i386/cpu.h | 6 ++++--
target/i386/kvm/kvm.c | 4 ++++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 82004b65b944..8a83d0995c66 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -434,8 +434,10 @@ typedef enum X86Seg {
#define MSR_IA32_MISC_ENABLE 0x1a0
/* Indicates good rep/movs microcode on some processors: */
-#define MSR_IA32_MISC_ENABLE_DEFAULT 1
-#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
+#define MSR_IA32_MISC_ENABLE_DEFAULT 1
+#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
+#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
+#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index f148a6d52fa4..002e0520dd76 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -2180,6 +2180,10 @@ void kvm_arch_reset_vcpu(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
+ /* Disable BTS feature which is unsupported on KVM */
+ env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
+ env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
+
env->xcr0 = 1;
if (kvm_irqchip_in_kernel()) {
env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
--
2.25.1
next reply other threads:[~2022-07-18 3:31 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-18 3:22 Zhenzhong Duan [this message]
2022-07-18 3:57 ` [PATCH] i386: Disable BTS and PEBS Like Xu
2022-07-18 7:44 ` Duan, Zhenzhong
2022-07-18 16:08 ` Paolo Bonzini
2022-07-18 20:12 ` Sean Christopherson
2022-07-19 18:18 ` Paolo Bonzini
2022-07-19 18:53 ` Sean Christopherson
2022-07-20 2:35 ` Duan, Zhenzhong
2022-07-20 15:48 ` Sean Christopherson
2022-07-21 2:42 ` Like Xu
2022-08-19 1:38 ` Duan, Zhenzhong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220718032206.34488-1-zhenzhong.duan@intel.com \
--to=zhenzhong.duan@intel.com \
--cc=likexu@tencent.com \
--cc=mtosatti@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=seanjc@google.com \
--cc=xiangfeix.ma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).