From: Igor Mammedov <imammedo@redhat.com>
To: Joao Martins <joao.m.martins@oracle.com>
Cc: qemu-devel@nongnu.org, Eduardo Habkost <eduardo@habkost.net>,
"Michael S. Tsirkin" <mst@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alex Williamson <alex.williamson@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>, Ani Sinha <ani@anisinha.ca>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
"Dr. David Alan Gilbert" <dgilbert@redhat.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: [PATCH v8 09/11] i386/pc: bounds check phys-bits against max used GPA
Date: Mon, 18 Jul 2022 15:56:57 +0200 [thread overview]
Message-ID: <20220718155657.5f975c50@redhat.com> (raw)
In-Reply-To: <20220718151622.3c38f261@redhat.com>
On Mon, 18 Jul 2022 15:16:22 +0200
Igor Mammedov <imammedo@redhat.com> wrote:
> On Fri, 15 Jul 2022 18:16:26 +0100
> Joao Martins <joao.m.martins@oracle.com> wrote:
>
> > Calculate max *used* GPA against the CPU maximum possible address
> > and error out if the former surprasses the latter. This ensures
> > max used GPA is reacheable by configured phys-bits. Default phys-bits
> > on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough for the CPU to
> > address 1Tb (0xff ffff ffff) or 1010G (0xfc ffff ffff) in AMD hosts
> > with IOMMU.
> >
> > This is preparation for AMD guests with >1010G, where it will want relocate
> > ram-above-4g to be after 1Tb instead of 4G.
> >
> > Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
[...]
> > + return pc_pci_hole64_start() + pci_hole64_size - 1;
off by 1?
> > +}
> > +
[...]
next prev parent reply other threads:[~2022-07-18 14:19 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 17:16 [PATCH v8 00/11] i386/pc: Fix creation of >= 1010G guests on AMD systems with IOMMU Joao Martins
2022-07-15 17:16 ` [PATCH v8 01/11] hw/i386: add 4g boundary start to X86MachineState Joao Martins
2022-07-15 17:16 ` [PATCH v8 02/11] i386/pc: create pci-host qdev prior to pc_memory_init() Joao Martins
2022-07-15 17:16 ` [PATCH v8 03/11] i386/pc: pass pci_hole64_size " Joao Martins
2022-07-15 17:16 ` [PATCH v8 04/11] i386/pc: factor out above-4g end to an helper Joao Martins
2022-07-15 17:16 ` [PATCH v8 05/11] i386/pc: factor out cxl range end to helper Joao Martins
2022-07-18 12:53 ` Igor Mammedov
2022-07-15 17:16 ` [PATCH v8 06/11] i386/pc: factor out cxl range start " Joao Martins
2022-07-18 12:52 ` Igor Mammedov
2022-07-18 13:51 ` Joao Martins
2022-07-15 17:16 ` [PATCH v8 07/11] i386/pc: handle unitialized mr in pc_get_cxl_range_end() Joao Martins
2022-07-18 12:58 ` Igor Mammedov
2022-07-18 13:55 ` Joao Martins
2022-07-15 17:16 ` [PATCH v8 08/11] i386/pc: factor out device_memory base/size to helper Joao Martins
2022-07-18 13:03 ` Igor Mammedov
2022-07-18 14:22 ` Joao Martins
2022-07-15 17:16 ` [PATCH v8 09/11] i386/pc: bounds check phys-bits against max used GPA Joao Martins
2022-07-18 13:16 ` Igor Mammedov
2022-07-18 13:56 ` Igor Mammedov [this message]
2022-07-18 14:21 ` Joao Martins
2022-07-15 17:16 ` [PATCH v8 10/11] i386/pc: relocate 4g start to 1T where applicable Joao Martins
2022-07-18 13:18 ` Igor Mammedov
2022-07-15 17:16 ` [PATCH v8 11/11] i386/pc: restrict AMD only enforcing of 1Tb hole to new machine type Joao Martins
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