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From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Joao Martins <joao.m.martins@oracle.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>
Subject: [PULL 13/16] i386/pc: bounds check phys-bits against max used GPA
Date: Tue, 26 Jul 2022 15:40:54 -0400	[thread overview]
Message-ID: <20220726193858.177462-14-mst@redhat.com> (raw)
In-Reply-To: <20220726193858.177462-1-mst@redhat.com>

From: Joao Martins <joao.m.martins@oracle.com>

Calculate max *used* GPA against the CPU maximum possible address
and error out if the former surprasses the latter. This ensures
max used GPA is reacheable by configured phys-bits. Default phys-bits
on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough for the CPU to
address 1Tb (0xff ffff ffff) or 1010G (0xfc ffff ffff) in AMD hosts
with IOMMU.

This is preparation for AMD guests with >1010G, where it will want relocate
ram-above-4g to be after 1Tb instead of 4G.

Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220719170014.27028-10-joao.m.martins@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/pc.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index ebc27e4cb7..56d8c179ea 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -879,6 +879,18 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
     return start;
 }
 
+static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
+{
+    X86CPU *cpu = X86_CPU(first_cpu);
+
+    /* 32-bit systems don't have hole64 thus return max CPU address */
+    if (cpu->phys_bits <= 32) {
+        return ((hwaddr)1 << cpu->phys_bits) - 1;
+    }
+
+    return pc_pci_hole64_start() + pci_hole64_size - 1;
+}
+
 void pc_memory_init(PCMachineState *pcms,
                     MemoryRegion *system_memory,
                     MemoryRegion *rom_memory,
@@ -893,13 +905,28 @@ void pc_memory_init(PCMachineState *pcms,
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
     X86MachineState *x86ms = X86_MACHINE(pcms);
+    hwaddr maxphysaddr, maxusedaddr;
     hwaddr cxl_base, cxl_resv_end = 0;
+    X86CPU *cpu = X86_CPU(first_cpu);
 
     assert(machine->ram_size == x86ms->below_4g_mem_size +
                                 x86ms->above_4g_mem_size);
 
     linux_boot = (machine->kernel_filename != NULL);
 
+    /*
+     * phys-bits is required to be appropriately configured
+     * to make sure max used GPA is reachable.
+     */
+    maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
+    maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
+    if (maxphysaddr < maxusedaddr) {
+        error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
+                     " phys-bits too low (%u)",
+                     maxphysaddr, maxusedaddr, cpu->phys_bits);
+        exit(EXIT_FAILURE);
+    }
+
     /*
      * Split single memory region and use aliases to address portions of it,
      * done for backwards compatibility with older qemus.
-- 
MST



  parent reply	other threads:[~2022-07-26 19:59 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-26 19:40 [PULL 00/16] pc,virtio: fixes Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 01/16] acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug() Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 02/16] hw/machine: Clear out left over CXL related pointer from move of state handling to machines Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 03/16] hw/i386/pc: Always place CXL Memory Regions after device_memory Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 04/16] hw/cxl: Fix size of constant in interleave granularity function Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 05/16] hw/i386: add 4g boundary start to X86MachineState Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 06/16] i386/pc: create pci-host qdev prior to pc_memory_init() Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 07/16] i386/pc: pass pci_hole64_size " Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 08/16] i386/pc: factor out above-4g end to an helper Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 09/16] i386/pc: factor out cxl range end to helper Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 10/16] i386/pc: factor out cxl range start " Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 11/16] i386/pc: handle unitialized mr in pc_get_cxl_range_end() Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 12/16] i386/pc: factor out device_memory base/size to helper Michael S. Tsirkin
2022-07-26 19:40 ` Michael S. Tsirkin [this message]
2022-07-26 19:40 ` [PULL 14/16] i386/pc: relocate 4g start to 1T where applicable Michael S. Tsirkin
2022-07-26 19:40 ` [PULL 15/16] i386/pc: restrict AMD only enforcing of 1Tb hole to new machine type Michael S. Tsirkin
2022-07-26 19:41 ` [PULL 16/16] hw/virtio/virtio-iommu: Enforce power-of-two notify for both MAP and UNMAP Michael S. Tsirkin
2022-07-26 21:51 ` [PULL 00/16] pc,virtio: fixes Richard Henderson

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