* [PULL 1/2] RISC-V: Allow both Zmmul and M
2022-07-28 0:59 [PULL 0/2] riscv-to-apply queue Alistair Francis
@ 2022-07-28 0:59 ` Alistair Francis
2022-07-28 1:00 ` [PULL 2/2] hw/intc: sifive_plic: Fix multi-socket plic configuraiton Alistair Francis
2022-07-28 18:27 ` [PULL 0/2] riscv-to-apply queue Richard Henderson
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-07-28 0:59 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Palmer Dabbelt, Alistair Francis
From: Palmer Dabbelt <palmer@rivosinc.com>
We got to talking about how Zmmul and M interact with each other
https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
combination, it just means that the multiplication instructions are
supported even when M is disabled at runtime via misa.
This just stops overriding M from Zmmul, with that the other checks for
the multiplication instructions work as per the ISA.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220714180033.22385-1-palmer@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1bb3973806..ac6f82ebd0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -619,11 +619,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_ifencei = true;
}
- if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
- warn_report("Zmmul will override M");
- cpu->cfg.ext_m = false;
- }
-
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
--
2.37.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PULL 2/2] hw/intc: sifive_plic: Fix multi-socket plic configuraiton
2022-07-28 0:59 [PULL 0/2] riscv-to-apply queue Alistair Francis
2022-07-28 0:59 ` [PULL 1/2] RISC-V: Allow both Zmmul and M Alistair Francis
@ 2022-07-28 1:00 ` Alistair Francis
2022-07-28 18:27 ` [PULL 0/2] riscv-to-apply queue Richard Henderson
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-07-28 1:00 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Atish Patra, Alistair Francis
From: Atish Patra <atishp@rivosinc.com>
Since commit 40244040a7ac, multi-socket configuration with plic is
broken as the hartid for second socket is calculated incorrectly.
The hartid stored in addr_config already includes the offset
for the base hartid for that socket. Adding it again would lead
to segfault while creating the plic device for the virt machine.
qdev_connect_gpio_out was also invoked with incorrect number of gpio
lines.
Fixes: 40244040a7ac (hw/intc: sifive_plic: Avoid overflowing the addr_config buffer)
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220723090335.671105-1-atishp@rivosinc.com>
[ Changes by AF:
- Change the qdev_connect_gpio_out() numbering
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 56d60e9ac9..af4ae3630e 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -454,10 +454,10 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
for (i = 0; i < plic->num_addrs; i++) {
int cpu_num = plic->addr_config[i].hartid;
- CPUState *cpu = qemu_get_cpu(hartid_base + cpu_num);
+ CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
- qdev_connect_gpio_out(dev, num_harts + cpu_num,
+ qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
--
2.37.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PULL 0/2] riscv-to-apply queue
2022-07-28 0:59 [PULL 0/2] riscv-to-apply queue Alistair Francis
2022-07-28 0:59 ` [PULL 1/2] RISC-V: Allow both Zmmul and M Alistair Francis
2022-07-28 1:00 ` [PULL 2/2] hw/intc: sifive_plic: Fix multi-socket plic configuraiton Alistair Francis
@ 2022-07-28 18:27 ` Richard Henderson
2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2022-07-28 18:27 UTC (permalink / raw)
To: Alistair Francis, qemu-devel; +Cc: alistair23, Alistair Francis
On 7/27/22 17:59, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 7b17a1a841fc2336eba53afade9cadb14bd3dd9a:
>
> Update version for v7.1.0-rc0 release (2022-07-26 18:03:16 -0700)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220728
>
> for you to fetch changes up to 54f218363052be210e77d2ada8c0c1e51b3ad6cd:
>
> hw/intc: sifive_plic: Fix multi-socket plic configuraiton (2022-07-28 09:08:44 +1000)
>
> ----------------------------------------------------------------
> Sixth RISC-V PR for QEMU 7.1
>
> This is a PR to go in for RC1. It fixes a segfault that occurs
> when using multiple sockets on the RISC-V virt board. It also
> includes a small fix to allow both Zmmul and M extensions.
>
> * Allow both Zmmul and M extension
> * Fix multi-socket plic configuraiton
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.
r~
>
> ----------------------------------------------------------------
> Atish Patra (1):
> hw/intc: sifive_plic: Fix multi-socket plic configuraiton
>
> Palmer Dabbelt (1):
> RISC-V: Allow both Zmmul and M
>
> hw/intc/sifive_plic.c | 4 ++--
> target/riscv/cpu.c | 5 -----
> 2 files changed, 2 insertions(+), 7 deletions(-)
>
^ permalink raw reply [flat|nested] 4+ messages in thread