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From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Openrisc <openrisc@lists.librecores.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [PATCH v3 06/11] hw/openrisc: Initialize timer time at startup
Date: Sat, 30 Jul 2022 08:01:12 +0900	[thread overview]
Message-ID: <20220729230117.3768312-7-shorne@gmail.com> (raw)
In-Reply-To: <20220729230117.3768312-1-shorne@gmail.com>

The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.

This patch moves timer initialization to the cpu reset.  There are two
resets registered here:

 1. Per cpu timer mask (ttmr) reset.
 2. Global cpu timer (last_clk and ttcr) reset, attached to the first
    cpu only.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
Since v2:
 - Moved timer init from init to reset suggested by Richard

 hw/openrisc/cputimer.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 93268815d8..10163b391b 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -22,6 +22,7 @@
 #include "cpu.h"
 #include "migration/vmstate.h"
 #include "qemu/timer.h"
+#include "sysemu/reset.h"
 
 #define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */
 
@@ -122,6 +123,24 @@ static void openrisc_timer_cb(void *opaque)
     qemu_cpu_kick(CPU(cpu));
 }
 
+/* Reset the per CPU counter state. */
+static void openrisc_count_reset(void *opaque)
+{
+    OpenRISCCPU *cpu = opaque;
+
+    if (cpu->env.is_counting) {
+        cpu_openrisc_count_stop(cpu);
+    }
+    cpu->env.ttmr = 0x00000000;
+}
+
+/* Reset the global timer state. */
+static void openrisc_timer_reset(void *opaque)
+{
+    or1k_timer->ttcr = 0x00000000;
+    or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+}
+
 static const VMStateDescription vmstate_or1k_timer = {
     .name = "or1k_timer",
     .version_id = 1,
@@ -136,10 +155,11 @@ static const VMStateDescription vmstate_or1k_timer = {
 void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
 {
     cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);
-    cpu->env.ttmr = 0x00000000;
 
+    qemu_register_reset(openrisc_count_reset, cpu);
     if (or1k_timer == NULL) {
         or1k_timer = g_new0(OR1KTimerState, 1);
+        qemu_register_reset(openrisc_timer_reset, cpu);
         vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
     }
 }
-- 
2.37.1



  parent reply	other threads:[~2022-07-29 23:07 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-29 23:01 [PATCH v3 00/11] OpenRISC Virtual Machine Stafford Horne
2022-07-29 23:01 ` [PATCH v3 01/11] hw/openrisc: Split re-usable boot time apis out to boot.c Stafford Horne
2022-07-29 23:01 ` [PATCH v3 02/11] target/openrisc: Fix memory reading in debugger Stafford Horne
2022-07-29 23:01 ` [PATCH v3 03/11] goldfish_rtc: Add big-endian property Stafford Horne
2022-07-29 23:39   ` Richard Henderson
2022-07-29 23:01 ` [PATCH v3 04/11] hw/openrisc: Add the OpenRISC virtual machine Stafford Horne
2022-07-29 23:01 ` [PATCH v3 05/11] hw/openrisc: Add PCI bus support to virt Stafford Horne
2022-07-29 23:01 ` Stafford Horne [this message]
2022-07-29 23:42   ` [PATCH v3 06/11] hw/openrisc: Initialize timer time at startup Richard Henderson
2022-07-29 23:01 ` [PATCH v3 07/11] target/openrisc: Add interrupted CPU to log Stafford Horne
2022-07-29 23:01 ` [PATCH v3 08/11] target/openrisc: Enable MTTCG Stafford Horne
2022-07-29 23:42   ` Richard Henderson
2022-08-02  2:03     ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 09/11] target/openrisc: Interrupt handling fixes Stafford Horne
2022-07-29 23:01 ` [PATCH v3 10/11] hw/openrisc: virt: pass random seed to fdt Stafford Horne
2022-07-29 23:01 ` [PATCH v3 11/11] docs/system: openrisc: Add OpenRISC documentation Stafford Horne

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