* [PATCH 01/19] ppc/ppc405: Remove taihu machine
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-02 18:02 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 02/19] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
` (17 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
It has been deprecated since 7.0.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/about/deprecated.rst | 9 --
docs/system/ppc/embedded.rst | 1 -
hw/ppc/ppc405_boards.c | 232 -----------------------------------
3 files changed, 242 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 7ee26626d5cf..2f9b41aaea48 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -233,15 +233,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
better reflects the way this property affects all random data within
the device tree blob, not just the ``kaslr-seed`` node.
-PPC 405 ``taihu`` machine (since 7.0)
-'''''''''''''''''''''''''''''''''''''
-
-The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
-except for some external periphery. However, the periphery of the ``taihu``
-machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
-been implemented), so there is not much value added by this board. Use the
-``ref405ep`` machine instead.
-
``pc-i440fx-1.4`` up to ``pc-i440fx-1.7`` (since 7.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''''
diff --git a/docs/system/ppc/embedded.rst b/docs/system/ppc/embedded.rst
index cfffbda24da9..af3b3d9fa460 100644
--- a/docs/system/ppc/embedded.rst
+++ b/docs/system/ppc/embedded.rst
@@ -6,5 +6,4 @@ Embedded family boards
- ``ppce500`` generic paravirt e500 platform
- ``ref405ep`` ref405ep
- ``sam460ex`` aCube Sam460ex
-- ``taihu`` taihu
- ``virtex-ml507`` Xilinx Virtex ML507 reference design
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index a66ad05e3ac3..1a4e7588c584 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -342,241 +342,9 @@ static const TypeInfo ref405ep_type = {
.class_init = ref405ep_class_init,
};
-/*****************************************************************************/
-/* AMCC Taihu evaluation board */
-/* - PowerPC 405EP processor
- * - SDRAM 128 MB at 0x00000000
- * - Boot flash 2 MB at 0xFFE00000
- * - Application flash 32 MB at 0xFC000000
- * - 2 serial ports
- * - 2 ethernet PHY
- * - 1 USB 1.1 device 0x50000000
- * - 1 LCD display 0x50100000
- * - 1 CPLD 0x50100000
- * - 1 I2C EEPROM
- * - 1 I2C thermal sensor
- * - a set of LEDs
- * - bit-bang SPI port using GPIOs
- * - 1 EBC interface connector 0 0x50200000
- * - 1 cardbus controller + expansion slot.
- * - 1 PCI expansion slot.
- */
-typedef struct taihu_cpld_t taihu_cpld_t;
-struct taihu_cpld_t {
- uint8_t reg0;
- uint8_t reg1;
-};
-
-static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
-{
- taihu_cpld_t *cpld;
- uint32_t ret;
-
- cpld = opaque;
- switch (addr) {
- case 0x0:
- ret = cpld->reg0;
- break;
- case 0x1:
- ret = cpld->reg1;
- break;
- default:
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void taihu_cpld_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
-{
- taihu_cpld_t *cpld;
-
- cpld = opaque;
- switch (addr) {
- case 0x0:
- /* Read only */
- break;
- case 0x1:
- cpld->reg1 = value;
- break;
- default:
- break;
- }
-}
-
-static const MemoryRegionOps taihu_cpld_ops = {
- .read = taihu_cpld_read,
- .write = taihu_cpld_write,
- .impl = {
- .min_access_size = 1,
- .max_access_size = 1,
- },
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static void taihu_cpld_reset (void *opaque)
-{
- taihu_cpld_t *cpld;
-
- cpld = opaque;
- cpld->reg0 = 0x01;
- cpld->reg1 = 0x80;
-}
-
-static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
-{
- taihu_cpld_t *cpld;
- MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
-
- cpld = g_new0(taihu_cpld_t, 1);
- memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
- memory_region_add_subregion(sysmem, base, cpld_memory);
- qemu_register_reset(&taihu_cpld_reset, cpld);
-}
-
-static void taihu_405ep_init(MachineState *machine)
-{
- MachineClass *mc = MACHINE_GET_CLASS(machine);
- const char *bios_name = machine->firmware ?: BIOS_FILENAME;
- const char *kernel_filename = machine->kernel_filename;
- const char *initrd_filename = machine->initrd_filename;
- char *filename;
- MemoryRegion *sysmem = get_system_memory();
- MemoryRegion *bios;
- MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
- hwaddr ram_bases[2], ram_sizes[2];
- long bios_size;
- target_ulong kernel_base, initrd_base;
- long kernel_size, initrd_size;
- int linux_boot;
- int fl_idx;
- DriveInfo *dinfo;
- DeviceState *uicdev;
-
- if (machine->ram_size != mc->default_ram_size) {
- char *sz = size_to_str(mc->default_ram_size);
- error_report("Invalid RAM size, should be %s", sz);
- g_free(sz);
- exit(EXIT_FAILURE);
- }
-
- ram_bases[0] = 0;
- ram_sizes[0] = 0x04000000;
- memory_region_init_alias(&ram_memories[0], NULL,
- "taihu_405ep.ram-0", machine->ram, ram_bases[0],
- ram_sizes[0]);
- ram_bases[1] = 0x04000000;
- ram_sizes[1] = 0x04000000;
- memory_region_init_alias(&ram_memories[1], NULL,
- "taihu_405ep.ram-1", machine->ram, ram_bases[1],
- ram_sizes[1]);
- ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
- 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
- /* allocate and load BIOS */
- fl_idx = 0;
-#if defined(USE_FLASH_BIOS)
- dinfo = drive_get(IF_PFLASH, 0, fl_idx);
- if (dinfo) {
- bios_size = 2 * MiB;
- pflash_cfi02_register(0xFFE00000,
- "taihu_405ep.bios", bios_size,
- blk_by_legacy_dinfo(dinfo),
- 64 * KiB, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
- fl_idx++;
- } else
-#endif
- {
- bios = g_new(MemoryRegion, 1);
- memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
- &error_fatal);
- filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- if (filename) {
- bios_size = load_image_size(filename,
- memory_region_get_ram_ptr(bios),
- BIOS_SIZE);
- g_free(filename);
- if (bios_size < 0) {
- error_report("Could not load PowerPC BIOS '%s'", bios_name);
- exit(1);
- }
- bios_size = (bios_size + 0xfff) & ~0xfff;
- memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
- } else if (!qtest_enabled()) {
- error_report("Could not load PowerPC BIOS '%s'", bios_name);
- exit(1);
- }
- }
- /* Register Linux flash */
- dinfo = drive_get(IF_PFLASH, 0, fl_idx);
- if (dinfo) {
- bios_size = 32 * MiB;
- pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
- blk_by_legacy_dinfo(dinfo),
- 64 * KiB, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
- fl_idx++;
- }
- /* Register CLPD & LCD display */
- taihu_cpld_init(sysmem, 0x50100000);
- /* Load kernel */
- linux_boot = (kernel_filename != NULL);
- if (linux_boot) {
- kernel_base = KERNEL_LOAD_ADDR;
- /* now we can load the kernel */
- kernel_size = load_image_targphys(kernel_filename, kernel_base,
- machine->ram_size - kernel_base);
- if (kernel_size < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
- /* load initrd */
- if (initrd_filename) {
- initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image_targphys(initrd_filename, initrd_base,
- machine->ram_size - initrd_base);
- if (initrd_size < 0) {
- error_report("could not load initial ram disk '%s'",
- initrd_filename);
- exit(1);
- }
- } else {
- initrd_base = 0;
- initrd_size = 0;
- }
- } else {
- kernel_base = 0;
- kernel_size = 0;
- initrd_base = 0;
- initrd_size = 0;
- }
-}
-
-static void taihu_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "taihu";
- mc->init = taihu_405ep_init;
- mc->default_ram_size = 0x08000000;
- mc->default_ram_id = "taihu_405ep.ram";
- mc->deprecation_reason = "incomplete, use 'ref405ep' instead";
-}
-
-static const TypeInfo taihu_type = {
- .name = MACHINE_TYPE_NAME("taihu"),
- .parent = TYPE_MACHINE,
- .class_init = taihu_class_init,
-};
-
static void ppc405_machine_init(void)
{
type_register_static(&ref405ep_type);
- type_register_static(&taihu_type);
}
type_init(ppc405_machine_init)
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 01/19] ppc/ppc405: Remove taihu machine
2022-08-01 13:10 ` [PATCH 01/19] ppc/ppc405: Remove taihu machine Cédric Le Goater
@ 2022-08-02 18:02 ` Daniel Henrique Barboza
2022-08-03 7:33 ` Cédric Le Goater
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-02 18:02 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> It has been deprecated since 7.0.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> docs/about/deprecated.rst | 9 --
> docs/system/ppc/embedded.rst | 1 -
> hw/ppc/ppc405_boards.c | 232 -----------------------------------
> 3 files changed, 242 deletions(-)
>
> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> index 7ee26626d5cf..2f9b41aaea48 100644
> --- a/docs/about/deprecated.rst
> +++ b/docs/about/deprecated.rst
> @@ -233,15 +233,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
> better reflects the way this property affects all random data within
> the device tree blob, not just the ``kaslr-seed`` node.
>
> -PPC 405 ``taihu`` machine (since 7.0)
> -'''''''''''''''''''''''''''''''''''''
> -
> -The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
> -except for some external periphery. However, the periphery of the ``taihu``
> -machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
> -been implemented), so there is not much value added by this board. Use the
> -``ref405ep`` machine instead.
> -
I believe we need to add a note in docs/about/removed-feature.rst as well.
E.g. 50f97a0ec6e81b8 where the swift-bmc Aspeed machine was removed. The
deprecated.rst entry was deleted and an entry in removed-features.rst was
added.
Don't worry re-sending the series just for that. I can fixup in the tree if
this is the only observation for the series.
Thanks,
Daniel
> ``pc-i440fx-1.4`` up to ``pc-i440fx-1.7`` (since 7.0)
> '''''''''''''''''''''''''''''''''''''''''''''''''''''
>
> diff --git a/docs/system/ppc/embedded.rst b/docs/system/ppc/embedded.rst
> index cfffbda24da9..af3b3d9fa460 100644
> --- a/docs/system/ppc/embedded.rst
> +++ b/docs/system/ppc/embedded.rst
> @@ -6,5 +6,4 @@ Embedded family boards
> - ``ppce500`` generic paravirt e500 platform
> - ``ref405ep`` ref405ep
> - ``sam460ex`` aCube Sam460ex
> -- ``taihu`` taihu
> - ``virtex-ml507`` Xilinx Virtex ML507 reference design
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index a66ad05e3ac3..1a4e7588c584 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -342,241 +342,9 @@ static const TypeInfo ref405ep_type = {
> .class_init = ref405ep_class_init,
> };
>
> -/*****************************************************************************/
> -/* AMCC Taihu evaluation board */
> -/* - PowerPC 405EP processor
> - * - SDRAM 128 MB at 0x00000000
> - * - Boot flash 2 MB at 0xFFE00000
> - * - Application flash 32 MB at 0xFC000000
> - * - 2 serial ports
> - * - 2 ethernet PHY
> - * - 1 USB 1.1 device 0x50000000
> - * - 1 LCD display 0x50100000
> - * - 1 CPLD 0x50100000
> - * - 1 I2C EEPROM
> - * - 1 I2C thermal sensor
> - * - a set of LEDs
> - * - bit-bang SPI port using GPIOs
> - * - 1 EBC interface connector 0 0x50200000
> - * - 1 cardbus controller + expansion slot.
> - * - 1 PCI expansion slot.
> - */
> -typedef struct taihu_cpld_t taihu_cpld_t;
> -struct taihu_cpld_t {
> - uint8_t reg0;
> - uint8_t reg1;
> -};
> -
> -static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
> -{
> - taihu_cpld_t *cpld;
> - uint32_t ret;
> -
> - cpld = opaque;
> - switch (addr) {
> - case 0x0:
> - ret = cpld->reg0;
> - break;
> - case 0x1:
> - ret = cpld->reg1;
> - break;
> - default:
> - ret = 0;
> - break;
> - }
> -
> - return ret;
> -}
> -
> -static void taihu_cpld_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size)
> -{
> - taihu_cpld_t *cpld;
> -
> - cpld = opaque;
> - switch (addr) {
> - case 0x0:
> - /* Read only */
> - break;
> - case 0x1:
> - cpld->reg1 = value;
> - break;
> - default:
> - break;
> - }
> -}
> -
> -static const MemoryRegionOps taihu_cpld_ops = {
> - .read = taihu_cpld_read,
> - .write = taihu_cpld_write,
> - .impl = {
> - .min_access_size = 1,
> - .max_access_size = 1,
> - },
> - .endianness = DEVICE_NATIVE_ENDIAN,
> -};
> -
> -static void taihu_cpld_reset (void *opaque)
> -{
> - taihu_cpld_t *cpld;
> -
> - cpld = opaque;
> - cpld->reg0 = 0x01;
> - cpld->reg1 = 0x80;
> -}
> -
> -static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
> -{
> - taihu_cpld_t *cpld;
> - MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
> -
> - cpld = g_new0(taihu_cpld_t, 1);
> - memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
> - memory_region_add_subregion(sysmem, base, cpld_memory);
> - qemu_register_reset(&taihu_cpld_reset, cpld);
> -}
> -
> -static void taihu_405ep_init(MachineState *machine)
> -{
> - MachineClass *mc = MACHINE_GET_CLASS(machine);
> - const char *bios_name = machine->firmware ?: BIOS_FILENAME;
> - const char *kernel_filename = machine->kernel_filename;
> - const char *initrd_filename = machine->initrd_filename;
> - char *filename;
> - MemoryRegion *sysmem = get_system_memory();
> - MemoryRegion *bios;
> - MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
> - hwaddr ram_bases[2], ram_sizes[2];
> - long bios_size;
> - target_ulong kernel_base, initrd_base;
> - long kernel_size, initrd_size;
> - int linux_boot;
> - int fl_idx;
> - DriveInfo *dinfo;
> - DeviceState *uicdev;
> -
> - if (machine->ram_size != mc->default_ram_size) {
> - char *sz = size_to_str(mc->default_ram_size);
> - error_report("Invalid RAM size, should be %s", sz);
> - g_free(sz);
> - exit(EXIT_FAILURE);
> - }
> -
> - ram_bases[0] = 0;
> - ram_sizes[0] = 0x04000000;
> - memory_region_init_alias(&ram_memories[0], NULL,
> - "taihu_405ep.ram-0", machine->ram, ram_bases[0],
> - ram_sizes[0]);
> - ram_bases[1] = 0x04000000;
> - ram_sizes[1] = 0x04000000;
> - memory_region_init_alias(&ram_memories[1], NULL,
> - "taihu_405ep.ram-1", machine->ram, ram_bases[1],
> - ram_sizes[1]);
> - ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
> - /* allocate and load BIOS */
> - fl_idx = 0;
> -#if defined(USE_FLASH_BIOS)
> - dinfo = drive_get(IF_PFLASH, 0, fl_idx);
> - if (dinfo) {
> - bios_size = 2 * MiB;
> - pflash_cfi02_register(0xFFE00000,
> - "taihu_405ep.bios", bios_size,
> - blk_by_legacy_dinfo(dinfo),
> - 64 * KiB, 1,
> - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
> - 1);
> - fl_idx++;
> - } else
> -#endif
> - {
> - bios = g_new(MemoryRegion, 1);
> - memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
> - &error_fatal);
> - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> - if (filename) {
> - bios_size = load_image_size(filename,
> - memory_region_get_ram_ptr(bios),
> - BIOS_SIZE);
> - g_free(filename);
> - if (bios_size < 0) {
> - error_report("Could not load PowerPC BIOS '%s'", bios_name);
> - exit(1);
> - }
> - bios_size = (bios_size + 0xfff) & ~0xfff;
> - memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
> - } else if (!qtest_enabled()) {
> - error_report("Could not load PowerPC BIOS '%s'", bios_name);
> - exit(1);
> - }
> - }
> - /* Register Linux flash */
> - dinfo = drive_get(IF_PFLASH, 0, fl_idx);
> - if (dinfo) {
> - bios_size = 32 * MiB;
> - pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
> - blk_by_legacy_dinfo(dinfo),
> - 64 * KiB, 1,
> - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
> - 1);
> - fl_idx++;
> - }
> - /* Register CLPD & LCD display */
> - taihu_cpld_init(sysmem, 0x50100000);
> - /* Load kernel */
> - linux_boot = (kernel_filename != NULL);
> - if (linux_boot) {
> - kernel_base = KERNEL_LOAD_ADDR;
> - /* now we can load the kernel */
> - kernel_size = load_image_targphys(kernel_filename, kernel_base,
> - machine->ram_size - kernel_base);
> - if (kernel_size < 0) {
> - error_report("could not load kernel '%s'", kernel_filename);
> - exit(1);
> - }
> - /* load initrd */
> - if (initrd_filename) {
> - initrd_base = INITRD_LOAD_ADDR;
> - initrd_size = load_image_targphys(initrd_filename, initrd_base,
> - machine->ram_size - initrd_base);
> - if (initrd_size < 0) {
> - error_report("could not load initial ram disk '%s'",
> - initrd_filename);
> - exit(1);
> - }
> - } else {
> - initrd_base = 0;
> - initrd_size = 0;
> - }
> - } else {
> - kernel_base = 0;
> - kernel_size = 0;
> - initrd_base = 0;
> - initrd_size = 0;
> - }
> -}
> -
> -static void taihu_class_init(ObjectClass *oc, void *data)
> -{
> - MachineClass *mc = MACHINE_CLASS(oc);
> -
> - mc->desc = "taihu";
> - mc->init = taihu_405ep_init;
> - mc->default_ram_size = 0x08000000;
> - mc->default_ram_id = "taihu_405ep.ram";
> - mc->deprecation_reason = "incomplete, use 'ref405ep' instead";
> -}
> -
> -static const TypeInfo taihu_type = {
> - .name = MACHINE_TYPE_NAME("taihu"),
> - .parent = TYPE_MACHINE,
> - .class_init = taihu_class_init,
> -};
> -
> static void ppc405_machine_init(void)
> {
> type_register_static(&ref405ep_type);
> - type_register_static(&taihu_type);
> }
>
> type_init(ppc405_machine_init)
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 01/19] ppc/ppc405: Remove taihu machine
2022-08-02 18:02 ` Daniel Henrique Barboza
@ 2022-08-03 7:33 ` Cédric Le Goater
0 siblings, 0 replies; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-03 7:33 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/2/22 20:02, Daniel Henrique Barboza wrote:
>
>
> On 8/1/22 10:10, Cédric Le Goater wrote:
>> It has been deprecated since 7.0.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> docs/about/deprecated.rst | 9 --
>> docs/system/ppc/embedded.rst | 1 -
>> hw/ppc/ppc405_boards.c | 232 -----------------------------------
>> 3 files changed, 242 deletions(-)
>>
>> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
>> index 7ee26626d5cf..2f9b41aaea48 100644
>> --- a/docs/about/deprecated.rst
>> +++ b/docs/about/deprecated.rst
>> @@ -233,15 +233,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
>> better reflects the way this property affects all random data within
>> the device tree blob, not just the ``kaslr-seed`` node.
>> -PPC 405 ``taihu`` machine (since 7.0)
>> -'''''''''''''''''''''''''''''''''''''
>> -
>> -The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
>> -except for some external periphery. However, the periphery of the ``taihu``
>> -machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
>> -been implemented), so there is not much value added by this board. Use the
>> -``ref405ep`` machine instead.
>> -
>
> I believe we need to add a note in docs/about/removed-feature.rst as well.
> E.g. 50f97a0ec6e81b8 where the swift-bmc Aspeed machine was removed. The
> deprecated.rst entry was deleted and an entry in removed-features.rst was
> added.
Ah yes. I forgot. Fixed in v2.
Thanks,
C.
>
> Don't worry re-sending the series just for that. I can fixup in the tree if
> this is the only observation for the series.
>
>
> Thanks,
>
>
> Daniel
>
>> ``pc-i440fx-1.4`` up to ``pc-i440fx-1.7`` (since 7.0)
>> '''''''''''''''''''''''''''''''''''''''''''''''''''''
>> diff --git a/docs/system/ppc/embedded.rst b/docs/system/ppc/embedded.rst
>> index cfffbda24da9..af3b3d9fa460 100644
>> --- a/docs/system/ppc/embedded.rst
>> +++ b/docs/system/ppc/embedded.rst
>> @@ -6,5 +6,4 @@ Embedded family boards
>> - ``ppce500`` generic paravirt e500 platform
>> - ``ref405ep`` ref405ep
>> - ``sam460ex`` aCube Sam460ex
>> -- ``taihu`` taihu
>> - ``virtex-ml507`` Xilinx Virtex ML507 reference design
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index a66ad05e3ac3..1a4e7588c584 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -342,241 +342,9 @@ static const TypeInfo ref405ep_type = {
>> .class_init = ref405ep_class_init,
>> };
>> -/*****************************************************************************/
>> -/* AMCC Taihu evaluation board */
>> -/* - PowerPC 405EP processor
>> - * - SDRAM 128 MB at 0x00000000
>> - * - Boot flash 2 MB at 0xFFE00000
>> - * - Application flash 32 MB at 0xFC000000
>> - * - 2 serial ports
>> - * - 2 ethernet PHY
>> - * - 1 USB 1.1 device 0x50000000
>> - * - 1 LCD display 0x50100000
>> - * - 1 CPLD 0x50100000
>> - * - 1 I2C EEPROM
>> - * - 1 I2C thermal sensor
>> - * - a set of LEDs
>> - * - bit-bang SPI port using GPIOs
>> - * - 1 EBC interface connector 0 0x50200000
>> - * - 1 cardbus controller + expansion slot.
>> - * - 1 PCI expansion slot.
>> - */
>> -typedef struct taihu_cpld_t taihu_cpld_t;
>> -struct taihu_cpld_t {
>> - uint8_t reg0;
>> - uint8_t reg1;
>> -};
>> -
>> -static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
>> -{
>> - taihu_cpld_t *cpld;
>> - uint32_t ret;
>> -
>> - cpld = opaque;
>> - switch (addr) {
>> - case 0x0:
>> - ret = cpld->reg0;
>> - break;
>> - case 0x1:
>> - ret = cpld->reg1;
>> - break;
>> - default:
>> - ret = 0;
>> - break;
>> - }
>> -
>> - return ret;
>> -}
>> -
>> -static void taihu_cpld_write(void *opaque, hwaddr addr,
>> - uint64_t value, unsigned size)
>> -{
>> - taihu_cpld_t *cpld;
>> -
>> - cpld = opaque;
>> - switch (addr) {
>> - case 0x0:
>> - /* Read only */
>> - break;
>> - case 0x1:
>> - cpld->reg1 = value;
>> - break;
>> - default:
>> - break;
>> - }
>> -}
>> -
>> -static const MemoryRegionOps taihu_cpld_ops = {
>> - .read = taihu_cpld_read,
>> - .write = taihu_cpld_write,
>> - .impl = {
>> - .min_access_size = 1,
>> - .max_access_size = 1,
>> - },
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> -};
>> -
>> -static void taihu_cpld_reset (void *opaque)
>> -{
>> - taihu_cpld_t *cpld;
>> -
>> - cpld = opaque;
>> - cpld->reg0 = 0x01;
>> - cpld->reg1 = 0x80;
>> -}
>> -
>> -static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
>> -{
>> - taihu_cpld_t *cpld;
>> - MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
>> -
>> - cpld = g_new0(taihu_cpld_t, 1);
>> - memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
>> - memory_region_add_subregion(sysmem, base, cpld_memory);
>> - qemu_register_reset(&taihu_cpld_reset, cpld);
>> -}
>> -
>> -static void taihu_405ep_init(MachineState *machine)
>> -{
>> - MachineClass *mc = MACHINE_GET_CLASS(machine);
>> - const char *bios_name = machine->firmware ?: BIOS_FILENAME;
>> - const char *kernel_filename = machine->kernel_filename;
>> - const char *initrd_filename = machine->initrd_filename;
>> - char *filename;
>> - MemoryRegion *sysmem = get_system_memory();
>> - MemoryRegion *bios;
>> - MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
>> - hwaddr ram_bases[2], ram_sizes[2];
>> - long bios_size;
>> - target_ulong kernel_base, initrd_base;
>> - long kernel_size, initrd_size;
>> - int linux_boot;
>> - int fl_idx;
>> - DriveInfo *dinfo;
>> - DeviceState *uicdev;
>> -
>> - if (machine->ram_size != mc->default_ram_size) {
>> - char *sz = size_to_str(mc->default_ram_size);
>> - error_report("Invalid RAM size, should be %s", sz);
>> - g_free(sz);
>> - exit(EXIT_FAILURE);
>> - }
>> -
>> - ram_bases[0] = 0;
>> - ram_sizes[0] = 0x04000000;
>> - memory_region_init_alias(&ram_memories[0], NULL,
>> - "taihu_405ep.ram-0", machine->ram, ram_bases[0],
>> - ram_sizes[0]);
>> - ram_bases[1] = 0x04000000;
>> - ram_sizes[1] = 0x04000000;
>> - memory_region_init_alias(&ram_memories[1], NULL,
>> - "taihu_405ep.ram-1", machine->ram, ram_bases[1],
>> - ram_sizes[1]);
>> - ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
>> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>> - /* allocate and load BIOS */
>> - fl_idx = 0;
>> -#if defined(USE_FLASH_BIOS)
>> - dinfo = drive_get(IF_PFLASH, 0, fl_idx);
>> - if (dinfo) {
>> - bios_size = 2 * MiB;
>> - pflash_cfi02_register(0xFFE00000,
>> - "taihu_405ep.bios", bios_size,
>> - blk_by_legacy_dinfo(dinfo),
>> - 64 * KiB, 1,
>> - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
>> - 1);
>> - fl_idx++;
>> - } else
>> -#endif
>> - {
>> - bios = g_new(MemoryRegion, 1);
>> - memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
>> - &error_fatal);
>> - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
>> - if (filename) {
>> - bios_size = load_image_size(filename,
>> - memory_region_get_ram_ptr(bios),
>> - BIOS_SIZE);
>> - g_free(filename);
>> - if (bios_size < 0) {
>> - error_report("Could not load PowerPC BIOS '%s'", bios_name);
>> - exit(1);
>> - }
>> - bios_size = (bios_size + 0xfff) & ~0xfff;
>> - memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
>> - } else if (!qtest_enabled()) {
>> - error_report("Could not load PowerPC BIOS '%s'", bios_name);
>> - exit(1);
>> - }
>> - }
>> - /* Register Linux flash */
>> - dinfo = drive_get(IF_PFLASH, 0, fl_idx);
>> - if (dinfo) {
>> - bios_size = 32 * MiB;
>> - pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
>> - blk_by_legacy_dinfo(dinfo),
>> - 64 * KiB, 1,
>> - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
>> - 1);
>> - fl_idx++;
>> - }
>> - /* Register CLPD & LCD display */
>> - taihu_cpld_init(sysmem, 0x50100000);
>> - /* Load kernel */
>> - linux_boot = (kernel_filename != NULL);
>> - if (linux_boot) {
>> - kernel_base = KERNEL_LOAD_ADDR;
>> - /* now we can load the kernel */
>> - kernel_size = load_image_targphys(kernel_filename, kernel_base,
>> - machine->ram_size - kernel_base);
>> - if (kernel_size < 0) {
>> - error_report("could not load kernel '%s'", kernel_filename);
>> - exit(1);
>> - }
>> - /* load initrd */
>> - if (initrd_filename) {
>> - initrd_base = INITRD_LOAD_ADDR;
>> - initrd_size = load_image_targphys(initrd_filename, initrd_base,
>> - machine->ram_size - initrd_base);
>> - if (initrd_size < 0) {
>> - error_report("could not load initial ram disk '%s'",
>> - initrd_filename);
>> - exit(1);
>> - }
>> - } else {
>> - initrd_base = 0;
>> - initrd_size = 0;
>> - }
>> - } else {
>> - kernel_base = 0;
>> - kernel_size = 0;
>> - initrd_base = 0;
>> - initrd_size = 0;
>> - }
>> -}
>> -
>> -static void taihu_class_init(ObjectClass *oc, void *data)
>> -{
>> - MachineClass *mc = MACHINE_CLASS(oc);
>> -
>> - mc->desc = "taihu";
>> - mc->init = taihu_405ep_init;
>> - mc->default_ram_size = 0x08000000;
>> - mc->default_ram_id = "taihu_405ep.ram";
>> - mc->deprecation_reason = "incomplete, use 'ref405ep' instead";
>> -}
>> -
>> -static const TypeInfo taihu_type = {
>> - .name = MACHINE_TYPE_NAME("taihu"),
>> - .parent = TYPE_MACHINE,
>> - .class_init = taihu_class_init,
>> -};
>> -
>> static void ppc405_machine_init(void)
>> {
>> type_register_static(&ref405ep_type);
>> - type_register_static(&taihu_type);
>> }
>> type_init(ppc405_machine_init)
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 02/19] ppc/ppc405: Introduce a PPC405 generic machine
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
2022-08-01 13:10 ` [PATCH 01/19] ppc/ppc405: Remove taihu machine Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-02 19:07 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 03/19] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
` (16 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
We will use this machine as a base to define the ref405ep and possibly
the PPC405 hotfoot board as found in the Linux kernel.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1a4e7588c584..4c269b6526a5 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -50,6 +50,15 @@
#define USE_FLASH_BIOS
+struct Ppc405MachineState {
+ /* Private */
+ MachineState parent_obj;
+ /* Public */
+};
+
+#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
+
/*****************************************************************************/
/* PPC405EP reference board (IBM) */
/* Standalone board with:
@@ -332,18 +341,34 @@ static void ref405ep_class_init(ObjectClass *oc, void *data)
mc->desc = "ref405ep";
mc->init = ref405ep_init;
- mc->default_ram_size = 0x08000000;
- mc->default_ram_id = "ef405ep.ram";
}
static const TypeInfo ref405ep_type = {
.name = MACHINE_TYPE_NAME("ref405ep"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_PPC405_MACHINE,
.class_init = ref405ep_class_init,
};
+static void ppc405_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "PPC405 generic machine";
+ mc->default_ram_size = 0x08000000;
+ mc->default_ram_id = "ppc405.ram";
+}
+
+static const TypeInfo ppc405_machine_type = {
+ .name = TYPE_PPC405_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(Ppc405MachineState),
+ .class_init = ppc405_machine_class_init,
+ .abstract = true,
+};
+
static void ppc405_machine_init(void)
{
+ type_register_static(&ppc405_machine_type);
type_register_static(&ref405ep_type);
}
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 02/19] ppc/ppc405: Introduce a PPC405 generic machine
2022-08-01 13:10 ` [PATCH 02/19] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
@ 2022-08-02 19:07 ` Daniel Henrique Barboza
2022-08-03 7:34 ` Cédric Le Goater
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-02 19:07 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> We will use this machine as a base to define the ref405ep and possibly
> the PPC405 hotfoot board as found in the Linux kernel.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405_boards.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 1a4e7588c584..4c269b6526a5 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -50,6 +50,15 @@
>
> #define USE_FLASH_BIOS
>
> +struct Ppc405MachineState {
> + /* Private */
> + MachineState parent_obj;
> + /* Public */
> +};
> +
> +#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
> +
> /*****************************************************************************/
> /* PPC405EP reference board (IBM) */
> /* Standalone board with:
> @@ -332,18 +341,34 @@ static void ref405ep_class_init(ObjectClass *oc, void *data)
>
> mc->desc = "ref405ep";
> mc->init = ref405ep_init;
> - mc->default_ram_size = 0x08000000;
> - mc->default_ram_id = "ef405ep.ram";
> }
>
> static const TypeInfo ref405ep_type = {
> .name = MACHINE_TYPE_NAME("ref405ep"),
> - .parent = TYPE_MACHINE,
> + .parent = TYPE_PPC405_MACHINE,
> .class_init = ref405ep_class_init,
> };
>
> +static void ppc405_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> + mc->desc = "PPC405 generic machine";
> + mc->default_ram_size = 0x08000000;
> + mc->default_ram_id = "ppc405.ram";
I don't mind changing the default_ram_id from "ef405ep.ram" to "ppc405.ram",
but since we're renaming it, might as well rename the remaining instances
of ef405ep.ram:
$ git grep 'ef405ep.ram'
hw/ppc/ppc405_uc.c: "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
hw/ppc/ppc405_uc.c: memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
I believe these can be renamed to "ppc405.ram.alias" and "ppc405.ram1" in
patch 05.
Thanks,
Daniel
> +}
> +
> +static const TypeInfo ppc405_machine_type = {
> + .name = TYPE_PPC405_MACHINE,
> + .parent = TYPE_MACHINE,
> + .instance_size = sizeof(Ppc405MachineState),
> + .class_init = ppc405_machine_class_init,
> + .abstract = true,
> +};
> +
> static void ppc405_machine_init(void)
> {
> + type_register_static(&ppc405_machine_type);
> type_register_static(&ref405ep_type);
> }
>
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 02/19] ppc/ppc405: Introduce a PPC405 generic machine
2022-08-02 19:07 ` Daniel Henrique Barboza
@ 2022-08-03 7:34 ` Cédric Le Goater
0 siblings, 0 replies; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-03 7:34 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/2/22 21:07, Daniel Henrique Barboza wrote:
>
>
> On 8/1/22 10:10, Cédric Le Goater wrote:
>> We will use this machine as a base to define the ref405ep and possibly
>> the PPC405 hotfoot board as found in the Linux kernel.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405_boards.c | 31 ++++++++++++++++++++++++++++---
>> 1 file changed, 28 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 1a4e7588c584..4c269b6526a5 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -50,6 +50,15 @@
>> #define USE_FLASH_BIOS
>> +struct Ppc405MachineState {
>> + /* Private */
>> + MachineState parent_obj;
>> + /* Public */
>> +};
>> +
>> +#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
>> +
>> /*****************************************************************************/
>> /* PPC405EP reference board (IBM) */
>> /* Standalone board with:
>> @@ -332,18 +341,34 @@ static void ref405ep_class_init(ObjectClass *oc, void *data)
>> mc->desc = "ref405ep";
>> mc->init = ref405ep_init;
>> - mc->default_ram_size = 0x08000000;
>> - mc->default_ram_id = "ef405ep.ram";
>> }
>> static const TypeInfo ref405ep_type = {
>> .name = MACHINE_TYPE_NAME("ref405ep"),
>> - .parent = TYPE_MACHINE,
>> + .parent = TYPE_PPC405_MACHINE,
>> .class_init = ref405ep_class_init,
>> };
>> +static void ppc405_machine_class_init(ObjectClass *oc, void *data)
>> +{
>> + MachineClass *mc = MACHINE_CLASS(oc);
>> +
>> + mc->desc = "PPC405 generic machine";
>> + mc->default_ram_size = 0x08000000;
>> + mc->default_ram_id = "ppc405.ram";
>
>
> I don't mind changing the default_ram_id from "ef405ep.ram" to "ppc405.ram",
> but since we're renaming it, might as well rename the remaining instances
> of ef405ep.ram:
>
> $ git grep 'ef405ep.ram'
> hw/ppc/ppc405_uc.c: "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
> hw/ppc/ppc405_uc.c: memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
Sure. I will clean that up also.
Thanks,
C.
>
> I believe these can be renamed to "ppc405.ram.alias" and "ppc405.ram1" in
> patch 05.
>
>
> Thanks,
>
>
> Daniel
>
>
>> +}
>> +
>> +static const TypeInfo ppc405_machine_type = {
>> + .name = TYPE_PPC405_MACHINE,
>> + .parent = TYPE_MACHINE,
>> + .instance_size = sizeof(Ppc405MachineState),
>> + .class_init = ppc405_machine_class_init,
>> + .abstract = true,
>> +};
>> +
>> static void ppc405_machine_init(void)
>> {
>> + type_register_static(&ppc405_machine_type);
>> type_register_static(&ref405ep_type);
>> }
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 03/19] ppc/ppc405: Move devices under the ref405ep machine
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
2022-08-01 13:10 ` [PATCH 01/19] ppc/ppc405: Remove taihu machine Cédric Le Goater
2022-08-01 13:10 ` [PATCH 02/19] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-02 19:08 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 04/19] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
` (15 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 31 +++++++++++++++++++------------
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 4c269b6526a5..24ec948d22a4 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -230,13 +230,11 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
env->load_info = &boot_info;
}
-static void ref405ep_init(MachineState *machine)
+static void ppc405_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
- DeviceState *dev;
- SysBusDevice *s;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
@@ -294,15 +292,6 @@ static void ref405ep_init(MachineState *machine)
memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
}
- /* Register FPGA */
- ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
- /* Register NVRAM */
- dev = qdev_new("sysbus-m48t08");
- qdev_prop_set_int32(dev, "base-year", 1968);
- s = SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
-
/* Load kernel and initrd using U-Boot images */
if (kernel_filename && machine->firmware) {
target_ulong kernel_base, initrd_base;
@@ -335,6 +324,23 @@ static void ref405ep_init(MachineState *machine)
}
}
+static void ref405ep_init(MachineState *machine)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+
+ ppc405_init(machine);
+
+ /* Register FPGA */
+ ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
+ /* Register NVRAM */
+ dev = qdev_new("sysbus-m48t08");
+ qdev_prop_set_int32(dev, "base-year", 1968);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
+}
+
static void ref405ep_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -354,6 +360,7 @@ static void ppc405_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "PPC405 generic machine";
+ mc->init = ppc405_init;
mc->default_ram_size = 0x08000000;
mc->default_ram_id = "ppc405.ram";
}
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 03/19] ppc/ppc405: Move devices under the ref405ep machine
2022-08-01 13:10 ` [PATCH 03/19] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
@ 2022-08-02 19:08 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-02 19:08 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405_boards.c | 31 +++++++++++++++++++------------
> 1 file changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 4c269b6526a5..24ec948d22a4 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -230,13 +230,11 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
> env->load_info = &boot_info;
> }
>
> -static void ref405ep_init(MachineState *machine)
> +static void ppc405_init(MachineState *machine)
> {
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> PowerPCCPU *cpu;
> - DeviceState *dev;
> - SysBusDevice *s;
> MemoryRegion *sram = g_new(MemoryRegion, 1);
> MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
> hwaddr ram_bases[2], ram_sizes[2];
> @@ -294,15 +292,6 @@ static void ref405ep_init(MachineState *machine)
> memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
> }
>
> - /* Register FPGA */
> - ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
> - /* Register NVRAM */
> - dev = qdev_new("sysbus-m48t08");
> - qdev_prop_set_int32(dev, "base-year", 1968);
> - s = SYS_BUS_DEVICE(dev);
> - sysbus_realize_and_unref(s, &error_fatal);
> - sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
> -
> /* Load kernel and initrd using U-Boot images */
> if (kernel_filename && machine->firmware) {
> target_ulong kernel_base, initrd_base;
> @@ -335,6 +324,23 @@ static void ref405ep_init(MachineState *machine)
> }
> }
>
> +static void ref405ep_init(MachineState *machine)
> +{
> + DeviceState *dev;
> + SysBusDevice *s;
> +
> + ppc405_init(machine);
> +
> + /* Register FPGA */
> + ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
> + /* Register NVRAM */
> + dev = qdev_new("sysbus-m48t08");
> + qdev_prop_set_int32(dev, "base-year", 1968);
> + s = SYS_BUS_DEVICE(dev);
> + sysbus_realize_and_unref(s, &error_fatal);
> + sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
> +}
> +
> static void ref405ep_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -354,6 +360,7 @@ static void ppc405_machine_class_init(ObjectClass *oc, void *data)
> MachineClass *mc = MACHINE_CLASS(oc);
>
> mc->desc = "PPC405 generic machine";
> + mc->init = ppc405_init;
> mc->default_ram_size = 0x08000000;
> mc->default_ram_id = "ppc405.ram";
> }
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 04/19] ppc/ppc405: Introduce a PPC405 SoC
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (2 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 03/19] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-02 19:18 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
` (14 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
It is an initial model to start QOMification of the PPC405 board.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 17 ++++++++++++++
hw/ppc/ppc405_boards.c | 29 ++++++++++-------------
hw/ppc/ppc405_uc.c | 53 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 82 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 83f156f585c8..c8cddb71733a 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -25,6 +25,7 @@
#ifndef PPC405_H
#define PPC405_H
+#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#define PPC405EP_SDRAM_BASE 0x00000000
@@ -62,6 +63,22 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_SOC "ppc405-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
+
+struct Ppc405SoCState {
+ /* Private */
+ DeviceState parent_obj;
+
+ /* Public */
+ MemoryRegion sram;
+ MemoryRegion ram_memories[2];
+ hwaddr ram_bases[2], ram_sizes[2];
+
+ MemoryRegion *dram_mr;
+ hwaddr ram_size;
+};
+
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 24ec948d22a4..96db52c5a309 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -54,6 +54,8 @@ struct Ppc405MachineState {
/* Private */
MachineState parent_obj;
/* Public */
+
+ Ppc405SoCState soc;
};
#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
@@ -232,12 +234,10 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
+ Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
- MemoryRegion *sram = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
- hwaddr ram_bases[2], ram_sizes[2];
MemoryRegion *sysmem = get_system_memory();
DeviceState *uicdev;
@@ -248,23 +248,18 @@ static void ppc405_init(MachineState *machine)
exit(EXIT_FAILURE);
}
- /* XXX: fix this */
- memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
- machine->ram, 0, machine->ram_size);
- ram_bases[0] = 0;
- ram_sizes[0] = machine->ram_size;
- memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
- ram_bases[1] = 0x00000000;
- ram_sizes[1] = 0x00000000;
+ object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
+ TYPE_PPC405_SOC);
+ object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
+ machine->ram_size, &error_fatal);
+ object_property_set_link(OBJECT(&ppc405->soc), "dram",
+ OBJECT(machine->ram), &error_abort);
+ qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
- cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
+ cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
+ ppc405->soc.ram_sizes,
33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
- /* allocate SRAM */
- memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
- &error_fatal);
- memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d6420c88d3a6..156e839b8283 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -30,6 +30,7 @@
#include "hw/ppc/ppc.h"
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "ppc405.h"
#include "hw/char/serial.h"
#include "qemu/timer.h"
@@ -1530,3 +1531,55 @@ PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
return cpu;
}
+
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405SoCState *s = PPC405_SOC(dev);
+ Error *err = NULL;
+
+ /* XXX: fix this ? */
+ memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
+ "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
+ s->ram_bases[0] = 0;
+ s->ram_sizes[0] = s->ram_size;
+ memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
+ s->ram_bases[1] = 0x00000000;
+ s->ram_sizes[1] = 0x00000000;
+
+ /* allocate SRAM */
+ memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
+ PPC405EP_SRAM_SIZE, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
+ &s->sram);
+}
+
+static Property ppc405_soc_properties[] = {
+ DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_soc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_soc_realize;
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc405_soc_properties);
+}
+
+static const TypeInfo ppc405_types[] = {
+ {
+ .name = TYPE_PPC405_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405SoCState),
+ .class_init = ppc405_soc_class_init,
+ }
+};
+
+DEFINE_TYPES(ppc405_types)
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 04/19] ppc/ppc405: Introduce a PPC405 SoC
2022-08-01 13:10 ` [PATCH 04/19] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
@ 2022-08-02 19:18 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-02 19:18 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> It is an initial model to start QOMification of the PPC405 board.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 17 ++++++++++++++
> hw/ppc/ppc405_boards.c | 29 ++++++++++-------------
> hw/ppc/ppc405_uc.c | 53 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 82 insertions(+), 17 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 83f156f585c8..c8cddb71733a 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -25,6 +25,7 @@
> #ifndef PPC405_H
> #define PPC405_H
>
> +#include "qom/object.h"
> #include "hw/ppc/ppc4xx.h"
>
> #define PPC405EP_SDRAM_BASE 0x00000000
> @@ -62,6 +63,22 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> +#define TYPE_PPC405_SOC "ppc405-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
> +
> +struct Ppc405SoCState {
> + /* Private */
> + DeviceState parent_obj;
> +
> + /* Public */
> + MemoryRegion sram;
> + MemoryRegion ram_memories[2];
> + hwaddr ram_bases[2], ram_sizes[2];
> +
> + MemoryRegion *dram_mr;
> + hwaddr ram_size;
> +};
> +
> /* PowerPC 405 core */
> ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 24ec948d22a4..96db52c5a309 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -54,6 +54,8 @@ struct Ppc405MachineState {
> /* Private */
> MachineState parent_obj;
> /* Public */
> +
> + Ppc405SoCState soc;
> };
>
> #define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
> @@ -232,12 +234,10 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
>
> static void ppc405_init(MachineState *machine)
> {
> + Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> PowerPCCPU *cpu;
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> - MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
> - hwaddr ram_bases[2], ram_sizes[2];
> MemoryRegion *sysmem = get_system_memory();
> DeviceState *uicdev;
>
> @@ -248,23 +248,18 @@ static void ppc405_init(MachineState *machine)
> exit(EXIT_FAILURE);
> }
>
> - /* XXX: fix this */
> - memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
> - machine->ram, 0, machine->ram_size);
> - ram_bases[0] = 0;
> - ram_sizes[0] = machine->ram_size;
> - memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
> - ram_bases[1] = 0x00000000;
> - ram_sizes[1] = 0x00000000;
> + object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
> + TYPE_PPC405_SOC);
> + object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
> + machine->ram_size, &error_fatal);
> + object_property_set_link(OBJECT(&ppc405->soc), "dram",
> + OBJECT(machine->ram), &error_abort);
> + qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>
> - cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
> + cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
> + ppc405->soc.ram_sizes,
> 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>
> - /* allocate SRAM */
> - memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
> - &error_fatal);
> - memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
> -
> /* allocate and load BIOS */
> if (machine->firmware) {
> MemoryRegion *bios = g_new(MemoryRegion, 1);
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index d6420c88d3a6..156e839b8283 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -30,6 +30,7 @@
> #include "hw/ppc/ppc.h"
> #include "hw/i2c/ppc4xx_i2c.h"
> #include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> #include "ppc405.h"
> #include "hw/char/serial.h"
> #include "qemu/timer.h"
> @@ -1530,3 +1531,55 @@ PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>
> return cpu;
> }
> +
> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> +{
> + Ppc405SoCState *s = PPC405_SOC(dev);
> + Error *err = NULL;
> +
> + /* XXX: fix this ? */
> + memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
> + "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
> + s->ram_bases[0] = 0;
> + s->ram_sizes[0] = s->ram_size;
> + memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
> + s->ram_bases[1] = 0x00000000;
> + s->ram_sizes[1] = 0x00000000;
> +
> + /* allocate SRAM */
> + memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
> + PPC405EP_SRAM_SIZE, &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
> + &s->sram);
> +}
> +
> +static Property ppc405_soc_properties[] = {
> + DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> + MemoryRegion *),
> + DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_soc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_soc_realize;
> + dc->user_creatable = false;
> + device_class_set_props(dc, ppc405_soc_properties);
> +}
> +
> +static const TypeInfo ppc405_types[] = {
> + {
> + .name = TYPE_PPC405_SOC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(Ppc405SoCState),
> + .class_init = ppc405_soc_class_init,
> + }
> +};
> +
> +DEFINE_TYPES(ppc405_types)
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (3 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 04/19] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-02 19:18 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 06/19] ppc/ppc405: QOM'ify CPU Cédric Le Goater
` (13 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize().
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 12 ++--
hw/ppc/ppc405_boards.c | 12 ++--
hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
3 files changed, 84 insertions(+), 91 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c8cddb71733a..5e4e96d86ceb 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -74,9 +74,14 @@ struct Ppc405SoCState {
MemoryRegion sram;
MemoryRegion ram_memories[2];
hwaddr ram_bases[2], ram_sizes[2];
+ bool do_dram_init;
MemoryRegion *dram_mr;
hwaddr ram_size;
+
+ uint32_t sysclk;
+ PowerPCCPU *cpu;
+ DeviceState *uic;
};
/* PowerPC 405 core */
@@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
void ppc405_ebc_init(CPUPPCState *env);
-PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
- MemoryRegion ram_memories[2],
- hwaddr ram_bases[2],
- hwaddr ram_sizes[2],
- uint32_t sysclk, DeviceState **uicdev,
- int do_init);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 96db52c5a309..363cb0770506 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
- PowerPCCPU *cpu;
MemoryRegion *sysmem = get_system_memory();
- DeviceState *uicdev;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
+ object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
+ !(kernel_filename == NULL), &error_abort);
+ object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
+ &error_abort);
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
- cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
- ppc405->soc.ram_sizes,
- 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
@@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- boot_from_kernel(machine, cpu);
+ boot_from_kernel(machine, ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 156e839b8283..59612504bf3f 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
#endif
}
-PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
- MemoryRegion ram_memories[2],
- hwaddr ram_bases[2],
- hwaddr ram_sizes[2],
- uint32_t sysclk, DeviceState **uicdevp,
- int do_init)
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
+ Ppc405SoCState *s = PPC405_SOC(dev);
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
- PowerPCCPU *cpu;
CPUPPCState *env;
- DeviceState *uicdev;
- SysBusDevice *uicsbd;
+ Error *err = NULL;
+
+ /* XXX: fix this ? */
+ memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
+ "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
+ s->ram_bases[0] = 0;
+ s->ram_sizes[0] = s->ram_size;
+ memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
+ s->ram_bases[1] = 0x00000000;
+ s->ram_sizes[1] = 0x00000000;
+
+ /* allocate SRAM */
+ memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
+ PPC405EP_SRAM_SIZE, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
+ &s->sram);
memset(clk_setup, 0, sizeof(clk_setup));
+
/* init CPUs */
- cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
+ s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
&clk_setup[PPC405EP_CPU_CLK],
- &tlb_clk_setup, sysclk);
- env = &cpu->env;
+ &tlb_clk_setup, s->sysclk);
+ env = &s->cpu->env;
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
- /* Internal devices init */
- /* Memory mapped devices registers */
+
+ /* CPU control */
+ ppc405ep_cpc_init(env, clk_setup, s->sysclk);
+
/* PLB arbitrer */
ppc4xx_plb_init(env);
+
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
+
/* OBP arbitrer */
ppc4xx_opba_init(0xef600600);
+
/* Universal interrupt controller */
- uicdev = qdev_new(TYPE_PPC_UIC);
- uicsbd = SYS_BUS_DEVICE(uicdev);
+ s->uic = qdev_new(TYPE_PPC_UIC);
- object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
+ object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
&error_fatal);
- sysbus_realize_and_unref(uicsbd, &error_fatal);
-
- sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
- qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
- sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
- qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
+ if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
+ return;
+ }
- *uicdevp = uicdev;
+ sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
+ qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
+ sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
+ qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- /* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
- ram_bases, ram_sizes, do_init);
+ /* XXX 405EP has no ECC interrupt */
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 2, s->ram_memories,
+ s->ram_bases, s->ram_sizes, s->do_dram_init);
+
/* External bus controller */
ppc405_ebc_init(env);
+
/* DMA controller */
- dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
- dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
- dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
- dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
+ dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
+ dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
+ dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
+ dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
ppc405_dma_init(env, dma_irqs);
- /* IIC controller */
+
+ /* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(uicdev, 2));
+ qdev_get_gpio_in(s->uic, 2));
/* GPIO */
ppc405_gpio_init(0xef600700);
+
/* Serial ports */
if (serial_hd(0) != NULL) {
- serial_mm_init(address_space_mem, 0xef600300, 0,
- qdev_get_gpio_in(uicdev, 0),
+ serial_mm_init(get_system_memory(), 0xef600300, 0,
+ qdev_get_gpio_in(s->uic, 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
- serial_mm_init(address_space_mem, 0xef600400, 0,
- qdev_get_gpio_in(uicdev, 1),
+ serial_mm_init(get_system_memory(), 0xef600400, 0,
+ qdev_get_gpio_in(s->uic, 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
+
/* OCM */
ppc405_ocm_init(env);
+
/* GPT */
- gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
- gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
- gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
- gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
- gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
+ gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
+ gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
+ gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
+ gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
+ gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
ppc4xx_gpt_init(0xef600000, gpt_irqs);
- /* PCI */
- /* Uses UIC IRQs 3, 16, 18 */
+
/* MAL */
- mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
- mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
- mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
- mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
+ mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
+ mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
+ mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
+ mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
ppc4xx_mal_init(env, 4, 2, mal_irqs);
+
/* Ethernet */
/* Uses UIC IRQs 9, 15, 17 */
- /* CPU control */
- ppc405ep_cpc_init(env, clk_setup, sysclk);
-
- return cpu;
-}
-
-static void ppc405_soc_realize(DeviceState *dev, Error **errp)
-{
- Ppc405SoCState *s = PPC405_SOC(dev);
- Error *err = NULL;
-
- /* XXX: fix this ? */
- memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
- "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
- s->ram_bases[0] = 0;
- s->ram_sizes[0] = s->ram_size;
- memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
- s->ram_bases[1] = 0x00000000;
- s->ram_sizes[1] = 0x00000000;
-
- /* allocate SRAM */
- memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
- PPC405EP_SRAM_SIZE, &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
- memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
- &s->sram);
}
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
+ DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
+ DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-01 13:10 ` [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
@ 2022-08-02 19:18 ` Daniel Henrique Barboza
2022-08-02 21:24 ` BALATON Zoltan
2022-08-03 8:03 ` Cédric Le Goater
0 siblings, 2 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-02 19:18 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> This moves all the code previously done in the ppc405ep_init() routine
> under ppc405_soc_realize().
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 12 ++--
> hw/ppc/ppc405_boards.c | 12 ++--
> hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
> 3 files changed, 84 insertions(+), 91 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index c8cddb71733a..5e4e96d86ceb 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -74,9 +74,14 @@ struct Ppc405SoCState {
> MemoryRegion sram;
> MemoryRegion ram_memories[2];
> hwaddr ram_bases[2], ram_sizes[2];
> + bool do_dram_init;
>
> MemoryRegion *dram_mr;
> hwaddr ram_size;
> +
> + uint32_t sysclk;
> + PowerPCCPU *cpu;
> + DeviceState *uic;
> };
>
> /* PowerPC 405 core */
> @@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
> void ppc4xx_plb_init(CPUPPCState *env);
> void ppc405_ebc_init(CPUPPCState *env);
>
> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
> - MemoryRegion ram_memories[2],
> - hwaddr ram_bases[2],
> - hwaddr ram_sizes[2],
> - uint32_t sysclk, DeviceState **uicdev,
> - int do_init);
> -
> #endif /* PPC405_H */
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 96db52c5a309..363cb0770506 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> - PowerPCCPU *cpu;
> MemoryRegion *sysmem = get_system_memory();
> - DeviceState *uicdev;
>
> if (machine->ram_size != mc->default_ram_size) {
> char *sz = size_to_str(mc->default_ram_size);
> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
> machine->ram_size, &error_fatal);
> object_property_set_link(OBJECT(&ppc405->soc), "dram",
> OBJECT(machine->ram), &error_abort);
> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
> + !(kernel_filename == NULL), &error_abort);
> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
> + &error_abort);
> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>
> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
> - ppc405->soc.ram_sizes,
> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
> -
> /* allocate and load BIOS */
> if (machine->firmware) {
> MemoryRegion *bios = g_new(MemoryRegion, 1);
> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>
> /* Load ELF kernel and rootfs.cpio */
> } else if (kernel_filename && !machine->firmware) {
> - boot_from_kernel(machine, cpu);
> + boot_from_kernel(machine, ppc405->soc.cpu);
> }
> }
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 156e839b8283..59612504bf3f 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
> #endif
> }
>
> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
> - MemoryRegion ram_memories[2],
> - hwaddr ram_bases[2],
> - hwaddr ram_sizes[2],
> - uint32_t sysclk, DeviceState **uicdevp,
> - int do_init)
> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> + Ppc405SoCState *s = PPC405_SOC(dev);
> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> - PowerPCCPU *cpu;
> CPUPPCState *env;
> - DeviceState *uicdev;
> - SysBusDevice *uicsbd;
> + Error *err = NULL;
> +
> + /* XXX: fix this ? */
So, this comment, originally from ppc405_boards.c, was added by commit
1a6c088620368 and it seemed to make reference to something with the refering
to the ram_* values:
/* XXX: fix this */
ram_bases[0] = 0x00000000;
ram_sizes[0] = 0x08000000;
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
(...)
No more context is provided aside from a git-svn-id from savannah.nongnu.org.
If no one can provide more context about what is to be fixed here, I'll
remove the comment.
> + memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
> + "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
As I mentioned in patch 2, ef405ep.ram.alias can be renamed to ppc405.ram.alias ...
> + s->ram_bases[0] = 0;
> + s->ram_sizes[0] = s->ram_size;
> + memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
And this can be renamed to ef405ep.ram1. If you agree with the rename I
can amend it in the tree.
Thanks,
Daniel
> + s->ram_bases[1] = 0x00000000;
> + s->ram_sizes[1] = 0x00000000;
> +
> + /* allocate SRAM */
> + memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
> + PPC405EP_SRAM_SIZE, &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
> + &s->sram);
>
> memset(clk_setup, 0, sizeof(clk_setup));
> +
> /* init CPUs */
> - cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
> + s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
> &clk_setup[PPC405EP_CPU_CLK],
> - &tlb_clk_setup, sysclk);
> - env = &cpu->env;
> + &tlb_clk_setup, s->sysclk);
> + env = &s->cpu->env;
> clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
> clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
> - /* Internal devices init */
> - /* Memory mapped devices registers */
> +
> + /* CPU control */
> + ppc405ep_cpc_init(env, clk_setup, s->sysclk);
> +
> /* PLB arbitrer */
> ppc4xx_plb_init(env);
> +
> /* PLB to OPB bridge */
> ppc4xx_pob_init(env);
> +
> /* OBP arbitrer */
> ppc4xx_opba_init(0xef600600);
> +
> /* Universal interrupt controller */
> - uicdev = qdev_new(TYPE_PPC_UIC);
> - uicsbd = SYS_BUS_DEVICE(uicdev);
> + s->uic = qdev_new(TYPE_PPC_UIC);
>
> - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
> &error_fatal);
> - sysbus_realize_and_unref(uicsbd, &error_fatal);
> -
> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
> + if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
> + return;
> + }
>
> - *uicdevp = uicdev;
> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> - /* XXX 405EP has no ECC interrupt */
> - ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
> - ram_bases, ram_sizes, do_init);
> + /* XXX 405EP has no ECC interrupt */
> + ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 2, s->ram_memories,
> + s->ram_bases, s->ram_sizes, s->do_dram_init);
> +
> /* External bus controller */
> ppc405_ebc_init(env);
> +
> /* DMA controller */
> - dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
> - dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
> - dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
> - dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
> + dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
> + dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
> + dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
> + dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
> ppc405_dma_init(env, dma_irqs);
> - /* IIC controller */
> +
> + /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> - qdev_get_gpio_in(uicdev, 2));
> + qdev_get_gpio_in(s->uic, 2));
> /* GPIO */
> ppc405_gpio_init(0xef600700);
> +
> /* Serial ports */
> if (serial_hd(0) != NULL) {
> - serial_mm_init(address_space_mem, 0xef600300, 0,
> - qdev_get_gpio_in(uicdev, 0),
> + serial_mm_init(get_system_memory(), 0xef600300, 0,
> + qdev_get_gpio_in(s->uic, 0),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
> DEVICE_BIG_ENDIAN);
> }
> if (serial_hd(1) != NULL) {
> - serial_mm_init(address_space_mem, 0xef600400, 0,
> - qdev_get_gpio_in(uicdev, 1),
> + serial_mm_init(get_system_memory(), 0xef600400, 0,
> + qdev_get_gpio_in(s->uic, 1),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
> DEVICE_BIG_ENDIAN);
> }
> +
> /* OCM */
> ppc405_ocm_init(env);
> +
> /* GPT */
> - gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
> - gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
> - gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
> - gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
> - gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
> + gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
> + gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
> + gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
> + gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
> + gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
> ppc4xx_gpt_init(0xef600000, gpt_irqs);
> - /* PCI */
> - /* Uses UIC IRQs 3, 16, 18 */
> +
> /* MAL */
> - mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
> - mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
> - mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
> - mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
> + mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
> + mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
> + mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
> + mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
> ppc4xx_mal_init(env, 4, 2, mal_irqs);
> +
> /* Ethernet */
> /* Uses UIC IRQs 9, 15, 17 */
> - /* CPU control */
> - ppc405ep_cpc_init(env, clk_setup, sysclk);
> -
> - return cpu;
> -}
> -
> -static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> -{
> - Ppc405SoCState *s = PPC405_SOC(dev);
> - Error *err = NULL;
> -
> - /* XXX: fix this ? */
> - memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
> - "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
> - s->ram_bases[0] = 0;
> - s->ram_sizes[0] = s->ram_size;
> - memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
> - s->ram_bases[1] = 0x00000000;
> - s->ram_sizes[1] = 0x00000000;
> -
> - /* allocate SRAM */
> - memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
> - PPC405EP_SRAM_SIZE, &err);
> - if (err) {
> - error_propagate(errp, err);
> - return;
> - }
> - memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
> - &s->sram);
> }
>
> static Property ppc405_soc_properties[] = {
> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> MemoryRegion *),
> + DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
> + DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-02 19:18 ` Daniel Henrique Barboza
@ 2022-08-02 21:24 ` BALATON Zoltan
2022-08-03 7:54 ` Cédric Le Goater
2022-08-03 9:23 ` Daniel Henrique Barboza
2022-08-03 8:03 ` Cédric Le Goater
1 sibling, 2 replies; 50+ messages in thread
From: BALATON Zoltan @ 2022-08-02 21:24 UTC (permalink / raw)
To: Daniel Henrique Barboza; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 5724 bytes --]
On Tue, 2 Aug 2022, Daniel Henrique Barboza wrote:
> On 8/1/22 10:10, Cédric Le Goater wrote:
>> This moves all the code previously done in the ppc405ep_init() routine
>> under ppc405_soc_realize().
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h | 12 ++--
>> hw/ppc/ppc405_boards.c | 12 ++--
>> hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
>> 3 files changed, 84 insertions(+), 91 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index c8cddb71733a..5e4e96d86ceb 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -74,9 +74,14 @@ struct Ppc405SoCState {
>> MemoryRegion sram;
>> MemoryRegion ram_memories[2];
>> hwaddr ram_bases[2], ram_sizes[2];
>> + bool do_dram_init;
>> MemoryRegion *dram_mr;
>> hwaddr ram_size;
>> +
>> + uint32_t sysclk;
>> + PowerPCCPU *cpu;
>> + DeviceState *uic;
>> };
>> /* PowerPC 405 core */
>> @@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env,
>> ram_addr_t ram_size);
>> void ppc4xx_plb_init(CPUPPCState *env);
>> void ppc405_ebc_init(CPUPPCState *env);
>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>> - MemoryRegion ram_memories[2],
>> - hwaddr ram_bases[2],
>> - hwaddr ram_sizes[2],
>> - uint32_t sysclk, DeviceState **uicdev,
>> - int do_init);
>> -
>> #endif /* PPC405_H */
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 96db52c5a309..363cb0770506 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>> const char *kernel_filename = machine->kernel_filename;
>> - PowerPCCPU *cpu;
>> MemoryRegion *sysmem = get_system_memory();
>> - DeviceState *uicdev;
>> if (machine->ram_size != mc->default_ram_size) {
>> char *sz = size_to_str(mc->default_ram_size);
>> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
>> machine->ram_size, &error_fatal);
>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>> OBJECT(machine->ram), &error_abort);
>> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>> + !(kernel_filename == NULL), &error_abort);
>> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>> + &error_abort);
>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories,
>> ppc405->soc.ram_bases,
>> - ppc405->soc.ram_sizes,
>> - 33333333, &uicdev, kernel_filename == NULL ? 0 :
>> 1);
>> -
>> /* allocate and load BIOS */
>> if (machine->firmware) {
>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>> /* Load ELF kernel and rootfs.cpio */
>> } else if (kernel_filename && !machine->firmware) {
>> - boot_from_kernel(machine, cpu);
>> + boot_from_kernel(machine, ppc405->soc.cpu);
>> }
>> }
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index 156e839b8283..59612504bf3f 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env,
>> clk_setup_t clk_setup[8],
>> #endif
>> }
>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>> - MemoryRegion ram_memories[2],
>> - hwaddr ram_bases[2],
>> - hwaddr ram_sizes[2],
>> - uint32_t sysclk, DeviceState **uicdevp,
>> - int do_init)
>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> {
>> + Ppc405SoCState *s = PPC405_SOC(dev);
>> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>> - PowerPCCPU *cpu;
>> CPUPPCState *env;
>> - DeviceState *uicdev;
>> - SysBusDevice *uicsbd;
>> + Error *err = NULL;
>> +
>> + /* XXX: fix this ? */
>
> So, this comment, originally from ppc405_boards.c, was added by commit
> 1a6c088620368 and it seemed to make reference to something with the refering
> to the ram_* values:
>
>
> /* XXX: fix this */
> ram_bases[0] = 0x00000000;
> ram_sizes[0] = 0x08000000;
> ram_bases[1] = 0x00000000;
> ram_sizes[1] = 0x00000000;
> (...)
>
>
> No more context is provided aside from a git-svn-id from savannah.nongnu.org.
>
> If no one can provide more context about what is to be fixed here, I'll
> remove the comment.
I'm not sure about it because I don't know 405 and only vaguely remember
how this was on 440/460EX but I think it might be that the memory
controller can be programmed to map RAM to different places but we don't
fully emulate that nor the different chunks/DIMM sockets that could be
possible and just map all system RAM to address 0 which is what most guest
firmware or OS does anyway. Maybe I'm wrong and don't remember this
correctly, the SDRAM controller model in ppc4xx_devs.c seems to do some
mapping but I think this is what the comment might refer to or something
similar. If so, I don't think it's worth emulating this more precisely
unless we know about a guest which needs this.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-02 21:24 ` BALATON Zoltan
@ 2022-08-03 7:54 ` Cédric Le Goater
2022-08-03 9:23 ` Daniel Henrique Barboza
1 sibling, 0 replies; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-03 7:54 UTC (permalink / raw)
To: BALATON Zoltan, Daniel Henrique Barboza; +Cc: qemu-ppc, qemu-devel
On 8/2/22 23:24, BALATON Zoltan wrote:
> On Tue, 2 Aug 2022, Daniel Henrique Barboza wrote:
>> On 8/1/22 10:10, Cédric Le Goater wrote:
>>> This moves all the code previously done in the ppc405ep_init() routine
>>> under ppc405_soc_realize().
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>> hw/ppc/ppc405.h | 12 ++--
>>> hw/ppc/ppc405_boards.c | 12 ++--
>>> hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
>>> 3 files changed, 84 insertions(+), 91 deletions(-)
>>>
>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>> index c8cddb71733a..5e4e96d86ceb 100644
>>> --- a/hw/ppc/ppc405.h
>>> +++ b/hw/ppc/ppc405.h
>>> @@ -74,9 +74,14 @@ struct Ppc405SoCState {
>>> MemoryRegion sram;
>>> MemoryRegion ram_memories[2];
>>> hwaddr ram_bases[2], ram_sizes[2];
>>> + bool do_dram_init;
>>> MemoryRegion *dram_mr;
>>> hwaddr ram_size;
>>> +
>>> + uint32_t sysclk;
>>> + PowerPCCPU *cpu;
>>> + DeviceState *uic;
>>> };
>>> /* PowerPC 405 core */
>>> @@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>>> void ppc4xx_plb_init(CPUPPCState *env);
>>> void ppc405_ebc_init(CPUPPCState *env);
>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>> - MemoryRegion ram_memories[2],
>>> - hwaddr ram_bases[2],
>>> - hwaddr ram_sizes[2],
>>> - uint32_t sysclk, DeviceState **uicdev,
>>> - int do_init);
>>> -
>>> #endif /* PPC405_H */
>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>> index 96db52c5a309..363cb0770506 100644
>>> --- a/hw/ppc/ppc405_boards.c
>>> +++ b/hw/ppc/ppc405_boards.c
>>> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
>>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>> const char *kernel_filename = machine->kernel_filename;
>>> - PowerPCCPU *cpu;
>>> MemoryRegion *sysmem = get_system_memory();
>>> - DeviceState *uicdev;
>>> if (machine->ram_size != mc->default_ram_size) {
>>> char *sz = size_to_str(mc->default_ram_size);
>>> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
>>> machine->ram_size, &error_fatal);
>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>> OBJECT(machine->ram), &error_abort);
>>> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>> + !(kernel_filename == NULL), &error_abort);
>>> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>> + &error_abort);
>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>>> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
>>> - ppc405->soc.ram_sizes,
>>> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>>> -
>>> /* allocate and load BIOS */
>>> if (machine->firmware) {
>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>>> /* Load ELF kernel and rootfs.cpio */
>>> } else if (kernel_filename && !machine->firmware) {
>>> - boot_from_kernel(machine, cpu);
>>> + boot_from_kernel(machine, ppc405->soc.cpu);
>>> }
>>> }
>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>> index 156e839b8283..59612504bf3f 100644
>>> --- a/hw/ppc/ppc405_uc.c
>>> +++ b/hw/ppc/ppc405_uc.c
>>> @@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
>>> #endif
>>> }
>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>> - MemoryRegion ram_memories[2],
>>> - hwaddr ram_bases[2],
>>> - hwaddr ram_sizes[2],
>>> - uint32_t sysclk, DeviceState **uicdevp,
>>> - int do_init)
>>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>> {
>>> + Ppc405SoCState *s = PPC405_SOC(dev);
>>> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>>> - PowerPCCPU *cpu;
>>> CPUPPCState *env;
>>> - DeviceState *uicdev;
>>> - SysBusDevice *uicsbd;
>>> + Error *err = NULL;
>>> +
>>> + /* XXX: fix this ? */
>>
>> So, this comment, originally from ppc405_boards.c, was added by commit
>> 1a6c088620368 and it seemed to make reference to something with the refering
>> to the ram_* values:
>>
>>
>> /* XXX: fix this */
>> ram_bases[0] = 0x00000000;
>> ram_sizes[0] = 0x08000000;
>> ram_bases[1] = 0x00000000;
>> ram_sizes[1] = 0x00000000;
>> (...)
>>
>>
>> No more context is provided aside from a git-svn-id from savannah.nongnu.org.
>>
>> If no one can provide more context about what is to be fixed here, I'll
>> remove the comment.
>
> I'm not sure about it because I don't know 405 and only vaguely remember how this was on 440/460EX but I think it might be that the memory controller can be programmed to map RAM to different places
Yes. See :
https://gitlab.com/huth/u-boot/-/blob/taihu/arch/powerpc/cpu/ppc4xx/sdram.c
Thomas had to hack the SDRAM init sequence for the QEMU machine to boot.
> but we don't fully emulate that nor the different chunks/DIMM sockets that could be possible and just map all system RAM to address 0 which is what most guest firmware or OS does anyway.
It feels like it. At least for the 405, only one bank is used :
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-0000000007ffffff (prio 0, i/o): sdram-containers
0000000000000000-0000000007ffffff (prio 0, ram): alias ef405ep.ram.alias @ppc405.ram 0000000000000000-0000000007ffffff
The machine allocates a set of memory regions which are aliases on the
machine RAM. These are passed to the SDRAM controller model which maps
and unmaps container regions depending on the register settings.
It could be simplified.
Thanks,
C.
> Maybe I'm wrong and don't remember this correctly, the SDRAM controller model in ppc4xx_devs.c seems to do some mapping but I think this is what the comment might refer to or something similar. If so, I don't think it's worth emulating this more precisely unless we know about a guest which needs this.
>
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-02 21:24 ` BALATON Zoltan
2022-08-03 7:54 ` Cédric Le Goater
@ 2022-08-03 9:23 ` Daniel Henrique Barboza
1 sibling, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:23 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
On 8/2/22 18:24, BALATON Zoltan wrote:
> On Tue, 2 Aug 2022, Daniel Henrique Barboza wrote:
>> On 8/1/22 10:10, Cédric Le Goater wrote:
>>> This moves all the code previously done in the ppc405ep_init() routine
>>> under ppc405_soc_realize().
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>> hw/ppc/ppc405.h | 12 ++--
>>> hw/ppc/ppc405_boards.c | 12 ++--
>>> hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
>>> 3 files changed, 84 insertions(+), 91 deletions(-)
>>>
>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>> index c8cddb71733a..5e4e96d86ceb 100644
>>> --- a/hw/ppc/ppc405.h
>>> +++ b/hw/ppc/ppc405.h
>>> @@ -74,9 +74,14 @@ struct Ppc405SoCState {
>>> MemoryRegion sram;
>>> MemoryRegion ram_memories[2];
>>> hwaddr ram_bases[2], ram_sizes[2];
>>> + bool do_dram_init;
>>> MemoryRegion *dram_mr;
>>> hwaddr ram_size;
>>> +
>>> + uint32_t sysclk;
>>> + PowerPCCPU *cpu;
>>> + DeviceState *uic;
>>> };
>>> /* PowerPC 405 core */
>>> @@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>>> void ppc4xx_plb_init(CPUPPCState *env);
>>> void ppc405_ebc_init(CPUPPCState *env);
>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>> - MemoryRegion ram_memories[2],
>>> - hwaddr ram_bases[2],
>>> - hwaddr ram_sizes[2],
>>> - uint32_t sysclk, DeviceState **uicdev,
>>> - int do_init);
>>> -
>>> #endif /* PPC405_H */
>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>> index 96db52c5a309..363cb0770506 100644
>>> --- a/hw/ppc/ppc405_boards.c
>>> +++ b/hw/ppc/ppc405_boards.c
>>> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
>>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>> const char *kernel_filename = machine->kernel_filename;
>>> - PowerPCCPU *cpu;
>>> MemoryRegion *sysmem = get_system_memory();
>>> - DeviceState *uicdev;
>>> if (machine->ram_size != mc->default_ram_size) {
>>> char *sz = size_to_str(mc->default_ram_size);
>>> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
>>> machine->ram_size, &error_fatal);
>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>> OBJECT(machine->ram), &error_abort);
>>> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>> + !(kernel_filename == NULL), &error_abort);
>>> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>> + &error_abort);
>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>>> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
>>> - ppc405->soc.ram_sizes,
>>> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>>> -
>>> /* allocate and load BIOS */
>>> if (machine->firmware) {
>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>>> /* Load ELF kernel and rootfs.cpio */
>>> } else if (kernel_filename && !machine->firmware) {
>>> - boot_from_kernel(machine, cpu);
>>> + boot_from_kernel(machine, ppc405->soc.cpu);
>>> }
>>> }
>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>> index 156e839b8283..59612504bf3f 100644
>>> --- a/hw/ppc/ppc405_uc.c
>>> +++ b/hw/ppc/ppc405_uc.c
>>> @@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
>>> #endif
>>> }
>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>> - MemoryRegion ram_memories[2],
>>> - hwaddr ram_bases[2],
>>> - hwaddr ram_sizes[2],
>>> - uint32_t sysclk, DeviceState **uicdevp,
>>> - int do_init)
>>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>> {
>>> + Ppc405SoCState *s = PPC405_SOC(dev);
>>> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>>> - PowerPCCPU *cpu;
>>> CPUPPCState *env;
>>> - DeviceState *uicdev;
>>> - SysBusDevice *uicsbd;
>>> + Error *err = NULL;
>>> +
>>> + /* XXX: fix this ? */
>>
>> So, this comment, originally from ppc405_boards.c, was added by commit
>> 1a6c088620368 and it seemed to make reference to something with the refering
>> to the ram_* values:
>>
>>
>> /* XXX: fix this */
>> ram_bases[0] = 0x00000000;
>> ram_sizes[0] = 0x08000000;
>> ram_bases[1] = 0x00000000;
>> ram_sizes[1] = 0x00000000;
>> (...)
>>
>>
>> No more context is provided aside from a git-svn-id from savannah.nongnu.org.
>>
>> If no one can provide more context about what is to be fixed here, I'll
>> remove the comment.
>
> I'm not sure about it because I don't know 405 and only vaguely remember how this was on 440/460EX but I think it might be that the memory controller can be programmed to map RAM to different places but we don't fully emulate that nor the different chunks/DIMM sockets that could be possible and just map all system RAM to address 0 which is what most guest firmware or OS does anyway. Maybe I'm wrong and don't remember this correctly, the SDRAM controller model in ppc4xx_devs.c seems to do some mapping but I think this is what the comment might refer to or something similar. If so, I don't think it's worth emulating this more precisely unless we know about a guest which needs this.
Thanks for the explanation!
I'm not sure if this is something worth documenting in this comment or not. I
guess it wouldn't hurt to mention "the memory controller can map RAM in different
sockets but we don't implement that" or something similar. Or just remove the
comment entirely.
Both works for me as long as we get rid of the 'fix this' comment. It implies
that we're doing something wrong on purpose, which doesn't seem to be the
case.
Thanks,
Daniel
>
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-02 19:18 ` Daniel Henrique Barboza
2022-08-02 21:24 ` BALATON Zoltan
@ 2022-08-03 8:03 ` Cédric Le Goater
2022-08-03 11:59 ` BALATON Zoltan
1 sibling, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-03 8:03 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/2/22 21:18, Daniel Henrique Barboza wrote:
>
>
> On 8/1/22 10:10, Cédric Le Goater wrote:
>> This moves all the code previously done in the ppc405ep_init() routine
>> under ppc405_soc_realize().
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h | 12 ++--
>> hw/ppc/ppc405_boards.c | 12 ++--
>> hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
>> 3 files changed, 84 insertions(+), 91 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index c8cddb71733a..5e4e96d86ceb 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -74,9 +74,14 @@ struct Ppc405SoCState {
>> MemoryRegion sram;
>> MemoryRegion ram_memories[2];
>> hwaddr ram_bases[2], ram_sizes[2];
>> + bool do_dram_init;
>> MemoryRegion *dram_mr;
>> hwaddr ram_size;
>> +
>> + uint32_t sysclk;
>> + PowerPCCPU *cpu;
>> + DeviceState *uic;
>> };
>> /* PowerPC 405 core */
>> @@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>> void ppc4xx_plb_init(CPUPPCState *env);
>> void ppc405_ebc_init(CPUPPCState *env);
>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>> - MemoryRegion ram_memories[2],
>> - hwaddr ram_bases[2],
>> - hwaddr ram_sizes[2],
>> - uint32_t sysclk, DeviceState **uicdev,
>> - int do_init);
>> -
>> #endif /* PPC405_H */
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 96db52c5a309..363cb0770506 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>> const char *kernel_filename = machine->kernel_filename;
>> - PowerPCCPU *cpu;
>> MemoryRegion *sysmem = get_system_memory();
>> - DeviceState *uicdev;
>> if (machine->ram_size != mc->default_ram_size) {
>> char *sz = size_to_str(mc->default_ram_size);
>> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
>> machine->ram_size, &error_fatal);
>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>> OBJECT(machine->ram), &error_abort);
>> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>> + !(kernel_filename == NULL), &error_abort);
>> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>> + &error_abort);
>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
>> - ppc405->soc.ram_sizes,
>> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>> -
>> /* allocate and load BIOS */
>> if (machine->firmware) {
>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>> /* Load ELF kernel and rootfs.cpio */
>> } else if (kernel_filename && !machine->firmware) {
>> - boot_from_kernel(machine, cpu);
>> + boot_from_kernel(machine, ppc405->soc.cpu);
>> }
>> }
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index 156e839b8283..59612504bf3f 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
>> #endif
>> }
>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>> - MemoryRegion ram_memories[2],
>> - hwaddr ram_bases[2],
>> - hwaddr ram_sizes[2],
>> - uint32_t sysclk, DeviceState **uicdevp,
>> - int do_init)
>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> {
>> + Ppc405SoCState *s = PPC405_SOC(dev);
>> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>> - PowerPCCPU *cpu;
>> CPUPPCState *env;
>> - DeviceState *uicdev;
>> - SysBusDevice *uicsbd;
>> + Error *err = NULL;
>> +
>> + /* XXX: fix this ? */
>
> So, this comment, originally from ppc405_boards.c, was added by commit
> 1a6c088620368 and it seemed to make reference to something with the refering
> to the ram_* values:
>
>
> /* XXX: fix this */
> ram_bases[0] = 0x00000000;
> ram_sizes[0] = 0x08000000;
> ram_bases[1] = 0x00000000;
> ram_sizes[1] = 0x00000000;
> (...)
>
>
> No more context is provided aside from a git-svn-id from savannah.nongnu.org.
>
> If no one can provide more context about what is to be fixed here, I'll
> remove the comment.
>
>
>
>> + memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
>> + "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
>
> As I mentioned in patch 2, ef405ep.ram.alias can be renamed to ppc405.ram.alias ...
sure.
>
>> + s->ram_bases[0] = 0;
>> + s->ram_sizes[0] = s->ram_size;
>> + memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
>
> And this can be renamed to ef405ep.ram1. If you agree with the rename I
> can amend it in the tree.
I think we can do better and simply remove the second bank. it is unused ...
I have patches QOMifying ppc4xx_sdram_init() but the current modelling
makes things a bit complex, specially ppc4xx_sdram_banks() which is only
used on the bamboo and sam460ex machines.
C.
>
>
>
> Thanks,
>
>
> Daniel
>
>> + s->ram_bases[1] = 0x00000000;
>> + s->ram_sizes[1] = 0x00000000;
>> +
>> + /* allocate SRAM */
>> + memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
>> + PPC405EP_SRAM_SIZE, &err);
>> + if (err) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> + memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
>> + &s->sram);
>> memset(clk_setup, 0, sizeof(clk_setup));
>> +
>> /* init CPUs */
>> - cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
>> + s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
>> &clk_setup[PPC405EP_CPU_CLK],
>> - &tlb_clk_setup, sysclk);
>> - env = &cpu->env;
>> + &tlb_clk_setup, s->sysclk);
>> + env = &s->cpu->env;
>> clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
>> clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
>> - /* Internal devices init */
>> - /* Memory mapped devices registers */
>> +
>> + /* CPU control */
>> + ppc405ep_cpc_init(env, clk_setup, s->sysclk);
>> +
>> /* PLB arbitrer */
>> ppc4xx_plb_init(env);
>> +
>> /* PLB to OPB bridge */
>> ppc4xx_pob_init(env);
>> +
>> /* OBP arbitrer */
>> ppc4xx_opba_init(0xef600600);
>> +
>> /* Universal interrupt controller */
>> - uicdev = qdev_new(TYPE_PPC_UIC);
>> - uicsbd = SYS_BUS_DEVICE(uicdev);
>> + s->uic = qdev_new(TYPE_PPC_UIC);
>> - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
>> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
>> &error_fatal);
>> - sysbus_realize_and_unref(uicsbd, &error_fatal);
>> -
>> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
>> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
>> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
>> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
>> + if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
>> + return;
>> + }
>> - *uicdevp = uicdev;
>> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
>> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
>> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
>> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
>> /* SDRAM controller */
>> - /* XXX 405EP has no ECC interrupt */
>> - ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
>> - ram_bases, ram_sizes, do_init);
>> + /* XXX 405EP has no ECC interrupt */
>> + ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 2, s->ram_memories,
>> + s->ram_bases, s->ram_sizes, s->do_dram_init);
>> +
>> /* External bus controller */
>> ppc405_ebc_init(env);
>> +
>> /* DMA controller */
>> - dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
>> - dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
>> - dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
>> - dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
>> + dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
>> + dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
>> + dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
>> + dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
>> ppc405_dma_init(env, dma_irqs);
>> - /* IIC controller */
>> +
>> + /* I2C controller */
>> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
>> - qdev_get_gpio_in(uicdev, 2));
>> + qdev_get_gpio_in(s->uic, 2));
>> /* GPIO */
>> ppc405_gpio_init(0xef600700);
>> +
>> /* Serial ports */
>> if (serial_hd(0) != NULL) {
>> - serial_mm_init(address_space_mem, 0xef600300, 0,
>> - qdev_get_gpio_in(uicdev, 0),
>> + serial_mm_init(get_system_memory(), 0xef600300, 0,
>> + qdev_get_gpio_in(s->uic, 0),
>> PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
>> DEVICE_BIG_ENDIAN);
>> }
>> if (serial_hd(1) != NULL) {
>> - serial_mm_init(address_space_mem, 0xef600400, 0,
>> - qdev_get_gpio_in(uicdev, 1),
>> + serial_mm_init(get_system_memory(), 0xef600400, 0,
>> + qdev_get_gpio_in(s->uic, 1),
>> PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
>> DEVICE_BIG_ENDIAN);
>> }
>> +
>> /* OCM */
>> ppc405_ocm_init(env);
>> +
>> /* GPT */
>> - gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
>> - gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
>> - gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
>> - gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
>> - gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
>> + gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
>> + gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
>> + gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
>> + gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
>> + gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
>> ppc4xx_gpt_init(0xef600000, gpt_irqs);
>> - /* PCI */
>> - /* Uses UIC IRQs 3, 16, 18 */
>> +
>> /* MAL */
>> - mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
>> - mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
>> - mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
>> - mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
>> + mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
>> + mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
>> + mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
>> + mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
>> ppc4xx_mal_init(env, 4, 2, mal_irqs);
>> +
>> /* Ethernet */
>> /* Uses UIC IRQs 9, 15, 17 */
>> - /* CPU control */
>> - ppc405ep_cpc_init(env, clk_setup, sysclk);
>> -
>> - return cpu;
>> -}
>> -
>> -static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> -{
>> - Ppc405SoCState *s = PPC405_SOC(dev);
>> - Error *err = NULL;
>> -
>> - /* XXX: fix this ? */
>> - memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
>> - "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
>> - s->ram_bases[0] = 0;
>> - s->ram_sizes[0] = s->ram_size;
>> - memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
>> - s->ram_bases[1] = 0x00000000;
>> - s->ram_sizes[1] = 0x00000000;
>> -
>> - /* allocate SRAM */
>> - memory_region_init_ram(&s->sram, OBJECT(s), "ef405ep.sram",
>> - PPC405EP_SRAM_SIZE, &err);
>> - if (err) {
>> - error_propagate(errp, err);
>> - return;
>> - }
>> - memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
>> - &s->sram);
>> }
>> static Property ppc405_soc_properties[] = {
>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>> MemoryRegion *),
>> + DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
>> + DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>> DEFINE_PROP_END_OF_LIST(),
>> };
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-03 8:03 ` Cédric Le Goater
@ 2022-08-03 11:59 ` BALATON Zoltan
2022-08-03 12:28 ` Cédric Le Goater
0 siblings, 1 reply; 50+ messages in thread
From: BALATON Zoltan @ 2022-08-03 11:59 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Daniel Henrique Barboza, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 8058 bytes --]
On Wed, 3 Aug 2022, Cédric Le Goater wrote:
> On 8/2/22 21:18, Daniel Henrique Barboza wrote:
>> On 8/1/22 10:10, Cédric Le Goater wrote:
>>> This moves all the code previously done in the ppc405ep_init() routine
>>> under ppc405_soc_realize().
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>> hw/ppc/ppc405.h | 12 ++--
>>> hw/ppc/ppc405_boards.c | 12 ++--
>>> hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
>>> 3 files changed, 84 insertions(+), 91 deletions(-)
>>>
>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>> index c8cddb71733a..5e4e96d86ceb 100644
>>> --- a/hw/ppc/ppc405.h
>>> +++ b/hw/ppc/ppc405.h
>>> @@ -74,9 +74,14 @@ struct Ppc405SoCState {
>>> MemoryRegion sram;
>>> MemoryRegion ram_memories[2];
>>> hwaddr ram_bases[2], ram_sizes[2];
>>> + bool do_dram_init;
>>> MemoryRegion *dram_mr;
>>> hwaddr ram_size;
>>> +
>>> + uint32_t sysclk;
>>> + PowerPCCPU *cpu;
>>> + DeviceState *uic;
>>> };
>>> /* PowerPC 405 core */
>>> @@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env,
>>> ram_addr_t ram_size);
>>> void ppc4xx_plb_init(CPUPPCState *env);
>>> void ppc405_ebc_init(CPUPPCState *env);
>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>> - MemoryRegion ram_memories[2],
>>> - hwaddr ram_bases[2],
>>> - hwaddr ram_sizes[2],
>>> - uint32_t sysclk, DeviceState **uicdev,
>>> - int do_init);
>>> -
>>> #endif /* PPC405_H */
>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>> index 96db52c5a309..363cb0770506 100644
>>> --- a/hw/ppc/ppc405_boards.c
>>> +++ b/hw/ppc/ppc405_boards.c
>>> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
>>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>> const char *kernel_filename = machine->kernel_filename;
>>> - PowerPCCPU *cpu;
>>> MemoryRegion *sysmem = get_system_memory();
>>> - DeviceState *uicdev;
>>> if (machine->ram_size != mc->default_ram_size) {
>>> char *sz = size_to_str(mc->default_ram_size);
>>> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
>>> machine->ram_size, &error_fatal);
>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>> OBJECT(machine->ram), &error_abort);
>>> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>> + !(kernel_filename == NULL), &error_abort);
>>> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>> + &error_abort);
>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>>> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories,
>>> ppc405->soc.ram_bases,
>>> - ppc405->soc.ram_sizes,
>>> - 33333333, &uicdev, kernel_filename == NULL ? 0 :
>>> 1);
>>> -
>>> /* allocate and load BIOS */
>>> if (machine->firmware) {
>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>>> /* Load ELF kernel and rootfs.cpio */
>>> } else if (kernel_filename && !machine->firmware) {
>>> - boot_from_kernel(machine, cpu);
>>> + boot_from_kernel(machine, ppc405->soc.cpu);
>>> }
>>> }
>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>> index 156e839b8283..59612504bf3f 100644
>>> --- a/hw/ppc/ppc405_uc.c
>>> +++ b/hw/ppc/ppc405_uc.c
>>> @@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env,
>>> clk_setup_t clk_setup[8],
>>> #endif
>>> }
>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>> - MemoryRegion ram_memories[2],
>>> - hwaddr ram_bases[2],
>>> - hwaddr ram_sizes[2],
>>> - uint32_t sysclk, DeviceState **uicdevp,
>>> - int do_init)
>>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>> {
>>> + Ppc405SoCState *s = PPC405_SOC(dev);
>>> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>>> - PowerPCCPU *cpu;
>>> CPUPPCState *env;
>>> - DeviceState *uicdev;
>>> - SysBusDevice *uicsbd;
>>> + Error *err = NULL;
>>> +
>>> + /* XXX: fix this ? */
>>
>> So, this comment, originally from ppc405_boards.c, was added by commit
>> 1a6c088620368 and it seemed to make reference to something with the
>> refering
>> to the ram_* values:
>>
>>
>> /* XXX: fix this */
>> ram_bases[0] = 0x00000000;
>> ram_sizes[0] = 0x08000000;
>> ram_bases[1] = 0x00000000;
>> ram_sizes[1] = 0x00000000;
>> (...)
>>
>>
>> No more context is provided aside from a git-svn-id from
>> savannah.nongnu.org.
>>
>> If no one can provide more context about what is to be fixed here, I'll
>> remove the comment.
>>
>>
>>
>>> + memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
>>> + "ef405ep.ram.alias", s->dram_mr, 0,
>>> s->ram_size);
>>
>> As I mentioned in patch 2, ef405ep.ram.alias can be renamed to
>> ppc405.ram.alias ...
>
> sure.
>
>>
>>> + s->ram_bases[0] = 0;
>>> + s->ram_sizes[0] = s->ram_size;
>>> + memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1",
>>> 0);
>>
>> And this can be renamed to ef405ep.ram1. If you agree with the rename I
>> can amend it in the tree.
>
>
> I think we can do better and simply remove the second bank. it is unused ...
>
> I have patches QOMifying ppc4xx_sdram_init() but the current modelling
> makes things a bit complex, specially ppc4xx_sdram_banks() which is only
> used on the bamboo and sam460ex machines.
We need to model the SDRAM controller for the sam460ex firmware at least
partially so it gets past the memory test and init. If you change it
please test that sam460ex still boots with firmware. I'm not sure 405 and
440 use the same sdram controller though or if the 460EX has a different
one as these may have been updated in later SoCs to support newer RAM
standards (I think the 460EX has DDR2) and the QEMU model is a bit messy
sharing components between 405 and 440. When I've changed some of these
for 460EX I've tried to name them so that 4xx means shared by all, 44x or
440 means 440 specific and 40x or similar for older SoCs only but this is
probably not always correct. I could not find a clean way to separate
these. QOMifying would make sense when cleaning this up otherwise it's
just adding more boilerplate without any clear advantage IMO.
If you want change these maybe you should get the docs for the emulated
chips and consult those for differences. Unfortunately the 460ex does not
seem to have docs available but it's similar to earlier IBM parts like
440GP which generally have docs. That's what I've used but still couldn't
find all parts like the PCIe conroller that I had to implement based on
what the firmware and drivers do (and only did that partially so it boots
as I did not fully understand how it works and how these are modelled in
QEMU).
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC
2022-08-03 11:59 ` BALATON Zoltan
@ 2022-08-03 12:28 ` Cédric Le Goater
0 siblings, 0 replies; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-03 12:28 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: Daniel Henrique Barboza, qemu-ppc, qemu-devel
On 8/3/22 13:59, BALATON Zoltan wrote:
> On Wed, 3 Aug 2022, Cédric Le Goater wrote:
>> On 8/2/22 21:18, Daniel Henrique Barboza wrote:
>>> On 8/1/22 10:10, Cédric Le Goater wrote:
>>>> This moves all the code previously done in the ppc405ep_init() routine
>>>> under ppc405_soc_realize().
>>>>
>>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>>> ---
>>>> hw/ppc/ppc405.h | 12 ++--
>>>> hw/ppc/ppc405_boards.c | 12 ++--
>>>> hw/ppc/ppc405_uc.c | 151 ++++++++++++++++++++---------------------
>>>> 3 files changed, 84 insertions(+), 91 deletions(-)
>>>>
>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>> index c8cddb71733a..5e4e96d86ceb 100644
>>>> --- a/hw/ppc/ppc405.h
>>>> +++ b/hw/ppc/ppc405.h
>>>> @@ -74,9 +74,14 @@ struct Ppc405SoCState {
>>>> MemoryRegion sram;
>>>> MemoryRegion ram_memories[2];
>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>> + bool do_dram_init;
>>>> MemoryRegion *dram_mr;
>>>> hwaddr ram_size;
>>>> +
>>>> + uint32_t sysclk;
>>>> + PowerPCCPU *cpu;
>>>> + DeviceState *uic;
>>>> };
>>>> /* PowerPC 405 core */
>>>> @@ -85,11 +90,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>>>> void ppc4xx_plb_init(CPUPPCState *env);
>>>> void ppc405_ebc_init(CPUPPCState *env);
>>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>>> - MemoryRegion ram_memories[2],
>>>> - hwaddr ram_bases[2],
>>>> - hwaddr ram_sizes[2],
>>>> - uint32_t sysclk, DeviceState **uicdev,
>>>> - int do_init);
>>>> -
>>>> #endif /* PPC405_H */
>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>> index 96db52c5a309..363cb0770506 100644
>>>> --- a/hw/ppc/ppc405_boards.c
>>>> +++ b/hw/ppc/ppc405_boards.c
>>>> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
>>>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>> const char *kernel_filename = machine->kernel_filename;
>>>> - PowerPCCPU *cpu;
>>>> MemoryRegion *sysmem = get_system_memory();
>>>> - DeviceState *uicdev;
>>>> if (machine->ram_size != mc->default_ram_size) {
>>>> char *sz = size_to_str(mc->default_ram_size);
>>>> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
>>>> machine->ram_size, &error_fatal);
>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>> OBJECT(machine->ram), &error_abort);
>>>> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>> + !(kernel_filename == NULL), &error_abort);
>>>> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>>> + &error_abort);
>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>>>> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories, ppc405->soc.ram_bases,
>>>> - ppc405->soc.ram_sizes,
>>>> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>>>> -
>>>> /* allocate and load BIOS */
>>>> if (machine->firmware) {
>>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>>> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>>>> /* Load ELF kernel and rootfs.cpio */
>>>> } else if (kernel_filename && !machine->firmware) {
>>>> - boot_from_kernel(machine, cpu);
>>>> + boot_from_kernel(machine, ppc405->soc.cpu);
>>>> }
>>>> }
>>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>>> index 156e839b8283..59612504bf3f 100644
>>>> --- a/hw/ppc/ppc405_uc.c
>>>> +++ b/hw/ppc/ppc405_uc.c
>>>> @@ -1432,134 +1432,131 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
>>>> #endif
>>>> }
>>>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>>> - MemoryRegion ram_memories[2],
>>>> - hwaddr ram_bases[2],
>>>> - hwaddr ram_sizes[2],
>>>> - uint32_t sysclk, DeviceState **uicdevp,
>>>> - int do_init)
>>>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>>> {
>>>> + Ppc405SoCState *s = PPC405_SOC(dev);
>>>> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>>>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>>>> - PowerPCCPU *cpu;
>>>> CPUPPCState *env;
>>>> - DeviceState *uicdev;
>>>> - SysBusDevice *uicsbd;
>>>> + Error *err = NULL;
>>>> +
>>>> + /* XXX: fix this ? */
>>>
>>> So, this comment, originally from ppc405_boards.c, was added by commit
>>> 1a6c088620368 and it seemed to make reference to something with the refering
>>> to the ram_* values:
>>>
>>>
>>> /* XXX: fix this */
>>> ram_bases[0] = 0x00000000;
>>> ram_sizes[0] = 0x08000000;
>>> ram_bases[1] = 0x00000000;
>>> ram_sizes[1] = 0x00000000;
>>> (...)
>>>
>>>
>>> No more context is provided aside from a git-svn-id from savannah.nongnu.org.
>>>
>>> If no one can provide more context about what is to be fixed here, I'll
>>> remove the comment.
>>>
>>>
>>>
>>>> + memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
>>>> + "ef405ep.ram.alias", s->dram_mr, 0, s->ram_size);
>>>
>>> As I mentioned in patch 2, ef405ep.ram.alias can be renamed to ppc405.ram.alias ...
>>
>> sure.
>>
>>>
>>>> + s->ram_bases[0] = 0;
>>>> + s->ram_sizes[0] = s->ram_size;
>>>> + memory_region_init(&s->ram_memories[1], OBJECT(s), "ef405ep.ram1", 0);
>>>
>>> And this can be renamed to ef405ep.ram1. If you agree with the rename I
>>> can amend it in the tree.
>>
>>
>> I think we can do better and simply remove the second bank. it is unused ...
>>
>> I have patches QOMifying ppc4xx_sdram_init() but the current modelling
>> makes things a bit complex, specially ppc4xx_sdram_banks() which is only
>> used on the bamboo and sam460ex machines.
>
> We need to model the SDRAM controller for the sam460ex firmware at least partially so it gets past the memory test and init. If you change it please test that sam460ex still boots with firmware.
Sure.
QOM'ifying models reveals the implementation shortcuts. The ppc405 board was
quite messy and it's getting better with the removal of ppc405ep_init().
ppc4xx_sdram_init() is the next step but it is quite localized in the SoC.
No hurries.
Thanks,
C.
> I'm not sure 405 and 440 use the same sdram controller though or if the 460EX has a different one as these may have been updated in later SoCs to support newer RAM standards (I think the 460EX has DDR2) and the QEMU model is a bit messy sharing components between 405 and 440. When I've changed some of these for 460EX I've tried to name them so that 4xx means shared by all, 44x or 440 means 440 specific and 40x or similar for older SoCs only but this is probably not always correct. I could not find a clean way to separate these. QOMifying would make sense when cleaning this up otherwise it's just adding more boilerplate without any clear advantage IMO.
>
> If you want change these maybe you should get the docs for the emulated chips and consult those for differences. Unfortunately the 460ex does not seem to have docs available but it's similar to earlier IBM parts like 440GP which generally have docs. That's what I've used but still couldn't find all parts like the PCIe conroller that I had to implement based on what the firmware and drivers do (and only did that partially so it boots as I did not fully understand how it works and how these are modelled in QEMU).
>
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 06/19] ppc/ppc405: QOM'ify CPU
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (4 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:09 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 07/19] ppc/ppc405: QOM'ify CPC Cédric Le Goater
` (12 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in the SoC realize routine. We will clean that up in the
following patches.
ppc_dcr_init simply allocates default DCR handlers for the CPU. Maybe
this could be done in model initializer of the CPU families needing it.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc405_uc.c | 34 ++++++++++++++++++++++++----------
3 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 5e4e96d86ceb..4e99ab48be36 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -80,7 +80,7 @@ struct Ppc405SoCState {
hwaddr ram_size;
uint32_t sysclk;
- PowerPCCPU *cpu;
+ PowerPCCPU cpu;
DeviceState *uic;
};
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 363cb0770506..82b51cc457fa 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- boot_from_kernel(machine, ppc405->soc.cpu);
+ boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 59612504bf3f..b84749b36114 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1432,10 +1432,18 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
#endif
}
+static void ppc405_soc_instance_init(Object *obj)
+{
+ Ppc405SoCState *s = PPC405_SOC(obj);
+
+ object_initialize_child(obj, "cpu", &s->cpu,
+ POWERPC_CPU_TYPE_NAME("405ep"));
+}
+
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
+ clk_setup_t clk_setup[PPC405EP_CLK_NB];
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUPPCState *env;
Error *err = NULL;
@@ -1462,12 +1470,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
memset(clk_setup, 0, sizeof(clk_setup));
/* init CPUs */
- s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
- &clk_setup[PPC405EP_CPU_CLK],
- &tlb_clk_setup, s->sysclk);
- env = &s->cpu->env;
- clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
- clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
+ if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
+ return;
+ }
+
+ env = &s->cpu.env;
+
+ clk_setup[PPC405EP_CPU_CLK].cb =
+ ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
+ clk_setup[PPC405EP_CPU_CLK].opaque = env;
+
+ ppc_dcr_init(env, NULL, NULL);
/* CPU control */
ppc405ep_cpc_init(env, clk_setup, s->sysclk);
@@ -1484,16 +1497,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
- object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
+ object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
&error_fatal);
if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
- qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
+ qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
- qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
+ qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
@@ -1575,6 +1588,7 @@ static const TypeInfo ppc405_types[] = {
.name = TYPE_PPC405_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405SoCState),
+ .instance_init = ppc405_soc_instance_init,
.class_init = ppc405_soc_class_init,
}
};
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 06/19] ppc/ppc405: QOM'ify CPU
2022-08-01 13:10 ` [PATCH 06/19] ppc/ppc405: QOM'ify CPU Cédric Le Goater
@ 2022-08-03 9:09 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:09 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Drop the use of ppc4xx_init() and duplicate a bit of code related to
> clocks in the SoC realize routine. We will clean that up in the
> following patches.
>
> ppc_dcr_init simply allocates default DCR handlers for the CPU. Maybe
> this could be done in model initializer of the CPU families needing it.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 2 +-
> hw/ppc/ppc405_boards.c | 2 +-
> hw/ppc/ppc405_uc.c | 34 ++++++++++++++++++++++++----------
> 3 files changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 5e4e96d86ceb..4e99ab48be36 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -80,7 +80,7 @@ struct Ppc405SoCState {
> hwaddr ram_size;
>
> uint32_t sysclk;
> - PowerPCCPU *cpu;
> + PowerPCCPU cpu;
> DeviceState *uic;
> };
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 363cb0770506..82b51cc457fa 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>
> /* Load ELF kernel and rootfs.cpio */
> } else if (kernel_filename && !machine->firmware) {
> - boot_from_kernel(machine, ppc405->soc.cpu);
> + boot_from_kernel(machine, &ppc405->soc.cpu);
> }
> }
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 59612504bf3f..b84749b36114 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1432,10 +1432,18 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
> #endif
> }
>
> +static void ppc405_soc_instance_init(Object *obj)
> +{
> + Ppc405SoCState *s = PPC405_SOC(obj);
> +
> + object_initialize_child(obj, "cpu", &s->cpu,
> + POWERPC_CPU_TYPE_NAME("405ep"));
> +}
> +
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
> + clk_setup_t clk_setup[PPC405EP_CLK_NB];
> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> CPUPPCState *env;
> Error *err = NULL;
> @@ -1462,12 +1470,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> memset(clk_setup, 0, sizeof(clk_setup));
>
> /* init CPUs */
> - s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
> - &clk_setup[PPC405EP_CPU_CLK],
> - &tlb_clk_setup, s->sysclk);
> - env = &s->cpu->env;
> - clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
> - clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
> + if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
> + return;
> + }
> +
> + env = &s->cpu.env;
> +
> + clk_setup[PPC405EP_CPU_CLK].cb =
> + ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
> + clk_setup[PPC405EP_CPU_CLK].opaque = env;
> +
> + ppc_dcr_init(env, NULL, NULL);
>
> /* CPU control */
> ppc405ep_cpc_init(env, clk_setup, s->sysclk);
> @@ -1484,16 +1497,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* Universal interrupt controller */
> s->uic = qdev_new(TYPE_PPC_UIC);
>
> - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
> &error_fatal);
> if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
> return;
> }
>
> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
> - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
> + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
> - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
> + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> /* XXX 405EP has no ECC interrupt */
> @@ -1575,6 +1588,7 @@ static const TypeInfo ppc405_types[] = {
> .name = TYPE_PPC405_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(Ppc405SoCState),
> + .instance_init = ppc405_soc_instance_init,
> .class_init = ppc405_soc_class_init,
> }
> };
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 07/19] ppc/ppc405: QOM'ify CPC
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (5 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 06/19] ppc/ppc405: QOM'ify CPU Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:14 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 08/19] ppc/ppc405: QOM'ify GPT Cédric Le Goater
` (11 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Since all clock settings are now handled at the CPC level, this changes
the SoC "sys-clk" property to be an alias on the same property in the
CPC model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 39 +++++++++++++++-
hw/ppc/ppc405_uc.c | 109 +++++++++++++++++++--------------------------
2 files changed, 85 insertions(+), 63 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4e99ab48be36..d51fb5094e95 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,43 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+typedef struct Ppc405SoCState Ppc405SoCState;
+
+#define TYPE_PPC405_CPC "ppc405-cpc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
+
+enum {
+ PPC405EP_CPU_CLK = 0,
+ PPC405EP_PLB_CLK = 1,
+ PPC405EP_OPB_CLK = 2,
+ PPC405EP_EBC_CLK = 3,
+ PPC405EP_MAL_CLK = 4,
+ PPC405EP_PCI_CLK = 5,
+ PPC405EP_UART0_CLK = 6,
+ PPC405EP_UART1_CLK = 7,
+ PPC405EP_CLK_NB = 8,
+};
+
+struct Ppc405CpcState {
+ DeviceState parent_obj;
+
+ PowerPCCPU *cpu;
+
+ uint32_t sysclk;
+ clk_setup_t clk_setup[PPC405EP_CLK_NB];
+ uint32_t boot;
+ uint32_t epctl;
+ uint32_t pllmr[2];
+ uint32_t ucr;
+ uint32_t srr;
+ uint32_t jtagid;
+ uint32_t pci;
+ /* Clock and power management */
+ uint32_t er;
+ uint32_t fr;
+ uint32_t sr;
+};
+
#define TYPE_PPC405_SOC "ppc405-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
@@ -79,9 +116,9 @@ struct Ppc405SoCState {
MemoryRegion *dram_mr;
hwaddr ram_size;
- uint32_t sysclk;
PowerPCCPU cpu;
DeviceState *uic;
+ Ppc405CpcState cpc;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index b84749b36114..20a3e5543423 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1178,36 +1178,7 @@ enum {
#endif
};
-enum {
- PPC405EP_CPU_CLK = 0,
- PPC405EP_PLB_CLK = 1,
- PPC405EP_OPB_CLK = 2,
- PPC405EP_EBC_CLK = 3,
- PPC405EP_MAL_CLK = 4,
- PPC405EP_PCI_CLK = 5,
- PPC405EP_UART0_CLK = 6,
- PPC405EP_UART1_CLK = 7,
- PPC405EP_CLK_NB = 8,
-};
-
-typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
-struct ppc405ep_cpc_t {
- uint32_t sysclk;
- clk_setup_t clk_setup[PPC405EP_CLK_NB];
- uint32_t boot;
- uint32_t epctl;
- uint32_t pllmr[2];
- uint32_t ucr;
- uint32_t srr;
- uint32_t jtagid;
- uint32_t pci;
- /* Clock and power management */
- uint32_t er;
- uint32_t fr;
- uint32_t sr;
-};
-
-static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
+static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
{
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
uint32_t UART0_clk, UART1_clk;
@@ -1302,10 +1273,9 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = PPC405_CPC(opaque);
uint32_t ret;
- cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
ret = cpc->boot;
@@ -1342,9 +1312,8 @@ static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = PPC405_CPC(opaque);
- cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
/* Read-only register */
@@ -1377,9 +1346,9 @@ static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc405ep_cpc_reset (void *opaque)
+static void ppc405_cpc_reset(DeviceState *dev)
{
- ppc405ep_cpc_t *cpc = opaque;
+ Ppc405CpcState *cpc = PPC405_CPC(dev);
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
cpc->epctl = 0x00000000;
@@ -1391,21 +1360,24 @@ static void ppc405ep_cpc_reset (void *opaque)
cpc->er = 0x00000000;
cpc->fr = 0x00000000;
cpc->sr = 0x00000000;
+ cpc->jtagid = 0x20267049;
ppc405ep_compute_clocks(cpc);
}
/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
- uint32_t sysclk)
+static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = PPC405_CPC(dev);
+ CPUPPCState *env;
+
+ assert(cpc->cpu);
+
+ env = &cpc->cpu->env;
+
+ cpc->clk_setup[PPC405EP_CPU_CLK].cb =
+ ppc_40x_timers_init(env, cpc->sysclk, PPC_INTERRUPT_PIT);
+ cpc->clk_setup[PPC405EP_CPU_CLK].opaque = env;
- cpc = g_new0(ppc405ep_cpc_t, 1);
- memcpy(cpc->clk_setup, clk_setup,
- PPC405EP_CLK_NB * sizeof(clk_setup_t));
- cpc->jtagid = 0x20267049;
- cpc->sysclk = sysclk;
- qemu_register_reset(&ppc405ep_cpc_reset, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
@@ -1422,14 +1394,23 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
-#if 0
- ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
-#endif
+}
+
+static Property ppc405_cpc_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc405CpcState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_cpc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_cpc_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_cpc_reset;
+ device_class_set_props(dc, ppc405_cpc_properties);
}
static void ppc405_soc_instance_init(Object *obj)
@@ -1438,12 +1419,14 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpu", &s->cpu,
POWERPC_CPU_TYPE_NAME("405ep"));
+
+ object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
+ object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- clk_setup_t clk_setup[PPC405EP_CLK_NB];
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUPPCState *env;
Error *err = NULL;
@@ -1467,8 +1450,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
&s->sram);
- memset(clk_setup, 0, sizeof(clk_setup));
-
/* init CPUs */
if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
return;
@@ -1476,14 +1457,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
env = &s->cpu.env;
- clk_setup[PPC405EP_CPU_CLK].cb =
- ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
- clk_setup[PPC405EP_CPU_CLK].opaque = env;
-
ppc_dcr_init(env, NULL, NULL);
/* CPU control */
- ppc405ep_cpc_init(env, clk_setup, s->sysclk);
+ object_property_set_link(OBJECT(&s->cpc), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&s->cpc), NULL, errp)) {
+ return;
+ }
/* PLB arbitrer */
ppc4xx_plb_init(env);
@@ -1568,7 +1549,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
@@ -1585,6 +1565,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_CPC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405CpcState),
+ .class_init = ppc405_cpc_class_init,
+ }, {
.name = TYPE_PPC405_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405SoCState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 07/19] ppc/ppc405: QOM'ify CPC
2022-08-01 13:10 ` [PATCH 07/19] ppc/ppc405: QOM'ify CPC Cédric Le Goater
@ 2022-08-03 9:14 ` Daniel Henrique Barboza
2022-08-03 9:16 ` Cédric Le Goater
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:14 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Since all clock settings are now handled at the CPC level, this changes
> the SoC "sys-clk" property to be an alias on the same property in the
> CPC model.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 39 +++++++++++++++-
> hw/ppc/ppc405_uc.c | 109 +++++++++++++++++++--------------------------
> 2 files changed, 85 insertions(+), 63 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 4e99ab48be36..d51fb5094e95 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -63,6 +63,43 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> +typedef struct Ppc405SoCState Ppc405SoCState;
> +
> +#define TYPE_PPC405_CPC "ppc405-cpc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
> +
> +enum {
> + PPC405EP_CPU_CLK = 0,
> + PPC405EP_PLB_CLK = 1,
> + PPC405EP_OPB_CLK = 2,
> + PPC405EP_EBC_CLK = 3,
> + PPC405EP_MAL_CLK = 4,
> + PPC405EP_PCI_CLK = 5,
> + PPC405EP_UART0_CLK = 6,
> + PPC405EP_UART1_CLK = 7,
> + PPC405EP_CLK_NB = 8,
> +};
> +
> +struct Ppc405CpcState {
> + DeviceState parent_obj;
> +
> + PowerPCCPU *cpu;
> +
> + uint32_t sysclk;
> + clk_setup_t clk_setup[PPC405EP_CLK_NB];
> + uint32_t boot;
> + uint32_t epctl;
> + uint32_t pllmr[2];
> + uint32_t ucr;
> + uint32_t srr;
> + uint32_t jtagid;
> + uint32_t pci;
> + /* Clock and power management */
> + uint32_t er;
> + uint32_t fr;
> + uint32_t sr;
> +};
> +
> #define TYPE_PPC405_SOC "ppc405-soc"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
>
> @@ -79,9 +116,9 @@ struct Ppc405SoCState {
> MemoryRegion *dram_mr;
> hwaddr ram_size;
>
> - uint32_t sysclk;
> PowerPCCPU cpu;
> DeviceState *uic;
> + Ppc405CpcState cpc;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index b84749b36114..20a3e5543423 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1178,36 +1178,7 @@ enum {
> #endif
> };
>
> -enum {
> - PPC405EP_CPU_CLK = 0,
> - PPC405EP_PLB_CLK = 1,
> - PPC405EP_OPB_CLK = 2,
> - PPC405EP_EBC_CLK = 3,
> - PPC405EP_MAL_CLK = 4,
> - PPC405EP_PCI_CLK = 5,
> - PPC405EP_UART0_CLK = 6,
> - PPC405EP_UART1_CLK = 7,
> - PPC405EP_CLK_NB = 8,
> -};
> -
> -typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
> -struct ppc405ep_cpc_t {
> - uint32_t sysclk;
> - clk_setup_t clk_setup[PPC405EP_CLK_NB];
> - uint32_t boot;
> - uint32_t epctl;
> - uint32_t pllmr[2];
> - uint32_t ucr;
> - uint32_t srr;
> - uint32_t jtagid;
> - uint32_t pci;
> - /* Clock and power management */
> - uint32_t er;
> - uint32_t fr;
> - uint32_t sr;
> -};
> -
> -static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
> +static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
> {
> uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
> uint32_t UART0_clk, UART1_clk;
> @@ -1302,10 +1273,9 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
>
> static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
> {
> - ppc405ep_cpc_t *cpc;
> + Ppc405CpcState *cpc = PPC405_CPC(opaque);
> uint32_t ret;
>
> - cpc = opaque;
> switch (dcrn) {
> case PPC405EP_CPC0_BOOT:
> ret = cpc->boot;
> @@ -1342,9 +1312,8 @@ static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
>
> static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
> {
> - ppc405ep_cpc_t *cpc;
> + Ppc405CpcState *cpc = PPC405_CPC(opaque);
>
> - cpc = opaque;
> switch (dcrn) {
> case PPC405EP_CPC0_BOOT:
> /* Read-only register */
> @@ -1377,9 +1346,9 @@ static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -static void ppc405ep_cpc_reset (void *opaque)
> +static void ppc405_cpc_reset(DeviceState *dev)
> {
> - ppc405ep_cpc_t *cpc = opaque;
> + Ppc405CpcState *cpc = PPC405_CPC(dev);
>
> cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
> cpc->epctl = 0x00000000;
> @@ -1391,21 +1360,24 @@ static void ppc405ep_cpc_reset (void *opaque)
> cpc->er = 0x00000000;
> cpc->fr = 0x00000000;
> cpc->sr = 0x00000000;
> + cpc->jtagid = 0x20267049;
> ppc405ep_compute_clocks(cpc);
> }
>
> /* XXX: sysclk should be between 25 and 100 MHz */
> -static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
> - uint32_t sysclk)
> +static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
> {
> - ppc405ep_cpc_t *cpc;
> + Ppc405CpcState *cpc = PPC405_CPC(dev);
> + CPUPPCState *env;
> +
> + assert(cpc->cpu);
> +
> + env = &cpc->cpu->env;
> +
> + cpc->clk_setup[PPC405EP_CPU_CLK].cb =
> + ppc_40x_timers_init(env, cpc->sysclk, PPC_INTERRUPT_PIT);
> + cpc->clk_setup[PPC405EP_CPU_CLK].opaque = env;
>
> - cpc = g_new0(ppc405ep_cpc_t, 1);
> - memcpy(cpc->clk_setup, clk_setup,
> - PPC405EP_CLK_NB * sizeof(clk_setup_t));
> - cpc->jtagid = 0x20267049;
> - cpc->sysclk = sysclk;
> - qemu_register_reset(&ppc405ep_cpc_reset, cpc);
> ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
> &dcr_read_epcpc, &dcr_write_epcpc);
> ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
> @@ -1422,14 +1394,23 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
> &dcr_read_epcpc, &dcr_write_epcpc);
> ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
> &dcr_read_epcpc, &dcr_write_epcpc);
> -#if 0
> - ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
> - &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
> - &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
> - &dcr_read_epcpc, &dcr_write_epcpc);
> -#endif
> +}
> +
> +static Property ppc405_cpc_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc405CpcState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_cpc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_cpc_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_cpc_reset;
> + device_class_set_props(dc, ppc405_cpc_properties);
> }
>
> static void ppc405_soc_instance_init(Object *obj)
> @@ -1438,12 +1419,14 @@ static void ppc405_soc_instance_init(Object *obj)
>
> object_initialize_child(obj, "cpu", &s->cpu,
> POWERPC_CPU_TYPE_NAME("405ep"));
> +
> + object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
> + object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - clk_setup_t clk_setup[PPC405EP_CLK_NB];
> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> CPUPPCState *env;
> Error *err = NULL;
> @@ -1467,8 +1450,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
> &s->sram);
>
> - memset(clk_setup, 0, sizeof(clk_setup));
> -
> /* init CPUs */
> if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
> return;
> @@ -1476,14 +1457,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> env = &s->cpu.env;
>
> - clk_setup[PPC405EP_CPU_CLK].cb =
> - ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
> - clk_setup[PPC405EP_CPU_CLK].opaque = env;
> -
> ppc_dcr_init(env, NULL, NULL);
>
> /* CPU control */
> - ppc405ep_cpc_init(env, clk_setup, s->sysclk);
> + object_property_set_link(OBJECT(&s->cpc), "cpu", OBJECT(&s->cpu),
> + &error_abort);
> + if (!qdev_realize(DEVICE(&s->cpc), NULL, errp)) {
> + return;
> + }
This if seems misaligned. Otherwise LGTM.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>
> /* PLB arbitrer */
> ppc4xx_plb_init(env);
> @@ -1568,7 +1549,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> static Property ppc405_soc_properties[] = {
> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> MemoryRegion *),
> - DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
> DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> DEFINE_PROP_END_OF_LIST(),
> @@ -1585,6 +1565,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_CPC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(Ppc405CpcState),
> + .class_init = ppc405_cpc_class_init,
> + }, {
> .name = TYPE_PPC405_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(Ppc405SoCState),
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 07/19] ppc/ppc405: QOM'ify CPC
2022-08-03 9:14 ` Daniel Henrique Barboza
@ 2022-08-03 9:16 ` Cédric Le Goater
0 siblings, 0 replies; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-03 9:16 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/3/22 11:14, Daniel Henrique Barboza wrote:
>> ppc_dcr_init(env, NULL, NULL);
>> /* CPU control */
>> - ppc405ep_cpc_init(env, clk_setup, s->sysclk);
>> + object_property_set_link(OBJECT(&s->cpc), "cpu", OBJECT(&s->cpu),
>> + &error_abort);
>> + if (!qdev_realize(DEVICE(&s->cpc), NULL, errp)) {
>> + return;
>> + }
>
> This if seems misaligned. Otherwise LGTM.
Indeed.
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Thanks,
C.
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 08/19] ppc/ppc405: QOM'ify GPT
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (6 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 07/19] ppc/ppc405: QOM'ify CPC Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:15 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 09/19] ppc/ppc405: QOM'ify OCM Cédric Le Goater
` (10 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 22 ++++++++++++
hw/ppc/ppc405_uc.c | 90 +++++++++++++++++++++++-----------------------
2 files changed, 67 insertions(+), 45 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d51fb5094e95..f7c0eb1d0008 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,27 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* General purpose timers */
+#define TYPE_PPC405_GPT "ppc405-gpt"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
+struct Ppc405GptState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ int64_t tb_offset;
+ uint32_t tb_freq;
+ QEMUTimer *timer;
+ qemu_irq irqs[5];
+ uint32_t oe;
+ uint32_t ol;
+ uint32_t im;
+ uint32_t is;
+ uint32_t ie;
+ uint32_t comp[5];
+ uint32_t mask[5];
+};
+
#define TYPE_PPC405_CPC "ppc405-cpc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
@@ -119,6 +140,7 @@ struct Ppc405SoCState {
PowerPCCPU cpu;
DeviceState *uic;
Ppc405CpcState cpc;
+ Ppc405GptState gpt;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 20a3e5543423..0f5e4ec15f14 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env)
/*****************************************************************************/
/* General purpose timers */
-typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
-struct ppc4xx_gpt_t {
- MemoryRegion iomem;
- int64_t tb_offset;
- uint32_t tb_freq;
- QEMUTimer *timer;
- qemu_irq irqs[5];
- uint32_t oe;
- uint32_t ol;
- uint32_t im;
- uint32_t is;
- uint32_t ie;
- uint32_t comp[5];
- uint32_t mask[5];
-};
-
-static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
+static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
{
/* XXX: TODO */
return 0;
}
-static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
+static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
{
/* XXX: TODO */
}
-static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
{
/* XXX: TODO */
}
static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_gpt_t *gpt = opaque;
+ Ppc405GptState *gpt = PPC405_GPT(opaque);
uint32_t ret;
int idx;
@@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_gpt_t *gpt = opaque;
+ Ppc405GptState *gpt = PPC405_GPT(opaque);
int idx;
trace_ppc4xx_gpt_write(addr, size, value);
@@ -1116,20 +1100,18 @@ static const MemoryRegionOps gpt_ops = {
static void ppc4xx_gpt_cb (void *opaque)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *gpt = PPC405_GPT(opaque);
- gpt = opaque;
ppc4xx_gpt_set_irqs(gpt);
ppc4xx_gpt_set_outputs(gpt);
ppc4xx_gpt_compute_timer(gpt);
}
-static void ppc4xx_gpt_reset (void *opaque)
+static void ppc405_gpt_reset(DeviceState *dev)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *gpt = PPC405_GPT(dev);
int i;
- gpt = opaque;
timer_del(gpt->timer);
gpt->oe = 0x00000000;
gpt->ol = 0x00000000;
@@ -1142,21 +1124,28 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
-static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
+static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *s = PPC405_GPT(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
- trace_ppc4xx_gpt_init(base);
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
+ memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0x0d4);
+ sysbus_init_mmio(sbd, &s->iomem);
- gpt = g_new0(ppc4xx_gpt_t, 1);
- for (i = 0; i < 5; i++) {
- gpt->irqs[i] = irqs[i];
+ for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
+ sysbus_init_irq(sbd, &s->irqs[i]);
}
- gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
- memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
- memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
- qemu_register_reset(ppc4xx_gpt_reset, gpt);
+}
+
+static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_gpt_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_gpt_reset;
}
/*****************************************************************************/
@@ -1422,14 +1411,17 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
+
+ object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
+ qemu_irq dma_irqs[4], mal_irqs[4];
CPUPPCState *env;
Error *err = NULL;
+ int i;
/* XXX: fix this ? */
memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
@@ -1528,12 +1520,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc405_ocm_init(env);
/* GPT */
- gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
- gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
- gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
- gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
- gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
- ppc4xx_gpt_init(0xef600000, gpt_irqs);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, 0xef600000);
+
+ for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
+ qdev_get_gpio_in(s->uic, 19 + i));
+ }
/* MAL */
mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
@@ -1565,6 +1560,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_GPT,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405GptState),
+ .class_init = ppc405_gpt_class_init,
+ }, {
.name = TYPE_PPC405_CPC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405CpcState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 08/19] ppc/ppc405: QOM'ify GPT
2022-08-01 13:10 ` [PATCH 08/19] ppc/ppc405: QOM'ify GPT Cédric Le Goater
@ 2022-08-03 9:15 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:15 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 22 ++++++++++++
> hw/ppc/ppc405_uc.c | 90 +++++++++++++++++++++++-----------------------
> 2 files changed, 67 insertions(+), 45 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index d51fb5094e95..f7c0eb1d0008 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,27 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +/* General purpose timers */
> +#define TYPE_PPC405_GPT "ppc405-gpt"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
> +struct Ppc405GptState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +
> + int64_t tb_offset;
> + uint32_t tb_freq;
> + QEMUTimer *timer;
> + qemu_irq irqs[5];
> + uint32_t oe;
> + uint32_t ol;
> + uint32_t im;
> + uint32_t is;
> + uint32_t ie;
> + uint32_t comp[5];
> + uint32_t mask[5];
> +};
> +
> #define TYPE_PPC405_CPC "ppc405-cpc"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
>
> @@ -119,6 +140,7 @@ struct Ppc405SoCState {
> PowerPCCPU cpu;
> DeviceState *uic;
> Ppc405CpcState cpc;
> + Ppc405GptState gpt;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 20a3e5543423..0f5e4ec15f14 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env)
>
> /*****************************************************************************/
> /* General purpose timers */
> -typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
> -struct ppc4xx_gpt_t {
> - MemoryRegion iomem;
> - int64_t tb_offset;
> - uint32_t tb_freq;
> - QEMUTimer *timer;
> - qemu_irq irqs[5];
> - uint32_t oe;
> - uint32_t ol;
> - uint32_t im;
> - uint32_t is;
> - uint32_t ie;
> - uint32_t comp[5];
> - uint32_t mask[5];
> -};
> -
> -static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
> +static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
> {
> /* XXX: TODO */
> return 0;
> }
>
> -static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
> +static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
> {
> /* XXX: TODO */
> }
>
> -static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
> +static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
> {
> uint32_t mask;
> int i;
> @@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
> }
> }
>
> -static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
> +static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
> {
> uint32_t mask;
> int i;
> @@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
> }
> }
>
> -static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
> +static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
> {
> /* XXX: TODO */
> }
>
> static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
> {
> - ppc4xx_gpt_t *gpt = opaque;
> + Ppc405GptState *gpt = PPC405_GPT(opaque);
> uint32_t ret;
> int idx;
>
> @@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
> static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
> unsigned size)
> {
> - ppc4xx_gpt_t *gpt = opaque;
> + Ppc405GptState *gpt = PPC405_GPT(opaque);
> int idx;
>
> trace_ppc4xx_gpt_write(addr, size, value);
> @@ -1116,20 +1100,18 @@ static const MemoryRegionOps gpt_ops = {
>
> static void ppc4xx_gpt_cb (void *opaque)
> {
> - ppc4xx_gpt_t *gpt;
> + Ppc405GptState *gpt = PPC405_GPT(opaque);
>
> - gpt = opaque;
> ppc4xx_gpt_set_irqs(gpt);
> ppc4xx_gpt_set_outputs(gpt);
> ppc4xx_gpt_compute_timer(gpt);
> }
>
> -static void ppc4xx_gpt_reset (void *opaque)
> +static void ppc405_gpt_reset(DeviceState *dev)
> {
> - ppc4xx_gpt_t *gpt;
> + Ppc405GptState *gpt = PPC405_GPT(dev);
> int i;
>
> - gpt = opaque;
> timer_del(gpt->timer);
> gpt->oe = 0x00000000;
> gpt->ol = 0x00000000;
> @@ -1142,21 +1124,28 @@ static void ppc4xx_gpt_reset (void *opaque)
> }
> }
>
> -static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
> +static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_gpt_t *gpt;
> + Ppc405GptState *s = PPC405_GPT(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> int i;
>
> - trace_ppc4xx_gpt_init(base);
> + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
> + memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0x0d4);
> + sysbus_init_mmio(sbd, &s->iomem);
>
> - gpt = g_new0(ppc4xx_gpt_t, 1);
> - for (i = 0; i < 5; i++) {
> - gpt->irqs[i] = irqs[i];
> + for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
> + sysbus_init_irq(sbd, &s->irqs[i]);
> }
> - gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
> - memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
> - memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
> - qemu_register_reset(ppc4xx_gpt_reset, gpt);
> +}
> +
> +static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_gpt_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_gpt_reset;
> }
>
> /*****************************************************************************/
> @@ -1422,14 +1411,17 @@ static void ppc405_soc_instance_init(Object *obj)
>
> object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
> object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
> +
> + object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> + qemu_irq dma_irqs[4], mal_irqs[4];
> CPUPPCState *env;
> Error *err = NULL;
> + int i;
>
> /* XXX: fix this ? */
> memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
> @@ -1528,12 +1520,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> ppc405_ocm_init(env);
>
> /* GPT */
> - gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
> - gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
> - gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
> - gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
> - gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
> - ppc4xx_gpt_init(0xef600000, gpt_irqs);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, 0xef600000);
> +
> + for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
> + qdev_get_gpio_in(s->uic, 19 + i));
> + }
>
> /* MAL */
> mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
> @@ -1565,6 +1560,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_GPT,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405GptState),
> + .class_init = ppc405_gpt_class_init,
> + }, {
> .name = TYPE_PPC405_CPC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(Ppc405CpcState),
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 09/19] ppc/ppc405: QOM'ify OCM
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (7 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 08/19] ppc/ppc405: QOM'ify GPT Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:16 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 10/19] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
` (9 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 18 ++++++++++++
hw/ppc/ppc405_uc.c | 73 ++++++++++++++++++++++++++++------------------
2 files changed, 63 insertions(+), 28 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index f7c0eb1d0008..e56363366cad 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,23 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* On Chip Memory */
+#define TYPE_PPC405_OCM "ppc405-ocm"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
+struct Ppc405OcmState {
+ SysBusDevice parent_obj;
+
+ PowerPCCPU *cpu;
+
+ MemoryRegion ram;
+ MemoryRegion isarc_ram;
+ MemoryRegion dsarc_ram;
+ uint32_t isarc;
+ uint32_t isacntl;
+ uint32_t dsarc;
+ uint32_t dsacntl;
+};
+
/* General purpose timers */
#define TYPE_PPC405_GPT "ppc405-gpt"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
@@ -141,6 +158,7 @@ struct Ppc405SoCState {
DeviceState *uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
+ Ppc405OcmState ocm;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 0f5e4ec15f14..59cade4c0680 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -773,20 +773,9 @@ enum {
OCM0_DSACNTL = 0x01B,
};
-typedef struct ppc405_ocm_t ppc405_ocm_t;
-struct ppc405_ocm_t {
- MemoryRegion ram;
- MemoryRegion isarc_ram;
- MemoryRegion dsarc_ram;
- uint32_t isarc;
- uint32_t isacntl;
- uint32_t dsarc;
- uint32_t dsacntl;
-};
-
-static void ocm_update_mappings (ppc405_ocm_t *ocm,
- uint32_t isarc, uint32_t isacntl,
- uint32_t dsarc, uint32_t dsacntl)
+static void ocm_update_mappings(Ppc405OcmState *ocm,
+ uint32_t isarc, uint32_t isacntl,
+ uint32_t dsarc, uint32_t dsacntl)
{
trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
ocm->isacntl, ocm->dsarc, ocm->dsacntl);
@@ -830,10 +819,9 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
static uint32_t dcr_read_ocm (void *opaque, int dcrn)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(opaque);
uint32_t ret;
- ocm = opaque;
switch (dcrn) {
case OCM0_ISARC:
ret = ocm->isarc;
@@ -857,10 +845,9 @@ static uint32_t dcr_read_ocm (void *opaque, int dcrn)
static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(opaque);
uint32_t isarc, dsarc, isacntl, dsacntl;
- ocm = opaque;
isarc = ocm->isarc;
dsarc = ocm->dsarc;
isacntl = ocm->isacntl;
@@ -886,12 +873,11 @@ static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
ocm->dsacntl = dsacntl;
}
-static void ocm_reset (void *opaque)
+static void ppc405_ocm_reset(DeviceState *dev)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(dev);
uint32_t isarc, dsarc, isacntl, dsacntl;
- ocm = opaque;
isarc = 0x00000000;
isacntl = 0x00000000;
dsarc = 0x00000000;
@@ -903,17 +889,21 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
-static void ppc405_ocm_init(CPUPPCState *env)
+static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(dev);
+ CPUPPCState *env;
+
+ assert(ocm->cpu);
+
+ env = &ocm->cpu->env;
- ocm = g_new0(ppc405_ocm_t, 1);
/* XXX: Size is 4096 or 0x04000000 */
- memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
+ memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
&error_fatal);
- memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
+ memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
&ocm->isarc_ram, 0, 4 * KiB);
- qemu_register_reset(&ocm_reset, ocm);
+
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_ISACNTL,
@@ -924,6 +914,22 @@ static void ppc405_ocm_init(CPUPPCState *env)
ocm, &dcr_read_ocm, &dcr_write_ocm);
}
+static Property ppc405_ocm_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc405OcmState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_ocm_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_ocm_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_ocm_reset;
+ device_class_set_props(dc, ppc405_ocm_properties);
+}
+
/*****************************************************************************/
/* General purpose timers */
static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
@@ -1413,6 +1419,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
+
+ object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1517,7 +1525,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* OCM */
- ppc405_ocm_init(env);
+ object_property_set_link(OBJECT(&s->ocm), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ocm), errp)) {
+ return;
+ }
/* GPT */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
@@ -1560,6 +1572,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_OCM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405OcmState),
+ .class_init = ppc405_ocm_class_init,
+ }, {
.name = TYPE_PPC405_GPT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GptState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 09/19] ppc/ppc405: QOM'ify OCM
2022-08-01 13:10 ` [PATCH 09/19] ppc/ppc405: QOM'ify OCM Cédric Le Goater
@ 2022-08-03 9:16 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:16 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 18 ++++++++++++
> hw/ppc/ppc405_uc.c | 73 ++++++++++++++++++++++++++++------------------
> 2 files changed, 63 insertions(+), 28 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index f7c0eb1d0008..e56363366cad 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,23 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +/* On Chip Memory */
> +#define TYPE_PPC405_OCM "ppc405-ocm"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
> +struct Ppc405OcmState {
> + SysBusDevice parent_obj;
> +
> + PowerPCCPU *cpu;
> +
> + MemoryRegion ram;
> + MemoryRegion isarc_ram;
> + MemoryRegion dsarc_ram;
> + uint32_t isarc;
> + uint32_t isacntl;
> + uint32_t dsarc;
> + uint32_t dsacntl;
> +};
> +
> /* General purpose timers */
> #define TYPE_PPC405_GPT "ppc405-gpt"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
> @@ -141,6 +158,7 @@ struct Ppc405SoCState {
> DeviceState *uic;
> Ppc405CpcState cpc;
> Ppc405GptState gpt;
> + Ppc405OcmState ocm;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 0f5e4ec15f14..59cade4c0680 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -773,20 +773,9 @@ enum {
> OCM0_DSACNTL = 0x01B,
> };
>
> -typedef struct ppc405_ocm_t ppc405_ocm_t;
> -struct ppc405_ocm_t {
> - MemoryRegion ram;
> - MemoryRegion isarc_ram;
> - MemoryRegion dsarc_ram;
> - uint32_t isarc;
> - uint32_t isacntl;
> - uint32_t dsarc;
> - uint32_t dsacntl;
> -};
> -
> -static void ocm_update_mappings (ppc405_ocm_t *ocm,
> - uint32_t isarc, uint32_t isacntl,
> - uint32_t dsarc, uint32_t dsacntl)
> +static void ocm_update_mappings(Ppc405OcmState *ocm,
> + uint32_t isarc, uint32_t isacntl,
> + uint32_t dsarc, uint32_t dsacntl)
> {
> trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
> ocm->isacntl, ocm->dsarc, ocm->dsacntl);
> @@ -830,10 +819,9 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
>
> static uint32_t dcr_read_ocm (void *opaque, int dcrn)
> {
> - ppc405_ocm_t *ocm;
> + Ppc405OcmState *ocm = PPC405_OCM(opaque);
> uint32_t ret;
>
> - ocm = opaque;
> switch (dcrn) {
> case OCM0_ISARC:
> ret = ocm->isarc;
> @@ -857,10 +845,9 @@ static uint32_t dcr_read_ocm (void *opaque, int dcrn)
>
> static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
> {
> - ppc405_ocm_t *ocm;
> + Ppc405OcmState *ocm = PPC405_OCM(opaque);
> uint32_t isarc, dsarc, isacntl, dsacntl;
>
> - ocm = opaque;
> isarc = ocm->isarc;
> dsarc = ocm->dsarc;
> isacntl = ocm->isacntl;
> @@ -886,12 +873,11 @@ static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
> ocm->dsacntl = dsacntl;
> }
>
> -static void ocm_reset (void *opaque)
> +static void ppc405_ocm_reset(DeviceState *dev)
> {
> - ppc405_ocm_t *ocm;
> + Ppc405OcmState *ocm = PPC405_OCM(dev);
> uint32_t isarc, dsarc, isacntl, dsacntl;
>
> - ocm = opaque;
> isarc = 0x00000000;
> isacntl = 0x00000000;
> dsarc = 0x00000000;
> @@ -903,17 +889,21 @@ static void ocm_reset (void *opaque)
> ocm->dsacntl = dsacntl;
> }
>
> -static void ppc405_ocm_init(CPUPPCState *env)
> +static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
> {
> - ppc405_ocm_t *ocm;
> + Ppc405OcmState *ocm = PPC405_OCM(dev);
> + CPUPPCState *env;
> +
> + assert(ocm->cpu);
> +
> + env = &ocm->cpu->env;
>
> - ocm = g_new0(ppc405_ocm_t, 1);
> /* XXX: Size is 4096 or 0x04000000 */
> - memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
> + memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
> &error_fatal);
> - memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
> + memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
> &ocm->isarc_ram, 0, 4 * KiB);
> - qemu_register_reset(&ocm_reset, ocm);
> +
> ppc_dcr_register(env, OCM0_ISARC,
> ocm, &dcr_read_ocm, &dcr_write_ocm);
> ppc_dcr_register(env, OCM0_ISACNTL,
> @@ -924,6 +914,22 @@ static void ppc405_ocm_init(CPUPPCState *env)
> ocm, &dcr_read_ocm, &dcr_write_ocm);
> }
>
> +static Property ppc405_ocm_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc405OcmState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_ocm_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_ocm_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_ocm_reset;
> + device_class_set_props(dc, ppc405_ocm_properties);
> +}
> +
> /*****************************************************************************/
> /* General purpose timers */
> static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
> @@ -1413,6 +1419,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
>
> object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
> +
> + object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1517,7 +1525,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* OCM */
> - ppc405_ocm_init(env);
> + object_property_set_link(OBJECT(&s->ocm), "cpu", OBJECT(&s->cpu),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ocm), errp)) {
> + return;
> + }
>
> /* GPT */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
> @@ -1560,6 +1572,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_OCM,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405OcmState),
> + .class_init = ppc405_ocm_class_init,
> + }, {
> .name = TYPE_PPC405_GPT,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc405GptState),
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 10/19] ppc/ppc405: QOM'ify GPIO
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (8 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 09/19] ppc/ppc405: QOM'ify OCM Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:24 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 11/19] ppc/ppc405: QOM'ify DMA Cédric Le Goater
` (8 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 21 +++++++++++++++++++
hw/ppc/ppc405_uc.c | 50 +++++++++++++++++++++-------------------------
2 files changed, 44 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index e56363366cad..46366c3b8a19 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,26 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* GPIO */
+#define TYPE_PPC405_GPIO "ppc405-gpio"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
+struct Ppc405GpioState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion io;
+ uint32_t or;
+ uint32_t tcr;
+ uint32_t osrh;
+ uint32_t osrl;
+ uint32_t tsrh;
+ uint32_t tsrl;
+ uint32_t odr;
+ uint32_t ir;
+ uint32_t rr1;
+ uint32_t isr1h;
+ uint32_t isr1l;
+};
+
/* On Chip Memory */
#define TYPE_PPC405_OCM "ppc405-ocm"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
@@ -159,6 +179,7 @@ struct Ppc405SoCState {
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
+ Ppc405GpioState gpio;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 59cade4c0680..a6c4e6934ffc 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -713,23 +713,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
}
/*****************************************************************************/
-/* GPIO */
-typedef struct ppc405_gpio_t ppc405_gpio_t;
-struct ppc405_gpio_t {
- MemoryRegion io;
- uint32_t or;
- uint32_t tcr;
- uint32_t osrh;
- uint32_t osrl;
- uint32_t tsrh;
- uint32_t tsrl;
- uint32_t odr;
- uint32_t ir;
- uint32_t rr1;
- uint32_t isr1h;
- uint32_t isr1l;
-};
-
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
trace_ppc405_gpio_read(addr, size);
@@ -748,20 +731,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc405_gpio_reset (void *opaque)
+static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
{
+ Ppc405GpioState *s = PPC405_GPIO(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
+ 0x038);
+ sysbus_init_mmio(sbd, &s->io);
}
-static void ppc405_gpio_init(hwaddr base)
+static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
{
- ppc405_gpio_t *gpio;
-
- trace_ppc405_gpio_init(base);
+ DeviceClass *dc = DEVICE_CLASS(oc);
- gpio = g_new0(ppc405_gpio_t, 1);
- memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
- memory_region_add_subregion(get_system_memory(), base, &gpio->io);
- qemu_register_reset(&ppc405_gpio_reset, gpio);
+ dc->realize = ppc405_gpio_realize;
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1421,6 +1406,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
+
+ object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1507,8 +1494,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
qdev_get_gpio_in(s->uic, 2));
+
/* GPIO */
- ppc405_gpio_init(0xef600700);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, 0xef600700);
/* Serial ports */
if (serial_hd(0) != NULL) {
@@ -1572,6 +1563,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405GpioState),
+ .class_init = ppc405_gpio_class_init,
+ }, {
.name = TYPE_PPC405_OCM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OcmState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 10/19] ppc/ppc405: QOM'ify GPIO
2022-08-01 13:10 ` [PATCH 10/19] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
@ 2022-08-03 9:24 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:24 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 21 +++++++++++++++++++
> hw/ppc/ppc405_uc.c | 50 +++++++++++++++++++++-------------------------
> 2 files changed, 44 insertions(+), 27 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index e56363366cad..46366c3b8a19 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,26 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +/* GPIO */
> +#define TYPE_PPC405_GPIO "ppc405-gpio"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
> +struct Ppc405GpioState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion io;
> + uint32_t or;
> + uint32_t tcr;
> + uint32_t osrh;
> + uint32_t osrl;
> + uint32_t tsrh;
> + uint32_t tsrl;
> + uint32_t odr;
> + uint32_t ir;
> + uint32_t rr1;
> + uint32_t isr1h;
> + uint32_t isr1l;
> +};
> +
> /* On Chip Memory */
> #define TYPE_PPC405_OCM "ppc405-ocm"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
> @@ -159,6 +179,7 @@ struct Ppc405SoCState {
> Ppc405CpcState cpc;
> Ppc405GptState gpt;
> Ppc405OcmState ocm;
> + Ppc405GpioState gpio;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 59cade4c0680..a6c4e6934ffc 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -713,23 +713,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
> }
>
> /*****************************************************************************/
> -/* GPIO */
> -typedef struct ppc405_gpio_t ppc405_gpio_t;
> -struct ppc405_gpio_t {
> - MemoryRegion io;
> - uint32_t or;
> - uint32_t tcr;
> - uint32_t osrh;
> - uint32_t osrl;
> - uint32_t tsrh;
> - uint32_t tsrl;
> - uint32_t odr;
> - uint32_t ir;
> - uint32_t rr1;
> - uint32_t isr1h;
> - uint32_t isr1l;
> -};
> -
> static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
> {
> trace_ppc405_gpio_read(addr, size);
> @@ -748,20 +731,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -static void ppc405_gpio_reset (void *opaque)
> +static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
> {
> + Ppc405GpioState *s = PPC405_GPIO(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
> + 0x038);
> + sysbus_init_mmio(sbd, &s->io);
> }
>
> -static void ppc405_gpio_init(hwaddr base)
> +static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
> {
> - ppc405_gpio_t *gpio;
> -
> - trace_ppc405_gpio_init(base);
> + DeviceClass *dc = DEVICE_CLASS(oc);
>
> - gpio = g_new0(ppc405_gpio_t, 1);
> - memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
> - memory_region_add_subregion(get_system_memory(), base, &gpio->io);
> - qemu_register_reset(&ppc405_gpio_reset, gpio);
> + dc->realize = ppc405_gpio_realize;
> + dc->user_creatable = false;
> }
>
> /*****************************************************************************/
> @@ -1421,6 +1406,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
>
> object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
> +
> + object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1507,8 +1494,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> qdev_get_gpio_in(s->uic, 2));
> +
> /* GPIO */
> - ppc405_gpio_init(0xef600700);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, 0xef600700);
>
> /* Serial ports */
> if (serial_hd(0) != NULL) {
> @@ -1572,6 +1563,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_GPIO,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405GpioState),
> + .class_init = ppc405_gpio_class_init,
> + }, {
> .name = TYPE_PPC405_OCM,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc405OcmState),
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 11/19] ppc/ppc405: QOM'ify DMA
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (9 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 10/19] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:25 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 12/19] ppc/ppc405: QOM'ify EBC Cédric Le Goater
` (7 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 23 +++++++++++++
hw/ppc/ppc405_uc.c | 80 +++++++++++++++++++++++++++++-----------------
2 files changed, 73 insertions(+), 30 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 46366c3b8a19..bd662b2444ff 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,28 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+
+
+/* DMA controller */
+#define TYPE_PPC405_DMA "ppc405-dma"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
+struct Ppc405DmaState {
+ SysBusDevice parent_obj;
+
+ PowerPCCPU *cpu;
+
+ qemu_irq irqs[4];
+ uint32_t cr[4];
+ uint32_t ct[4];
+ uint32_t da[4];
+ uint32_t sa[4];
+ uint32_t sg[4];
+ uint32_t sr;
+ uint32_t sgc;
+ uint32_t slp;
+ uint32_t pol;
+};
+
/* GPIO */
#define TYPE_PPC405_GPIO "ppc405-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
@@ -180,6 +202,7 @@ struct Ppc405SoCState {
Ppc405GptState gpt;
Ppc405OcmState ocm;
Ppc405GpioState gpio;
+ Ppc405DmaState dma;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index a6c4e6934ffc..2978a2665a4f 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -613,35 +613,20 @@ enum {
DMA0_POL = 0x126,
};
-typedef struct ppc405_dma_t ppc405_dma_t;
-struct ppc405_dma_t {
- qemu_irq irqs[4];
- uint32_t cr[4];
- uint32_t ct[4];
- uint32_t da[4];
- uint32_t sa[4];
- uint32_t sg[4];
- uint32_t sr;
- uint32_t sgc;
- uint32_t slp;
- uint32_t pol;
-};
-
-static uint32_t dcr_read_dma (void *opaque, int dcrn)
+static uint32_t dcr_read_dma(void *opaque, int dcrn)
{
return 0;
}
-static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
{
}
-static void ppc405_dma_reset (void *opaque)
+static void ppc405_dma_reset(DeviceState *dev)
{
- ppc405_dma_t *dma;
+ Ppc405DmaState *dma = PPC405_DMA(dev);
int i;
- dma = opaque;
for (i = 0; i < 4; i++) {
dma->cr[i] = 0x00000000;
dma->ct[i] = 0x00000000;
@@ -655,13 +640,20 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
-static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
+static void ppc405_dma_realize(DeviceState *dev, Error **errp)
{
- ppc405_dma_t *dma;
+ Ppc405DmaState *dma = PPC405_DMA(dev);
+ CPUPPCState *env;
+ int i;
+
+ assert(dma->cpu);
+
+ env = &dma->cpu->env;
+
+ for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]);
+ }
- dma = g_new0(ppc405_dma_t, 1);
- memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
- qemu_register_reset(&ppc405_dma_reset, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT0,
@@ -712,6 +704,22 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
dma, &dcr_read_dma, &dcr_write_dma);
}
+static Property ppc405_dma_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc405DmaState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_dma_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_dma_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_dma_reset;
+ device_class_set_props(dc, ppc405_dma_properties);
+}
+
/*****************************************************************************/
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
@@ -1408,12 +1416,14 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
+
+ object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq dma_irqs[4], mal_irqs[4];
+ qemu_irq mal_irqs[4];
CPUPPCState *env;
Error *err = NULL;
int i;
@@ -1485,11 +1495,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc405_ebc_init(env);
/* DMA controller */
- dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
- dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
- dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
- dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
- ppc405_dma_init(env, dma_irqs);
+ object_property_set_link(OBJECT(&s->dma), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp)) {
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+ qdev_get_gpio_in(s->uic, 5 + i));
+ }
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
@@ -1563,6 +1578,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_DMA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405DmaState),
+ .class_init = ppc405_dma_class_init,
+ }, {
.name = TYPE_PPC405_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GpioState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 11/19] ppc/ppc405: QOM'ify DMA
2022-08-01 13:10 ` [PATCH 11/19] ppc/ppc405: QOM'ify DMA Cédric Le Goater
@ 2022-08-03 9:25 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:25 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 23 +++++++++++++
> hw/ppc/ppc405_uc.c | 80 +++++++++++++++++++++++++++++-----------------
> 2 files changed, 73 insertions(+), 30 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 46366c3b8a19..bd662b2444ff 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,28 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +
> +
> +/* DMA controller */
> +#define TYPE_PPC405_DMA "ppc405-dma"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
> +struct Ppc405DmaState {
> + SysBusDevice parent_obj;
> +
> + PowerPCCPU *cpu;
> +
> + qemu_irq irqs[4];
> + uint32_t cr[4];
> + uint32_t ct[4];
> + uint32_t da[4];
> + uint32_t sa[4];
> + uint32_t sg[4];
> + uint32_t sr;
> + uint32_t sgc;
> + uint32_t slp;
> + uint32_t pol;
> +};
> +
> /* GPIO */
> #define TYPE_PPC405_GPIO "ppc405-gpio"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
> @@ -180,6 +202,7 @@ struct Ppc405SoCState {
> Ppc405GptState gpt;
> Ppc405OcmState ocm;
> Ppc405GpioState gpio;
> + Ppc405DmaState dma;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index a6c4e6934ffc..2978a2665a4f 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -613,35 +613,20 @@ enum {
> DMA0_POL = 0x126,
> };
>
> -typedef struct ppc405_dma_t ppc405_dma_t;
> -struct ppc405_dma_t {
> - qemu_irq irqs[4];
> - uint32_t cr[4];
> - uint32_t ct[4];
> - uint32_t da[4];
> - uint32_t sa[4];
> - uint32_t sg[4];
> - uint32_t sr;
> - uint32_t sgc;
> - uint32_t slp;
> - uint32_t pol;
> -};
> -
> -static uint32_t dcr_read_dma (void *opaque, int dcrn)
> +static uint32_t dcr_read_dma(void *opaque, int dcrn)
> {
> return 0;
> }
>
> -static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
> +static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
> {
> }
>
> -static void ppc405_dma_reset (void *opaque)
> +static void ppc405_dma_reset(DeviceState *dev)
> {
> - ppc405_dma_t *dma;
> + Ppc405DmaState *dma = PPC405_DMA(dev);
> int i;
>
> - dma = opaque;
> for (i = 0; i < 4; i++) {
> dma->cr[i] = 0x00000000;
> dma->ct[i] = 0x00000000;
> @@ -655,13 +640,20 @@ static void ppc405_dma_reset (void *opaque)
> dma->pol = 0x00000000;
> }
>
> -static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
> +static void ppc405_dma_realize(DeviceState *dev, Error **errp)
> {
> - ppc405_dma_t *dma;
> + Ppc405DmaState *dma = PPC405_DMA(dev);
> + CPUPPCState *env;
> + int i;
> +
> + assert(dma->cpu);
> +
> + env = &dma->cpu->env;
> +
> + for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]);
> + }
>
> - dma = g_new0(ppc405_dma_t, 1);
> - memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
> - qemu_register_reset(&ppc405_dma_reset, dma);
> ppc_dcr_register(env, DMA0_CR0,
> dma, &dcr_read_dma, &dcr_write_dma);
> ppc_dcr_register(env, DMA0_CT0,
> @@ -712,6 +704,22 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
> dma, &dcr_read_dma, &dcr_write_dma);
> }
>
> +static Property ppc405_dma_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc405DmaState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_dma_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_dma_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_dma_reset;
> + device_class_set_props(dc, ppc405_dma_properties);
> +}
> +
> /*****************************************************************************/
> static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
> {
> @@ -1408,12 +1416,14 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
>
> object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
> +
> + object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - qemu_irq dma_irqs[4], mal_irqs[4];
> + qemu_irq mal_irqs[4];
> CPUPPCState *env;
> Error *err = NULL;
> int i;
> @@ -1485,11 +1495,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> ppc405_ebc_init(env);
>
> /* DMA controller */
> - dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
> - dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
> - dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
> - dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
> - ppc405_dma_init(env, dma_irqs);
> + object_property_set_link(OBJECT(&s->dma), "cpu", OBJECT(&s->cpu),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp)) {
> + return;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> + qdev_get_gpio_in(s->uic, 5 + i));
> + }
>
> /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> @@ -1563,6 +1578,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_DMA,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405DmaState),
> + .class_init = ppc405_dma_class_init,
> + }, {
> .name = TYPE_PPC405_GPIO,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc405GpioState),
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 12/19] ppc/ppc405: QOM'ify EBC
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (10 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 11/19] ppc/ppc405: QOM'ify DMA Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:26 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 13/19] ppc/ppc405: QOM'ify OPBA Cédric Le Goater
` (6 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 16 +++++++++++
hw/ppc/ppc405_uc.c | 71 +++++++++++++++++++++++++++++++---------------
2 files changed, 64 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index bd662b2444ff..f1acb37185f5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,7 +65,22 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* Peripheral controller */
+#define TYPE_PPC405_EBC "ppc405-ebc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
+struct Ppc405EbcState {
+ DeviceState parent_obj;
+
+ PowerPCCPU *cpu;
+ uint32_t addr;
+ uint32_t bcr[8];
+ uint32_t bap[8];
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+ uint32_t cfg;
+};
/* DMA controller */
#define TYPE_PPC405_DMA "ppc405-dma"
@@ -203,6 +218,7 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+ Ppc405EbcState ebc;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2978a2665a4f..8d73b8c2dff0 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -393,17 +393,6 @@ static void ppc4xx_opba_init(hwaddr base)
/*****************************************************************************/
/* Peripheral controller */
-typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
-struct ppc4xx_ebc_t {
- uint32_t addr;
- uint32_t bcr[8];
- uint32_t bap[8];
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
- uint32_t cfg;
-};
-
enum {
EBC0_CFGADDR = 0x012,
EBC0_CFGDATA = 0x013,
@@ -411,10 +400,9 @@ enum {
static uint32_t dcr_read_ebc (void *opaque, int dcrn)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(opaque);
uint32_t ret;
- ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ret = ebc->addr;
@@ -496,9 +484,8 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn)
static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(opaque);
- ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ebc->addr = val;
@@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
}
}
-static void ebc_reset (void *opaque)
+static void ppc405_ebc_reset(DeviceState *dev)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(dev);
int i;
- ebc = opaque;
ebc->addr = 0x00000000;
ebc->bap[0] = 0x7F8FFE80;
ebc->bcr[0] = 0xFFE28000;
@@ -572,18 +558,46 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
-void ppc405_ebc_init(CPUPPCState *env)
+static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(dev);
+ CPUPPCState *env;
+
+ assert(ebc->cpu);
+
+ env = &ebc->cpu->env;
- ebc = g_new0(ppc4xx_ebc_t, 1);
- qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc_dcr_register(env, EBC0_CFGDATA,
ebc, &dcr_read_ebc, &dcr_write_ebc);
}
+static Property ppc405_ebc_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc405EbcState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_ebc_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_ebc_reset;
+ device_class_set_props(dc, ppc405_ebc_properties);
+}
+
+void ppc405_ebc_init(CPUPPCState *env)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ DeviceState *dev = qdev_new(TYPE_PPC405_EBC);
+
+ object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
+}
+
/*****************************************************************************/
/* DMA controller */
enum {
@@ -1418,6 +1432,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
+
+ object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1492,7 +1508,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->ram_bases, s->ram_sizes, s->do_dram_init);
/* External bus controller */
- ppc405_ebc_init(env);
+ object_property_set_link(OBJECT(&s->ebc), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&s->ebc), NULL, errp)) {
+ return;
+ }
/* DMA controller */
object_property_set_link(OBJECT(&s->dma), "cpu", OBJECT(&s->cpu),
@@ -1578,6 +1598,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_EBC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405EbcState),
+ .class_init = ppc405_ebc_class_init,
+ }, {
.name = TYPE_PPC405_DMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405DmaState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 12/19] ppc/ppc405: QOM'ify EBC
2022-08-01 13:10 ` [PATCH 12/19] ppc/ppc405: QOM'ify EBC Cédric Le Goater
@ 2022-08-03 9:26 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:26 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 16 +++++++++++
> hw/ppc/ppc405_uc.c | 71 +++++++++++++++++++++++++++++++---------------
> 2 files changed, 64 insertions(+), 23 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index bd662b2444ff..f1acb37185f5 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,7 +65,22 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +/* Peripheral controller */
> +#define TYPE_PPC405_EBC "ppc405-ebc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
> +struct Ppc405EbcState {
> + DeviceState parent_obj;
> +
> + PowerPCCPU *cpu;
>
> + uint32_t addr;
> + uint32_t bcr[8];
> + uint32_t bap[8];
> + uint32_t bear;
> + uint32_t besr0;
> + uint32_t besr1;
> + uint32_t cfg;
> +};
>
> /* DMA controller */
> #define TYPE_PPC405_DMA "ppc405-dma"
> @@ -203,6 +218,7 @@ struct Ppc405SoCState {
> Ppc405OcmState ocm;
> Ppc405GpioState gpio;
> Ppc405DmaState dma;
> + Ppc405EbcState ebc;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 2978a2665a4f..8d73b8c2dff0 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -393,17 +393,6 @@ static void ppc4xx_opba_init(hwaddr base)
>
> /*****************************************************************************/
> /* Peripheral controller */
> -typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
> -struct ppc4xx_ebc_t {
> - uint32_t addr;
> - uint32_t bcr[8];
> - uint32_t bap[8];
> - uint32_t bear;
> - uint32_t besr0;
> - uint32_t besr1;
> - uint32_t cfg;
> -};
> -
> enum {
> EBC0_CFGADDR = 0x012,
> EBC0_CFGDATA = 0x013,
> @@ -411,10 +400,9 @@ enum {
>
> static uint32_t dcr_read_ebc (void *opaque, int dcrn)
> {
> - ppc4xx_ebc_t *ebc;
> + Ppc405EbcState *ebc = PPC405_EBC(opaque);
> uint32_t ret;
>
> - ebc = opaque;
> switch (dcrn) {
> case EBC0_CFGADDR:
> ret = ebc->addr;
> @@ -496,9 +484,8 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn)
>
> static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
> {
> - ppc4xx_ebc_t *ebc;
> + Ppc405EbcState *ebc = PPC405_EBC(opaque);
>
> - ebc = opaque;
> switch (dcrn) {
> case EBC0_CFGADDR:
> ebc->addr = val;
> @@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -static void ebc_reset (void *opaque)
> +static void ppc405_ebc_reset(DeviceState *dev)
> {
> - ppc4xx_ebc_t *ebc;
> + Ppc405EbcState *ebc = PPC405_EBC(dev);
> int i;
>
> - ebc = opaque;
> ebc->addr = 0x00000000;
> ebc->bap[0] = 0x7F8FFE80;
> ebc->bcr[0] = 0xFFE28000;
> @@ -572,18 +558,46 @@ static void ebc_reset (void *opaque)
> ebc->cfg = 0x80400000;
> }
>
> -void ppc405_ebc_init(CPUPPCState *env)
> +static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_ebc_t *ebc;
> + Ppc405EbcState *ebc = PPC405_EBC(dev);
> + CPUPPCState *env;
> +
> + assert(ebc->cpu);
> +
> + env = &ebc->cpu->env;
>
> - ebc = g_new0(ppc4xx_ebc_t, 1);
> - qemu_register_reset(&ebc_reset, ebc);
> ppc_dcr_register(env, EBC0_CFGADDR,
> ebc, &dcr_read_ebc, &dcr_write_ebc);
> ppc_dcr_register(env, EBC0_CFGDATA,
> ebc, &dcr_read_ebc, &dcr_write_ebc);
> }
>
> +static Property ppc405_ebc_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc405EbcState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_ebc_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_ebc_reset;
> + device_class_set_props(dc, ppc405_ebc_properties);
> +}
> +
> +void ppc405_ebc_init(CPUPPCState *env)
> +{
> + PowerPCCPU *cpu = env_archcpu(env);
> + DeviceState *dev = qdev_new(TYPE_PPC405_EBC);
> +
> + object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort);
> + qdev_realize_and_unref(dev, NULL, &error_fatal);
> +}
> +
> /*****************************************************************************/
> /* DMA controller */
> enum {
> @@ -1418,6 +1432,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
>
> object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
> +
> + object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1492,7 +1508,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> s->ram_bases, s->ram_sizes, s->do_dram_init);
>
> /* External bus controller */
> - ppc405_ebc_init(env);
> + object_property_set_link(OBJECT(&s->ebc), "cpu", OBJECT(&s->cpu),
> + &error_abort);
> + if (!qdev_realize(DEVICE(&s->ebc), NULL, errp)) {
> + return;
> + }
>
> /* DMA controller */
> object_property_set_link(OBJECT(&s->dma), "cpu", OBJECT(&s->cpu),
> @@ -1578,6 +1598,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_EBC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(Ppc405EbcState),
> + .class_init = ppc405_ebc_class_init,
> + }, {
> .name = TYPE_PPC405_DMA,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc405DmaState),
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 13/19] ppc/ppc405: QOM'ify OPBA
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (11 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 12/19] ppc/ppc405: QOM'ify EBC Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:27 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 14/19] ppc/ppc405: QOM'ify POB Cédric Le Goater
` (5 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 12 ++++++++++++
hw/ppc/ppc405_uc.c | 47 +++++++++++++++++++++++++++-------------------
2 files changed, 40 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index f1acb37185f5..ebff00bdad80 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,17 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* OPB arbitrer */
+#define TYPE_PPC405_OPBA "ppc405-opba"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
+struct Ppc405OpbaState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion io;
+ uint8_t cr;
+ uint8_t pr;
+};
+
/* Peripheral controller */
#define TYPE_PPC405_EBC "ppc405-ebc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
@@ -219,6 +230,7 @@ struct Ppc405SoCState {
Ppc405GpioState gpio;
Ppc405DmaState dma;
Ppc405EbcState ebc;
+ Ppc405OpbaState opba;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8d73b8c2dff0..c5de00de7981 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -310,16 +310,10 @@ static void ppc4xx_pob_init(CPUPPCState *env)
/*****************************************************************************/
/* OPB arbitrer */
-typedef struct ppc4xx_opba_t ppc4xx_opba_t;
-struct ppc4xx_opba_t {
- MemoryRegion io;
- uint8_t cr;
- uint8_t pr;
-};
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_opba_t *opba = opaque;
+ Ppc405OpbaState *opba = PPC405_OPBA(opaque);
uint32_t ret;
switch (addr) {
@@ -341,7 +335,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_opba_t *opba = opaque;
+ Ppc405OpbaState *opba = PPC405_OPBA(opaque);
trace_opba_writeb(addr, value);
@@ -366,25 +360,30 @@ static const MemoryRegionOps opba_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ppc4xx_opba_reset (void *opaque)
+static void ppc405_opba_reset(DeviceState *dev)
{
- ppc4xx_opba_t *opba;
+ Ppc405OpbaState *opba = PPC405_OPBA(dev);
- opba = opaque;
opba->cr = 0x00; /* No dynamic priorities - park disabled */
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(hwaddr base)
+static void ppc405_opba_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_opba_t *opba;
+ Ppc405OpbaState *s = PPC405_OPBA(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- trace_opba_init(base);
+ memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 0x002);
+ sysbus_init_mmio(sbd, &s->io);
+}
+
+static void ppc405_opba_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
- opba = g_new0(ppc4xx_opba_t, 1);
- memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
- memory_region_add_subregion(get_system_memory(), base, &opba->io);
- qemu_register_reset(ppc4xx_opba_reset, opba);
+ dc->realize = ppc405_opba_realize;
+ dc->reset = ppc405_opba_reset;
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1434,6 +1433,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
+
+ object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1486,7 +1487,10 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_pob_init(env);
/* OBP arbitrer */
- ppc4xx_opba_init(0xef600600);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
@@ -1598,6 +1602,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_OPBA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405OpbaState),
+ .class_init = ppc405_opba_class_init,
+ }, {
.name = TYPE_PPC405_EBC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405EbcState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 13/19] ppc/ppc405: QOM'ify OPBA
2022-08-01 13:10 ` [PATCH 13/19] ppc/ppc405: QOM'ify OPBA Cédric Le Goater
@ 2022-08-03 9:27 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:27 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 12 ++++++++++++
> hw/ppc/ppc405_uc.c | 47 +++++++++++++++++++++++++++-------------------
> 2 files changed, 40 insertions(+), 19 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index f1acb37185f5..ebff00bdad80 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,17 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +/* OPB arbitrer */
> +#define TYPE_PPC405_OPBA "ppc405-opba"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
> +struct Ppc405OpbaState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion io;
> + uint8_t cr;
> + uint8_t pr;
> +};
> +
> /* Peripheral controller */
> #define TYPE_PPC405_EBC "ppc405-ebc"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
> @@ -219,6 +230,7 @@ struct Ppc405SoCState {
> Ppc405GpioState gpio;
> Ppc405DmaState dma;
> Ppc405EbcState ebc;
> + Ppc405OpbaState opba;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 8d73b8c2dff0..c5de00de7981 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -310,16 +310,10 @@ static void ppc4xx_pob_init(CPUPPCState *env)
>
> /*****************************************************************************/
> /* OPB arbitrer */
> -typedef struct ppc4xx_opba_t ppc4xx_opba_t;
> -struct ppc4xx_opba_t {
> - MemoryRegion io;
> - uint8_t cr;
> - uint8_t pr;
> -};
>
> static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
> {
> - ppc4xx_opba_t *opba = opaque;
> + Ppc405OpbaState *opba = PPC405_OPBA(opaque);
> uint32_t ret;
>
> switch (addr) {
> @@ -341,7 +335,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
> static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
> unsigned size)
> {
> - ppc4xx_opba_t *opba = opaque;
> + Ppc405OpbaState *opba = PPC405_OPBA(opaque);
>
> trace_opba_writeb(addr, value);
>
> @@ -366,25 +360,30 @@ static const MemoryRegionOps opba_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> -static void ppc4xx_opba_reset (void *opaque)
> +static void ppc405_opba_reset(DeviceState *dev)
> {
> - ppc4xx_opba_t *opba;
> + Ppc405OpbaState *opba = PPC405_OPBA(dev);
>
> - opba = opaque;
> opba->cr = 0x00; /* No dynamic priorities - park disabled */
> opba->pr = 0x11;
> }
>
> -static void ppc4xx_opba_init(hwaddr base)
> +static void ppc405_opba_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_opba_t *opba;
> + Ppc405OpbaState *s = PPC405_OPBA(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
>
> - trace_opba_init(base);
> + memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 0x002);
> + sysbus_init_mmio(sbd, &s->io);
> +}
> +
> +static void ppc405_opba_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
>
> - opba = g_new0(ppc4xx_opba_t, 1);
> - memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
> - memory_region_add_subregion(get_system_memory(), base, &opba->io);
> - qemu_register_reset(ppc4xx_opba_reset, opba);
> + dc->realize = ppc405_opba_realize;
> + dc->reset = ppc405_opba_reset;
> + dc->user_creatable = false;
> }
>
> /*****************************************************************************/
> @@ -1434,6 +1433,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
>
> object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
> +
> + object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1486,7 +1487,10 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> ppc4xx_pob_init(env);
>
> /* OBP arbitrer */
> - ppc4xx_opba_init(0xef600600);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
>
> /* Universal interrupt controller */
> s->uic = qdev_new(TYPE_PPC_UIC);
> @@ -1598,6 +1602,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_OPBA,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405OpbaState),
> + .class_init = ppc405_opba_class_init,
> + }, {
> .name = TYPE_PPC405_EBC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(Ppc405EbcState),
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 14/19] ppc/ppc405: QOM'ify POB
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (12 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 13/19] ppc/ppc405: QOM'ify OPBA Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:27 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 15/19] ppc/ppc405: QOM'ify PLB Cédric Le Goater
` (4 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 14 +++++++++++
hw/ppc/ppc405_uc.c | 58 +++++++++++++++++++++++++++++++---------------
2 files changed, 53 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ebff00bdad80..d39d65cc86e4 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* PLB to OPB bridge */
+#define TYPE_PPC405_POB "ppc405-pob"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
+struct Ppc405PobState {
+ DeviceState parent_obj;
+
+ PowerPCCPU *cpu;
+
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+};
+
/* OPB arbitrer */
#define TYPE_PPC405_OPBA "ppc405-opba"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
@@ -231,6 +244,7 @@ struct Ppc405SoCState {
Ppc405DmaState dma;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
+ Ppc405PobState pob;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index c5de00de7981..218d911bca3c 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -234,19 +234,11 @@ enum {
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob_t ppc4xx_pob_t;
-struct ppc4xx_pob_t {
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
-};
-
static uint32_t dcr_read_pob (void *opaque, int dcrn)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(opaque);
uint32_t ret;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
ret = pob->bear;
@@ -268,9 +260,8 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(opaque);
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
/* Read only */
@@ -286,26 +277,44 @@ static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc4xx_pob_reset (void *opaque)
+static void ppc405_pob_reset(DeviceState *dev)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(dev);
- pob = opaque;
/* No error */
pob->bear = 0x00000000;
pob->besr0 = 0x0000000;
pob->besr1 = 0x0000000;
}
-static void ppc4xx_pob_init(CPUPPCState *env)
+static void ppc405_pob_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(dev);
+ CPUPPCState *env;
+
+ assert(pob->cpu);
+
+ env = &pob->cpu->env;
- pob = g_new0(ppc4xx_pob_t, 1);
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
- qemu_register_reset(ppc4xx_pob_reset, pob);
+}
+
+static Property ppc405_pob_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc405PobState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_pob_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_pob_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_pob_reset;
+ device_class_set_props(dc, ppc405_pob_properties);
}
/*****************************************************************************/
@@ -1435,6 +1444,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
+
+ object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1484,7 +1495,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
- ppc4xx_pob_init(env);
+ object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&s->pob), NULL, errp)) {
+ return;
+ }
/* OBP arbitrer */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
@@ -1602,6 +1617,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_POB,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405PobState),
+ .class_init = ppc405_pob_class_init,
+ }, {
.name = TYPE_PPC405_OPBA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 14/19] ppc/ppc405: QOM'ify POB
2022-08-01 13:10 ` [PATCH 14/19] ppc/ppc405: QOM'ify POB Cédric Le Goater
@ 2022-08-03 9:27 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:27 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 14 +++++++++++
> hw/ppc/ppc405_uc.c | 58 +++++++++++++++++++++++++++++++---------------
> 2 files changed, 53 insertions(+), 19 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index ebff00bdad80..d39d65cc86e4 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +/* PLB to OPB bridge */
> +#define TYPE_PPC405_POB "ppc405-pob"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
> +struct Ppc405PobState {
> + DeviceState parent_obj;
> +
> + PowerPCCPU *cpu;
> +
> + uint32_t bear;
> + uint32_t besr0;
> + uint32_t besr1;
> +};
> +
> /* OPB arbitrer */
> #define TYPE_PPC405_OPBA "ppc405-opba"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
> @@ -231,6 +244,7 @@ struct Ppc405SoCState {
> Ppc405DmaState dma;
> Ppc405EbcState ebc;
> Ppc405OpbaState opba;
> + Ppc405PobState pob;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index c5de00de7981..218d911bca3c 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -234,19 +234,11 @@ enum {
> POB0_BEAR = 0x0A4,
> };
>
> -typedef struct ppc4xx_pob_t ppc4xx_pob_t;
> -struct ppc4xx_pob_t {
> - uint32_t bear;
> - uint32_t besr0;
> - uint32_t besr1;
> -};
> -
> static uint32_t dcr_read_pob (void *opaque, int dcrn)
> {
> - ppc4xx_pob_t *pob;
> + Ppc405PobState *pob = PPC405_POB(opaque);
> uint32_t ret;
>
> - pob = opaque;
> switch (dcrn) {
> case POB0_BEAR:
> ret = pob->bear;
> @@ -268,9 +260,8 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
>
> static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
> {
> - ppc4xx_pob_t *pob;
> + Ppc405PobState *pob = PPC405_POB(opaque);
>
> - pob = opaque;
> switch (dcrn) {
> case POB0_BEAR:
> /* Read only */
> @@ -286,26 +277,44 @@ static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -static void ppc4xx_pob_reset (void *opaque)
> +static void ppc405_pob_reset(DeviceState *dev)
> {
> - ppc4xx_pob_t *pob;
> + Ppc405PobState *pob = PPC405_POB(dev);
>
> - pob = opaque;
> /* No error */
> pob->bear = 0x00000000;
> pob->besr0 = 0x0000000;
> pob->besr1 = 0x0000000;
> }
>
> -static void ppc4xx_pob_init(CPUPPCState *env)
> +static void ppc405_pob_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_pob_t *pob;
> + Ppc405PobState *pob = PPC405_POB(dev);
> + CPUPPCState *env;
> +
> + assert(pob->cpu);
> +
> + env = &pob->cpu->env;
>
> - pob = g_new0(ppc4xx_pob_t, 1);
> ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
> ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
> ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
> - qemu_register_reset(ppc4xx_pob_reset, pob);
> +}
> +
> +static Property ppc405_pob_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc405PobState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_pob_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_pob_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_pob_reset;
> + device_class_set_props(dc, ppc405_pob_properties);
> }
>
> /*****************************************************************************/
> @@ -1435,6 +1444,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
>
> object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
> +
> + object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1484,7 +1495,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> ppc4xx_plb_init(env);
>
> /* PLB to OPB bridge */
> - ppc4xx_pob_init(env);
> + object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu),
> + &error_abort);
> + if (!qdev_realize(DEVICE(&s->pob), NULL, errp)) {
> + return;
> + }
>
> /* OBP arbitrer */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
> @@ -1602,6 +1617,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_POB,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(Ppc405PobState),
> + .class_init = ppc405_pob_class_init,
> + }, {
> .name = TYPE_PPC405_OPBA,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc405OpbaState),
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 15/19] ppc/ppc405: QOM'ify PLB
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (13 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 14/19] ppc/ppc405: QOM'ify POB Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:43 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 16/19] ppc/ppc405: QOM'ify MAL Cédric Le Goater
` (3 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 14 ++++++++++
hw/ppc/ppc405_uc.c | 67 +++++++++++++++++++++++++++++++++-------------
2 files changed, 62 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d39d65cc86e4..4ff5cdcf5c65 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* Peripheral local bus arbitrer */
+#define TYPE_PPC405_PLB "ppc405-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
+struct Ppc405PlbState {
+ DeviceState parent_obj;
+
+ PowerPCCPU *cpu;
+
+ uint32_t acr;
+ uint32_t bear;
+ uint32_t besr;
+};
+
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -245,6 +258,7 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
+ Ppc405PlbState plb;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 218d911bca3c..45bcf3a6dd8a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -148,19 +148,11 @@ enum {
PLB4A1_ACR = 0x089,
};
-typedef struct ppc4xx_plb_t ppc4xx_plb_t;
-struct ppc4xx_plb_t {
- uint32_t acr;
- uint32_t bear;
- uint32_t besr;
-};
-
static uint32_t dcr_read_plb (void *opaque, int dcrn)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
uint32_t ret;
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
ret = plb->acr;
@@ -182,9 +174,8 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
/* We don't care about the actual parameters written as
@@ -202,28 +193,55 @@ static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc4xx_plb_reset (void *opaque)
+static void ppc405_plb_reset(DeviceState *dev)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(dev);
- plb = opaque;
plb->acr = 0x00000000;
plb->bear = 0x00000000;
plb->besr = 0x00000000;
}
-void ppc4xx_plb_init(CPUPPCState *env)
+static void ppc405_plb_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(dev);
+ CPUPPCState *env;
+
+ assert(plb->cpu);
+
+ env = &plb->cpu->env;
- plb = g_new0(ppc4xx_plb_t, 1);
ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- qemu_register_reset(ppc4xx_plb_reset, plb);
+}
+
+static Property ppc405_plb_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc405PlbState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_plb_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_plb_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_plb_reset;
+ device_class_set_props(dc, ppc405_plb_properties);
+}
+
+void ppc4xx_plb_init(CPUPPCState *env)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ DeviceState *dev = qdev_new(TYPE_PPC405_EBC);
+
+ object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
}
/*****************************************************************************/
@@ -1446,6 +1464,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
+
+ object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1492,7 +1512,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ object_property_set_link(OBJECT(&s->plb), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&s->plb), NULL, errp)) {
+ return;
+ }
/* PLB to OPB bridge */
object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu),
@@ -1617,6 +1641,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_PLB,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405PlbState),
+ .class_init = ppc405_plb_class_init,
+ }, {
.name = TYPE_PPC405_POB,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405PobState),
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 15/19] ppc/ppc405: QOM'ify PLB
2022-08-01 13:10 ` [PATCH 15/19] ppc/ppc405: QOM'ify PLB Cédric Le Goater
@ 2022-08-03 9:43 ` Daniel Henrique Barboza
2022-08-03 11:06 ` BALATON Zoltan
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:43 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 14 ++++++++++
> hw/ppc/ppc405_uc.c | 67 +++++++++++++++++++++++++++++++++-------------
> 2 files changed, 62 insertions(+), 19 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index d39d65cc86e4..4ff5cdcf5c65 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t {
>
> typedef struct Ppc405SoCState Ppc405SoCState;
>
> +/* Peripheral local bus arbitrer */
I wasn't aware that arbitrer is a word. Google says that 'arbitrer' is an
old form of 'arbitrator'.
I looked it up because I thought you misspelled 'arbiter', which is the name
of a Protoss combat unit in Starcraft. And it happens to be a synonym of
'arbitrator' as well.
'arbitrer' is fine, don't worry about it.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> +#define TYPE_PPC405_PLB "ppc405-plb"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
> +struct Ppc405PlbState {
> + DeviceState parent_obj;
> +
> + PowerPCCPU *cpu;
> +
> + uint32_t acr;
> + uint32_t bear;
> + uint32_t besr;
> +};
> +
> /* PLB to OPB bridge */
> #define TYPE_PPC405_POB "ppc405-pob"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
> @@ -245,6 +258,7 @@ struct Ppc405SoCState {
> Ppc405EbcState ebc;
> Ppc405OpbaState opba;
> Ppc405PobState pob;
> + Ppc405PlbState plb;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 218d911bca3c..45bcf3a6dd8a 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -148,19 +148,11 @@ enum {
> PLB4A1_ACR = 0x089,
> };
>
> -typedef struct ppc4xx_plb_t ppc4xx_plb_t;
> -struct ppc4xx_plb_t {
> - uint32_t acr;
> - uint32_t bear;
> - uint32_t besr;
> -};
> -
> static uint32_t dcr_read_plb (void *opaque, int dcrn)
> {
> - ppc4xx_plb_t *plb;
> + Ppc405PlbState *plb = PPC405_PLB(opaque);
> uint32_t ret;
>
> - plb = opaque;
> switch (dcrn) {
> case PLB0_ACR:
> ret = plb->acr;
> @@ -182,9 +174,8 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
>
> static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
> {
> - ppc4xx_plb_t *plb;
> + Ppc405PlbState *plb = PPC405_PLB(opaque);
>
> - plb = opaque;
> switch (dcrn) {
> case PLB0_ACR:
> /* We don't care about the actual parameters written as
> @@ -202,28 +193,55 @@ static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -static void ppc4xx_plb_reset (void *opaque)
> +static void ppc405_plb_reset(DeviceState *dev)
> {
> - ppc4xx_plb_t *plb;
> + Ppc405PlbState *plb = PPC405_PLB(dev);
>
> - plb = opaque;
> plb->acr = 0x00000000;
> plb->bear = 0x00000000;
> plb->besr = 0x00000000;
> }
>
> -void ppc4xx_plb_init(CPUPPCState *env)
> +static void ppc405_plb_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_plb_t *plb;
> + Ppc405PlbState *plb = PPC405_PLB(dev);
> + CPUPPCState *env;
> +
> + assert(plb->cpu);
> +
> + env = &plb->cpu->env;
>
> - plb = g_new0(ppc4xx_plb_t, 1);
> ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
> ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
> ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> - qemu_register_reset(ppc4xx_plb_reset, plb);
> +}
> +
> +static Property ppc405_plb_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc405PlbState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_plb_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_plb_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_plb_reset;
> + device_class_set_props(dc, ppc405_plb_properties);
> +}
> +
> +void ppc4xx_plb_init(CPUPPCState *env)
> +{
> + PowerPCCPU *cpu = env_archcpu(env);
> + DeviceState *dev = qdev_new(TYPE_PPC405_EBC);
> +
> + object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort);
> + qdev_realize_and_unref(dev, NULL, &error_fatal);
> }
>
> /*****************************************************************************/
> @@ -1446,6 +1464,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
>
> object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
> +
> + object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1492,7 +1512,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* PLB arbitrer */
> - ppc4xx_plb_init(env);
> + object_property_set_link(OBJECT(&s->plb), "cpu", OBJECT(&s->cpu),
> + &error_abort);
> + if (!qdev_realize(DEVICE(&s->plb), NULL, errp)) {
> + return;
> + }
>
> /* PLB to OPB bridge */
> object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu),
> @@ -1617,6 +1641,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_PLB,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(Ppc405PlbState),
> + .class_init = ppc405_plb_class_init,
> + }, {
> .name = TYPE_PPC405_POB,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(Ppc405PobState),
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 15/19] ppc/ppc405: QOM'ify PLB
2022-08-03 9:43 ` Daniel Henrique Barboza
@ 2022-08-03 11:06 ` BALATON Zoltan
0 siblings, 0 replies; 50+ messages in thread
From: BALATON Zoltan @ 2022-08-03 11:06 UTC (permalink / raw)
To: Daniel Henrique Barboza; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1038 bytes --]
On Wed, 3 Aug 2022, Daniel Henrique Barboza wrote:
> On 8/1/22 10:10, Cédric Le Goater wrote:
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h | 14 ++++++++++
>> hw/ppc/ppc405_uc.c | 67 +++++++++++++++++++++++++++++++++-------------
>> 2 files changed, 62 insertions(+), 19 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index d39d65cc86e4..4ff5cdcf5c65 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t {
>> typedef struct Ppc405SoCState Ppc405SoCState;
>> +/* Peripheral local bus arbitrer */
>
> I wasn't aware that arbitrer is a word. Google says that 'arbitrer' is an
> old form of 'arbitrator'.
>
> I looked it up because I thought you misspelled 'arbiter', which is the name
> of a Protoss combat unit in Starcraft. And it happens to be a synonym of
> 'arbitrator' as well.
>
> 'arbitrer' is fine, don't worry about it.
I think that's what the chip docs call it so it comes from there.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 16/19] ppc/ppc405: QOM'ify MAL
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (14 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 15/19] ppc/ppc405: QOM'ify PLB Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:45 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 17/19] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
` (2 subsequent siblings)
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 1 +
include/hw/ppc/ppc4xx.h | 28 ++++++++++
hw/ppc/ppc405_uc.c | 20 +++++--
hw/ppc/ppc4xx_devs.c | 120 +++++++++++++++++++++++++---------------
4 files changed, 118 insertions(+), 51 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4ff5cdcf5c65..0cbfd977aecf 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -259,6 +259,7 @@ struct Ppc405SoCState {
Ppc405OpbaState opba;
Ppc405PobState pob;
Ppc405PlbState plb;
+ Ppc4xxMalState mal;
};
/* PowerPC 405 core */
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 980f964b5a91..a383560576d7 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -26,6 +26,7 @@
#define PPC4XX_H
#include "hw/ppc/ppc.h"
+#include "hw/sysbus.h"
#include "exec/memory.h"
/* PowerPC 4xx core initialization */
@@ -44,6 +45,33 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
hwaddr *ram_sizes,
int do_init);
+/* Memory Access Layer (MAL) */
+#define TYPE_PPC4xx_MAL "ppc4xx-mal"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
+struct Ppc4xxMalState {
+ SysBusDevice parent_obj;
+
+ PowerPCCPU *cpu;
+
+ qemu_irq irqs[4];
+ uint32_t cfg;
+ uint32_t esr;
+ uint32_t ier;
+ uint32_t txcasr;
+ uint32_t txcarr;
+ uint32_t txeobisr;
+ uint32_t txdeir;
+ uint32_t rxcasr;
+ uint32_t rxcarr;
+ uint32_t rxeobisr;
+ uint32_t rxdeir;
+ uint32_t *txctpr;
+ uint32_t *rxctpr;
+ uint32_t *rcbs;
+ uint8_t txcnum;
+ uint8_t rxcnum;
+};
+
void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
qemu_irq irqs[4]);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 45bcf3a6dd8a..de2c3c0c747c 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1466,12 +1466,13 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
+
+ object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq mal_irqs[4];
CPUPPCState *env;
Error *err = NULL;
int i;
@@ -1612,11 +1613,18 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* MAL */
- mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
- mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
- mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
- mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
- ppc4xx_mal_init(env, 4, 2, mal_irqs);
+ object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
+ object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
+ object_property_set_link(OBJECT(&s->mal), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->mal), errp)) {
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
+ qdev_get_gpio_in(s->uic, 11 + i));
+ }
/* Ethernet */
/* Uses UIC IRQs 9, 15, 17 */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 737c0896b4f8..c935a7acf6a0 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -491,32 +491,10 @@ enum {
MAL0_RCBS1 = 0x1E1,
};
-typedef struct ppc4xx_mal_t ppc4xx_mal_t;
-struct ppc4xx_mal_t {
- qemu_irq irqs[4];
- uint32_t cfg;
- uint32_t esr;
- uint32_t ier;
- uint32_t txcasr;
- uint32_t txcarr;
- uint32_t txeobisr;
- uint32_t txdeir;
- uint32_t rxcasr;
- uint32_t rxcarr;
- uint32_t rxeobisr;
- uint32_t rxdeir;
- uint32_t *txctpr;
- uint32_t *rxctpr;
- uint32_t *rcbs;
- uint8_t txcnum;
- uint8_t rxcnum;
-};
-
-static void ppc4xx_mal_reset(void *opaque)
+static void ppc4xx_mal_reset(DeviceState *dev)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
- mal = opaque;
mal->cfg = 0x0007C000;
mal->esr = 0x00000000;
mal->ier = 0x00000000;
@@ -530,10 +508,9 @@ static void ppc4xx_mal_reset(void *opaque)
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
uint32_t ret;
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
ret = mal->cfg;
@@ -587,13 +564,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x80000000) {
- ppc4xx_mal_reset(mal);
+ ppc4xx_mal_reset(DEVICE(mal));
}
mal->cfg = val & 0x00FFC087;
break;
@@ -644,23 +620,30 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
}
}
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4])
+static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ CPUPPCState *env;
int i;
- assert(txcnum <= 32 && rxcnum <= 32);
- mal = g_malloc0(sizeof(*mal));
- mal->txcnum = txcnum;
- mal->rxcnum = rxcnum;
- mal->txctpr = g_new0(uint32_t, txcnum);
- mal->rxctpr = g_new0(uint32_t, rxcnum);
- mal->rcbs = g_new0(uint32_t, rxcnum);
- for (i = 0; i < 4; i++) {
- mal->irqs[i] = irqs[i];
+ assert(mal->cpu);
+
+ env = &mal->cpu->env;
+
+ if (mal->txcnum > 32 || mal->rxcnum > 32) {
+ error_setg(errp, "invalid TXC/RXC number");
+ return;
}
- qemu_register_reset(&ppc4xx_mal_reset, mal);
+
+ mal->txctpr = g_new0(uint32_t, mal->txcnum);
+ mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
+ mal->rcbs = g_new0(uint32_t, mal->rxcnum);
+
+ for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
+ sysbus_init_irq(sbd, &mal->irqs[i]);
+ }
+
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
@@ -683,16 +666,63 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
- for (i = 0; i < txcnum; i++) {
+ for (i = 0; i < mal->txcnum; i++) {
ppc_dcr_register(env, MAL0_TXCTP0R + i,
mal, &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
+ for (i = 0; i < mal->rxcnum; i++) {
ppc_dcr_register(env, MAL0_RXCTP0R + i,
mal, &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
+ for (i = 0; i < mal->rxcnum; i++) {
ppc_dcr_register(env, MAL0_RCBS0 + i,
mal, &dcr_read_mal, &dcr_write_mal);
}
}
+
+static Property ppc4xx_mal_properties[] = {
+ DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
+ DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
+ DEFINE_PROP_LINK("cpu", Ppc4xxMalState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_mal_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc4xx_mal_reset;
+ device_class_set_props(dc, ppc4xx_mal_properties);
+}
+
+void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
+ qemu_irq irqs[4])
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ DeviceState *dev = qdev_new(TYPE_PPC4xx_MAL);
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
+ int i;
+
+ qdev_prop_set_uint32(dev, "txc-num", txcnum);
+ qdev_prop_set_uint32(dev, "rxc-num", rxcnum);
+ object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
+
+ for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irqs[i]);
+ }
+}
+
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_MAL,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc4xxMalState),
+ .class_init = ppc4xx_mal_class_init,
+ }
+};
+
+DEFINE_TYPES(ppc4xx_types)
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 16/19] ppc/ppc405: QOM'ify MAL
2022-08-01 13:10 ` [PATCH 16/19] ppc/ppc405: QOM'ify MAL Cédric Le Goater
@ 2022-08-03 9:45 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:45 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 1 +
> include/hw/ppc/ppc4xx.h | 28 ++++++++++
> hw/ppc/ppc405_uc.c | 20 +++++--
> hw/ppc/ppc4xx_devs.c | 120 +++++++++++++++++++++++++---------------
> 4 files changed, 118 insertions(+), 51 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 4ff5cdcf5c65..0cbfd977aecf 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -259,6 +259,7 @@ struct Ppc405SoCState {
> Ppc405OpbaState opba;
> Ppc405PobState pob;
> Ppc405PlbState plb;
> + Ppc4xxMalState mal;
> };
>
> /* PowerPC 405 core */
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 980f964b5a91..a383560576d7 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -26,6 +26,7 @@
> #define PPC4XX_H
>
> #include "hw/ppc/ppc.h"
> +#include "hw/sysbus.h"
> #include "exec/memory.h"
>
> /* PowerPC 4xx core initialization */
> @@ -44,6 +45,33 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
> hwaddr *ram_sizes,
> int do_init);
>
> +/* Memory Access Layer (MAL) */
> +#define TYPE_PPC4xx_MAL "ppc4xx-mal"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
> +struct Ppc4xxMalState {
> + SysBusDevice parent_obj;
> +
> + PowerPCCPU *cpu;
> +
> + qemu_irq irqs[4];
> + uint32_t cfg;
> + uint32_t esr;
> + uint32_t ier;
> + uint32_t txcasr;
> + uint32_t txcarr;
> + uint32_t txeobisr;
> + uint32_t txdeir;
> + uint32_t rxcasr;
> + uint32_t rxcarr;
> + uint32_t rxeobisr;
> + uint32_t rxdeir;
> + uint32_t *txctpr;
> + uint32_t *rxctpr;
> + uint32_t *rcbs;
> + uint8_t txcnum;
> + uint8_t rxcnum;
> +};
> +
> void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> qemu_irq irqs[4]);
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 45bcf3a6dd8a..de2c3c0c747c 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1466,12 +1466,13 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
>
> object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
> +
> + object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - qemu_irq mal_irqs[4];
> CPUPPCState *env;
> Error *err = NULL;
> int i;
> @@ -1612,11 +1613,18 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* MAL */
> - mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
> - mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
> - mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
> - mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
> - ppc4xx_mal_init(env, 4, 2, mal_irqs);
> + object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
> + object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
> + object_property_set_link(OBJECT(&s->mal), "cpu", OBJECT(&s->cpu),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->mal), errp)) {
> + return;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
> + qdev_get_gpio_in(s->uic, 11 + i));
> + }
>
> /* Ethernet */
> /* Uses UIC IRQs 9, 15, 17 */
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 737c0896b4f8..c935a7acf6a0 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -491,32 +491,10 @@ enum {
> MAL0_RCBS1 = 0x1E1,
> };
>
> -typedef struct ppc4xx_mal_t ppc4xx_mal_t;
> -struct ppc4xx_mal_t {
> - qemu_irq irqs[4];
> - uint32_t cfg;
> - uint32_t esr;
> - uint32_t ier;
> - uint32_t txcasr;
> - uint32_t txcarr;
> - uint32_t txeobisr;
> - uint32_t txdeir;
> - uint32_t rxcasr;
> - uint32_t rxcarr;
> - uint32_t rxeobisr;
> - uint32_t rxdeir;
> - uint32_t *txctpr;
> - uint32_t *rxctpr;
> - uint32_t *rcbs;
> - uint8_t txcnum;
> - uint8_t rxcnum;
> -};
> -
> -static void ppc4xx_mal_reset(void *opaque)
> +static void ppc4xx_mal_reset(DeviceState *dev)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(dev);
>
> - mal = opaque;
> mal->cfg = 0x0007C000;
> mal->esr = 0x00000000;
> mal->ier = 0x00000000;
> @@ -530,10 +508,9 @@ static void ppc4xx_mal_reset(void *opaque)
>
> static uint32_t dcr_read_mal(void *opaque, int dcrn)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
> uint32_t ret;
>
> - mal = opaque;
> switch (dcrn) {
> case MAL0_CFG:
> ret = mal->cfg;
> @@ -587,13 +564,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
>
> static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
>
> - mal = opaque;
> switch (dcrn) {
> case MAL0_CFG:
> if (val & 0x80000000) {
> - ppc4xx_mal_reset(mal);
> + ppc4xx_mal_reset(DEVICE(mal));
> }
> mal->cfg = val & 0x00FFC087;
> break;
> @@ -644,23 +620,30 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> - qemu_irq irqs[4])
> +static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> + CPUPPCState *env;
> int i;
>
> - assert(txcnum <= 32 && rxcnum <= 32);
> - mal = g_malloc0(sizeof(*mal));
> - mal->txcnum = txcnum;
> - mal->rxcnum = rxcnum;
> - mal->txctpr = g_new0(uint32_t, txcnum);
> - mal->rxctpr = g_new0(uint32_t, rxcnum);
> - mal->rcbs = g_new0(uint32_t, rxcnum);
> - for (i = 0; i < 4; i++) {
> - mal->irqs[i] = irqs[i];
> + assert(mal->cpu);
> +
> + env = &mal->cpu->env;
> +
> + if (mal->txcnum > 32 || mal->rxcnum > 32) {
> + error_setg(errp, "invalid TXC/RXC number");
> + return;
> }
> - qemu_register_reset(&ppc4xx_mal_reset, mal);
> +
> + mal->txctpr = g_new0(uint32_t, mal->txcnum);
> + mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
> + mal->rcbs = g_new0(uint32_t, mal->rxcnum);
> +
> + for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
> + sysbus_init_irq(sbd, &mal->irqs[i]);
> + }
> +
> ppc_dcr_register(env, MAL0_CFG,
> mal, &dcr_read_mal, &dcr_write_mal);
> ppc_dcr_register(env, MAL0_ESR,
> @@ -683,16 +666,63 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> mal, &dcr_read_mal, &dcr_write_mal);
> ppc_dcr_register(env, MAL0_RXDEIR,
> mal, &dcr_read_mal, &dcr_write_mal);
> - for (i = 0; i < txcnum; i++) {
> + for (i = 0; i < mal->txcnum; i++) {
> ppc_dcr_register(env, MAL0_TXCTP0R + i,
> mal, &dcr_read_mal, &dcr_write_mal);
> }
> - for (i = 0; i < rxcnum; i++) {
> + for (i = 0; i < mal->rxcnum; i++) {
> ppc_dcr_register(env, MAL0_RXCTP0R + i,
> mal, &dcr_read_mal, &dcr_write_mal);
> }
> - for (i = 0; i < rxcnum; i++) {
> + for (i = 0; i < mal->rxcnum; i++) {
> ppc_dcr_register(env, MAL0_RCBS0 + i,
> mal, &dcr_read_mal, &dcr_write_mal);
> }
> }
> +
> +static Property ppc4xx_mal_properties[] = {
> + DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
> + DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
> + DEFINE_PROP_LINK("cpu", Ppc4xxMalState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc4xx_mal_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc4xx_mal_reset;
> + device_class_set_props(dc, ppc4xx_mal_properties);
> +}
> +
> +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> + qemu_irq irqs[4])
> +{
> + PowerPCCPU *cpu = env_archcpu(env);
> + DeviceState *dev = qdev_new(TYPE_PPC4xx_MAL);
> + Ppc4xxMalState *mal = PPC4xx_MAL(dev);
> + int i;
> +
> + qdev_prop_set_uint32(dev, "txc-num", txcnum);
> + qdev_prop_set_uint32(dev, "rxc-num", rxcnum);
> + object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort);
> + qdev_realize_and_unref(dev, NULL, &error_fatal);
> +
> + for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irqs[i]);
> + }
> +}
> +
> +static const TypeInfo ppc4xx_types[] = {
> + {
> + .name = TYPE_PPC4xx_MAL,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc4xxMalState),
> + .class_init = ppc4xx_mal_class_init,
> + }
> +};
> +
> +DEFINE_TYPES(ppc4xx_types)
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 17/19] ppc/ppc405: QOM'ify FPGA
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (15 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 16/19] ppc/ppc405: QOM'ify MAL Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:45 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 18/19] ppc/ppc405: QOM'ify UIC Cédric Le Goater
2022-08-01 13:10 ` [PATCH 19/19] ppc/ppc405: QOM'ify I2C Cédric Le Goater
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 55 +++++++++++++++++++++++++++++-------------
1 file changed, 38 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 82b51cc457fa..2900c267b7ac 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -71,18 +71,23 @@ OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
* - NVRAM (0xF0000000)
* - FPGA (0xF0300000)
*/
-typedef struct ref405ep_fpga_t ref405ep_fpga_t;
-struct ref405ep_fpga_t {
+
+#define TYPE_PPC405_FPGA "ppc405-fpga"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA);
+struct Ppc405FpgaState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
uint8_t reg0;
uint8_t reg1;
};
static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
- ref405ep_fpga_t *fpga;
+ Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
uint32_t ret;
- fpga = opaque;
switch (addr) {
case 0x0:
ret = fpga->reg0;
@@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ref405ep_fpga_t *fpga;
+ Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
- fpga = opaque;
switch (addr) {
case 0x0:
/* Read only */
@@ -126,27 +130,39 @@ static const MemoryRegionOps ref405ep_fpga_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ref405ep_fpga_reset (void *opaque)
+static void ref405ep_fpga_reset(DeviceState *dev)
{
- ref405ep_fpga_t *fpga;
+ Ppc405FpgaState *fpga = PPC405_FPGA(dev);
- fpga = opaque;
fpga->reg0 = 0x00;
fpga->reg1 = 0x0F;
}
-static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
+static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
{
- ref405ep_fpga_t *fpga;
- MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
+ Ppc405FpgaState *s = PPC405_FPGA(dev);
- fpga = g_new0(ref405ep_fpga_t, 1);
- memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
+ memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
"fpga", 0x00000100);
- memory_region_add_subregion(sysmem, base, fpga_memory);
- qemu_register_reset(&ref405ep_fpga_reset, fpga);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ref405ep_fpga_realize;
+ dc->user_creatable = false;
+ dc->reset = ref405ep_fpga_reset;
}
+static const TypeInfo ref405ep_fpga_type = {
+ .name = TYPE_PPC405_FPGA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405FpgaState),
+ .class_init = ref405ep_fpga_class_init,
+};
+
/*
* CPU reset handler when booting directly from a loaded kernel
*/
@@ -325,7 +341,11 @@ static void ref405ep_init(MachineState *machine)
ppc405_init(machine);
/* Register FPGA */
- ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
+ dev = qdev_new(TYPE_PPC405_FPGA);
+ object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
+
/* Register NVRAM */
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
@@ -370,6 +390,7 @@ static void ppc405_machine_init(void)
{
type_register_static(&ppc405_machine_type);
type_register_static(&ref405ep_type);
+ type_register_static(&ref405ep_fpga_type);
}
type_init(ppc405_machine_init)
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 17/19] ppc/ppc405: QOM'ify FPGA
2022-08-01 13:10 ` [PATCH 17/19] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
@ 2022-08-03 9:45 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:45 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405_boards.c | 55 +++++++++++++++++++++++++++++-------------
> 1 file changed, 38 insertions(+), 17 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 82b51cc457fa..2900c267b7ac 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -71,18 +71,23 @@ OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
> * - NVRAM (0xF0000000)
> * - FPGA (0xF0300000)
> */
> -typedef struct ref405ep_fpga_t ref405ep_fpga_t;
> -struct ref405ep_fpga_t {
> +
> +#define TYPE_PPC405_FPGA "ppc405-fpga"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA);
> +struct Ppc405FpgaState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +
> uint8_t reg0;
> uint8_t reg1;
> };
>
> static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> {
> - ref405ep_fpga_t *fpga;
> + Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
> uint32_t ret;
>
> - fpga = opaque;
> switch (addr) {
> case 0x0:
> ret = fpga->reg0;
> @@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
> unsigned size)
> {
> - ref405ep_fpga_t *fpga;
> + Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
>
> - fpga = opaque;
> switch (addr) {
> case 0x0:
> /* Read only */
> @@ -126,27 +130,39 @@ static const MemoryRegionOps ref405ep_fpga_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> -static void ref405ep_fpga_reset (void *opaque)
> +static void ref405ep_fpga_reset(DeviceState *dev)
> {
> - ref405ep_fpga_t *fpga;
> + Ppc405FpgaState *fpga = PPC405_FPGA(dev);
>
> - fpga = opaque;
> fpga->reg0 = 0x00;
> fpga->reg1 = 0x0F;
> }
>
> -static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
> +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
> {
> - ref405ep_fpga_t *fpga;
> - MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
> + Ppc405FpgaState *s = PPC405_FPGA(dev);
>
> - fpga = g_new0(ref405ep_fpga_t, 1);
> - memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
> + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
> "fpga", 0x00000100);
> - memory_region_add_subregion(sysmem, base, fpga_memory);
> - qemu_register_reset(&ref405ep_fpga_reset, fpga);
> + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
> +}
> +
> +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ref405ep_fpga_realize;
> + dc->user_creatable = false;
> + dc->reset = ref405ep_fpga_reset;
> }
>
> +static const TypeInfo ref405ep_fpga_type = {
> + .name = TYPE_PPC405_FPGA,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405FpgaState),
> + .class_init = ref405ep_fpga_class_init,
> +};
> +
> /*
> * CPU reset handler when booting directly from a loaded kernel
> */
> @@ -325,7 +341,11 @@ static void ref405ep_init(MachineState *machine)
> ppc405_init(machine);
>
> /* Register FPGA */
> - ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
> + dev = qdev_new(TYPE_PPC405_FPGA);
> + object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
> +
> /* Register NVRAM */
> dev = qdev_new("sysbus-m48t08");
> qdev_prop_set_int32(dev, "base-year", 1968);
> @@ -370,6 +390,7 @@ static void ppc405_machine_init(void)
> {
> type_register_static(&ppc405_machine_type);
> type_register_static(&ref405ep_type);
> + type_register_static(&ref405ep_fpga_type);
> }
>
> type_init(ppc405_machine_init)
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 18/19] ppc/ppc405: QOM'ify UIC
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (16 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 17/19] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-01 13:17 ` Cédric Le Goater
2022-08-03 9:46 ` Daniel Henrique Barboza
2022-08-01 13:10 ` [PATCH 19/19] ppc/ppc405: QOM'ify I2C Cédric Le Goater
18 siblings, 2 replies; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 3 ++-
hw/ppc/ppc405_uc.c | 27 ++++++++++++++-------------
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 0cbfd977aecf..c2cfccb9d106 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
+#include "hw/intc/ppc-uic.h"
#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000
@@ -249,7 +250,7 @@ struct Ppc405SoCState {
hwaddr ram_size;
PowerPCCPU cpu;
- DeviceState *uic;
+ PPCUIC uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index de2c3c0c747c..0336d1e08689 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1448,6 +1448,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpu", &s->cpu,
POWERPC_CPU_TYPE_NAME("405ep"));
+ object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
+
object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
@@ -1533,22 +1535,21 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
/* Universal interrupt controller */
- s->uic = qdev_new(TYPE_PPC_UIC);
-
- object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
+ object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
&error_fatal);
- if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->uic), errp)) {
return;
}
- sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
- sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_CINT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 2, s->ram_memories,
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 2,
+ s->ram_memories,
s->ram_bases, s->ram_sizes, s->do_dram_init);
/* External bus controller */
@@ -1567,12 +1568,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
- qdev_get_gpio_in(s->uic, 5 + i));
+ qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
}
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(s->uic, 2));
+ qdev_get_gpio_in(DEVICE(&s->uic), 2));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
@@ -1583,13 +1584,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Serial ports */
if (serial_hd(0) != NULL) {
serial_mm_init(get_system_memory(), 0xef600300, 0,
- qdev_get_gpio_in(s->uic, 0),
+ qdev_get_gpio_in(DEVICE(&s->uic), 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
serial_mm_init(get_system_memory(), 0xef600400, 0,
- qdev_get_gpio_in(s->uic, 1),
+ qdev_get_gpio_in(DEVICE(&s->uic), 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
@@ -1609,7 +1610,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
- qdev_get_gpio_in(s->uic, 19 + i));
+ qdev_get_gpio_in(&s->uic, 19 + i));
}
/* MAL */
@@ -1623,7 +1624,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
- qdev_get_gpio_in(s->uic, 11 + i));
+ qdev_get_gpio_in(&s->uic, 11 + i));
}
/* Ethernet */
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 18/19] ppc/ppc405: QOM'ify UIC
2022-08-01 13:10 ` [PATCH 18/19] ppc/ppc405: QOM'ify UIC Cédric Le Goater
@ 2022-08-01 13:17 ` Cédric Le Goater
2022-08-03 9:46 ` Daniel Henrique Barboza
1 sibling, 0 replies; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:17 UTC (permalink / raw)
To: qemu-ppc; +Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan
Daniel,
On 8/1/22 15:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 3 ++-
> hw/ppc/ppc405_uc.c | 27 ++++++++++++++-------------
> 2 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 0cbfd977aecf..c2cfccb9d106 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -27,6 +27,7 @@
>
> #include "qom/object.h"
> #include "hw/ppc/ppc4xx.h"
> +#include "hw/intc/ppc-uic.h"
>
> #define PPC405EP_SDRAM_BASE 0x00000000
> #define PPC405EP_NVRAM_BASE 0xF0000000
> @@ -249,7 +250,7 @@ struct Ppc405SoCState {
> hwaddr ram_size;
>
> PowerPCCPU cpu;
> - DeviceState *uic;
> + PPCUIC uic;
> Ppc405CpcState cpc;
> Ppc405GptState gpt;
> Ppc405OcmState ocm;
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index de2c3c0c747c..0336d1e08689 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1448,6 +1448,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "cpu", &s->cpu,
> POWERPC_CPU_TYPE_NAME("405ep"));
>
> + object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
> +
> object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
> object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
>
> @@ -1533,22 +1535,21 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
>
> /* Universal interrupt controller */
> - s->uic = qdev_new(TYPE_PPC_UIC);
> -
> - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
> + object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
> &error_fatal);
> - if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uic), errp)) {
> return;
> }
>
> - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
> - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_CINT,
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> /* XXX 405EP has no ECC interrupt */
> - ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 2, s->ram_memories,
> + ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 2,
> + s->ram_memories,
> s->ram_bases, s->ram_sizes, s->do_dram_init);
>
> /* External bus controller */
> @@ -1567,12 +1568,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> - qdev_get_gpio_in(s->uic, 5 + i));
> + qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
> }
>
> /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> - qdev_get_gpio_in(s->uic, 2));
> + qdev_get_gpio_in(DEVICE(&s->uic), 2));
>
> /* GPIO */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> @@ -1583,13 +1584,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* Serial ports */
> if (serial_hd(0) != NULL) {
> serial_mm_init(get_system_memory(), 0xef600300, 0,
> - qdev_get_gpio_in(s->uic, 0),
> + qdev_get_gpio_in(DEVICE(&s->uic), 0),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
> DEVICE_BIG_ENDIAN);
> }
> if (serial_hd(1) != NULL) {
> serial_mm_init(get_system_memory(), 0xef600400, 0,
> - qdev_get_gpio_in(s->uic, 1),
> + qdev_get_gpio_in(DEVICE(&s->uic), 1),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
> DEVICE_BIG_ENDIAN);
> }
> @@ -1609,7 +1610,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
> - qdev_get_gpio_in(s->uic, 19 + i));
> + qdev_get_gpio_in(&s->uic, 19 + i));
> }
>
> /* MAL */
> @@ -1623,7 +1624,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
> - qdev_get_gpio_in(s->uic, 11 + i));
> + qdev_get_gpio_in(&s->uic, 11 + i));
> }
>
> /* Ethernet */
There is a compile bug in this patch. If you consider applying the patchset,
please fold in the following changes. Sorry about that.
Thanks,
C.
@@ -1616,7 +1616,7 @@ static void ppc405_soc_realize(DeviceSta
for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
- qdev_get_gpio_in(&s->uic, 19 + i));
+ qdev_get_gpio_in(DEVICE(&s->uic), 19 + i));
}
/* MAL */
@@ -1630,7 +1630,7 @@ static void ppc405_soc_realize(DeviceSta
for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
- qdev_get_gpio_in(&s->uic, 11 + i));
+ qdev_get_gpio_in(DEVICE(&s->uic), 11 + i));
}
/* Ethernet */
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 18/19] ppc/ppc405: QOM'ify UIC
2022-08-01 13:10 ` [PATCH 18/19] ppc/ppc405: QOM'ify UIC Cédric Le Goater
2022-08-01 13:17 ` Cédric Le Goater
@ 2022-08-03 9:46 ` Daniel Henrique Barboza
1 sibling, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:46 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
With the compile fix that you mentioned fixed up:
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 3 ++-
> hw/ppc/ppc405_uc.c | 27 ++++++++++++++-------------
> 2 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 0cbfd977aecf..c2cfccb9d106 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -27,6 +27,7 @@
>
> #include "qom/object.h"
> #include "hw/ppc/ppc4xx.h"
> +#include "hw/intc/ppc-uic.h"
>
> #define PPC405EP_SDRAM_BASE 0x00000000
> #define PPC405EP_NVRAM_BASE 0xF0000000
> @@ -249,7 +250,7 @@ struct Ppc405SoCState {
> hwaddr ram_size;
>
> PowerPCCPU cpu;
> - DeviceState *uic;
> + PPCUIC uic;
> Ppc405CpcState cpc;
> Ppc405GptState gpt;
> Ppc405OcmState ocm;
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index de2c3c0c747c..0336d1e08689 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1448,6 +1448,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "cpu", &s->cpu,
> POWERPC_CPU_TYPE_NAME("405ep"));
>
> + object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
> +
> object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
> object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
>
> @@ -1533,22 +1535,21 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
>
> /* Universal interrupt controller */
> - s->uic = qdev_new(TYPE_PPC_UIC);
> -
> - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
> + object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
> &error_fatal);
> - if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uic), errp)) {
> return;
> }
>
> - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
> - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_CINT,
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> /* XXX 405EP has no ECC interrupt */
> - ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 2, s->ram_memories,
> + ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 2,
> + s->ram_memories,
> s->ram_bases, s->ram_sizes, s->do_dram_init);
>
> /* External bus controller */
> @@ -1567,12 +1568,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> - qdev_get_gpio_in(s->uic, 5 + i));
> + qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
> }
>
> /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> - qdev_get_gpio_in(s->uic, 2));
> + qdev_get_gpio_in(DEVICE(&s->uic), 2));
>
> /* GPIO */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> @@ -1583,13 +1584,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* Serial ports */
> if (serial_hd(0) != NULL) {
> serial_mm_init(get_system_memory(), 0xef600300, 0,
> - qdev_get_gpio_in(s->uic, 0),
> + qdev_get_gpio_in(DEVICE(&s->uic), 0),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
> DEVICE_BIG_ENDIAN);
> }
> if (serial_hd(1) != NULL) {
> serial_mm_init(get_system_memory(), 0xef600400, 0,
> - qdev_get_gpio_in(s->uic, 1),
> + qdev_get_gpio_in(DEVICE(&s->uic), 1),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
> DEVICE_BIG_ENDIAN);
> }
> @@ -1609,7 +1610,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
> - qdev_get_gpio_in(s->uic, 19 + i));
> + qdev_get_gpio_in(&s->uic, 19 + i));
> }
>
> /* MAL */
> @@ -1623,7 +1624,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
> - qdev_get_gpio_in(s->uic, 11 + i));
> + qdev_get_gpio_in(&s->uic, 11 + i));
> }
>
> /* Ethernet */
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 19/19] ppc/ppc405: QOM'ify I2C
2022-08-01 13:10 [PATCH 00/19] ppc: QOM'ify 405 board Cédric Le Goater
` (17 preceding siblings ...)
2022-08-01 13:10 ` [PATCH 18/19] ppc/ppc405: QOM'ify UIC Cédric Le Goater
@ 2022-08-01 13:10 ` Cédric Le Goater
2022-08-03 9:46 ` Daniel Henrique Barboza
18 siblings, 1 reply; 50+ messages in thread
From: Cédric Le Goater @ 2022-08-01 13:10 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Cédric Le Goater
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 2 ++
hw/ppc/ppc405_uc.c | 10 ++++++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c2cfccb9d106..0b1e15c18fe0 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -28,6 +28,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/intc/ppc-uic.h"
+#include "hw/i2c/ppc4xx_i2c.h"
#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000
@@ -256,6 +257,7 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+ PPC4xxI2CState i2c;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 0336d1e08689..5372c308c227 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1461,6 +1461,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
+ object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C);
+
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
@@ -1572,8 +1574,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* I2C controller */
- sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(DEVICE(&s->uic), 2));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, 0xef600500);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
+ qdev_get_gpio_in(DEVICE(&s->uic), 2));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
--
2.37.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 19/19] ppc/ppc405: QOM'ify I2C
2022-08-01 13:10 ` [PATCH 19/19] ppc/ppc405: QOM'ify I2C Cédric Le Goater
@ 2022-08-03 9:46 ` Daniel Henrique Barboza
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Henrique Barboza @ 2022-08-03 9:46 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc; +Cc: qemu-devel, BALATON Zoltan
On 8/1/22 10:10, Cédric Le Goater wrote:
> Having an explicit I2C model object will help if one day we want to
> add I2C devices on the bus.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/ppc/ppc405.h | 2 ++
> hw/ppc/ppc405_uc.c | 10 ++++++++--
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index c2cfccb9d106..0b1e15c18fe0 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -28,6 +28,7 @@
> #include "qom/object.h"
> #include "hw/ppc/ppc4xx.h"
> #include "hw/intc/ppc-uic.h"
> +#include "hw/i2c/ppc4xx_i2c.h"
>
> #define PPC405EP_SDRAM_BASE 0x00000000
> #define PPC405EP_NVRAM_BASE 0xF0000000
> @@ -256,6 +257,7 @@ struct Ppc405SoCState {
> Ppc405OcmState ocm;
> Ppc405GpioState gpio;
> Ppc405DmaState dma;
> + PPC4xxI2CState i2c;
> Ppc405EbcState ebc;
> Ppc405OpbaState opba;
> Ppc405PobState pob;
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 0336d1e08689..5372c308c227 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1461,6 +1461,8 @@ static void ppc405_soc_instance_init(Object *obj)
>
> object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
>
> + object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C);
> +
> object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
>
> object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
> @@ -1572,8 +1574,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* I2C controller */
> - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> - qdev_get_gpio_in(DEVICE(&s->uic), 2));
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, 0xef600500);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
> + qdev_get_gpio_in(DEVICE(&s->uic), 2));
>
> /* GPIO */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
^ permalink raw reply [flat|nested] 50+ messages in thread