[PULL 0/1] riscv-to-apply queue

[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 0e0c2cf6de0bc6538840837c63b25817cd417347:

  Merge tag 'pull-target-arm-20220801' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-08-01 12:00:08 -0700)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220802

for you to fetch changes up to 1eaa63429a9944265c92efdb94c02fabb231f564:

  linux-user/riscv: Align signal frame to 16 bytes (2022-08-02 08:56:49 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for QEMU 7.1

This is a second PR to go in for RC1. It fixes a bug we have had
for awhile, but it's a simple fix so let's pull it in for RC1.

* linux-user/riscv: Align signal frame to 16 bytes

----------------------------------------------------------------
Richard Henderson (1):
      linux-user/riscv: Align signal frame to 16 bytes

 linux-user/riscv/signal.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

[PULL 1/1] linux-user/riscv: Align signal frame to 16 bytes

[Alistair Francis]

From: Richard Henderson <richard.henderson@linaro.org>

Follow the kernel's alignment, as we already noted.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1093
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220729201942.30738-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 linux-user/riscv/signal.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index 296e39fbf0..eaa168199a 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -64,9 +64,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
 
     /* This is the X/Open sanctioned signal stack switching.  */
     sp = target_sigsp(sp, ka) - framesize;
-
-    /* XXX: kernel aligns with 0xf ? */
-    sp &= ~3UL; /* align sp on 4-byte boundary */
+    sp &= ~0xf;
 
     return sp;
 }
-- 
2.37.1

Re: [PULL 0/1] riscv-to-apply queue

[Richard Henderson]

On 8/1/22 16:02, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit 0e0c2cf6de0bc6538840837c63b25817cd417347:
> 
>    Merge tag 'pull-target-arm-20220801' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-08-01 12:00:08 -0700)
> 
> are available in the Git repository at:
> 
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220802
> 
> for you to fetch changes up to 1eaa63429a9944265c92efdb94c02fabb231f564:
> 
>    linux-user/riscv: Align signal frame to 16 bytes (2022-08-02 08:56:49 +1000)
> 
> ----------------------------------------------------------------
> Seventh RISC-V PR for QEMU 7.1
> 
> This is a second PR to go in for RC1. It fixes a bug we have had
> for awhile, but it's a simple fix so let's pull it in for RC1.
> 
> * linux-user/riscv: Align signal frame to 16 bytes

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~


> 
> ----------------------------------------------------------------
> Richard Henderson (1):
>        linux-user/riscv: Align signal frame to 16 bytes
> 
>   linux-user/riscv/signal.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
> 

[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

The following changes since commit d1181d29370a4318a9f11ea92065bea6bb159f83:

  Merge tag 'pull-nbd-2023-07-19' of https://repo.or.cz/qemu/ericb into staging (2023-07-20 09:54:07 +0100)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230723-3

for you to fetch changes up to dcaaf2bf9bfd2c664dbeff0069fcab3d75c924d3:

  roms/opensbi: Upgrade from v1.3 to v1.3.1 (2023-07-23 19:32:02 +1000)

----------------------------------------------------------------
Fifth RISC-V PR for 8.1

* roms/opensbi: Upgrade from v1.3 to v1.3.1

----------------------------------------------------------------
Bin Meng (1):
      roms/opensbi: Upgrade from v1.3 to v1.3.1

 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 135344 -> 135376 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 138304 -> 138368 bytes
 roms/opensbi                                   |   2 +-
 3 files changed, 1 insertion(+), 1 deletion(-)

Re: [PULL 0/1] riscv-to-apply queue

[Peter Maydell]

On Sun, 23 Jul 2023 at 10:35, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit d1181d29370a4318a9f11ea92065bea6bb159f83:
>
>   Merge tag 'pull-nbd-2023-07-19' of https://repo.or.cz/qemu/ericb into staging (2023-07-20 09:54:07 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230723-3
>
> for you to fetch changes up to dcaaf2bf9bfd2c664dbeff0069fcab3d75c924d3:
>
>   roms/opensbi: Upgrade from v1.3 to v1.3.1 (2023-07-23 19:32:02 +1000)
>
> ----------------------------------------------------------------
> Fifth RISC-V PR for 8.1
>
> * roms/opensbi: Upgrade from v1.3 to v1.3.1
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.1
for any user-visible changes.

-- PMM

[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

The following changes since commit 2eefd4fcec4b8fe41ceee2a8f00cdec1fe81b75c:

  Merge tag 'pull-maintainer-9.1-rc3-160824-1' of https://gitlab.com/stsquad/qemu into staging (2024-08-17 16:46:45 +1000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240819-1

for you to fetch changes up to 6df664f87c738788891f3bda701e63e23a0dbbc2:

  Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" (2024-08-19 14:34:49 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

This reverts a commit adding `#msi-cells=<0>` to the virt machine
as that commit results in PCI devices unable to us MSIs. Even though
it's a kernel bug, we don't want to break existing users.

* Revert adding #msi-cells to virt machine

----------------------------------------------------------------
Andrew Jones (1):
      Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'"

 hw/riscv/virt.c | 1 -
 1 file changed, 1 deletion(-)

Re: [PULL 0/1] riscv-to-apply queue

[Richard Henderson]

On 8/19/24 14:43, Alistair Francis wrote:
> The following changes since commit 2eefd4fcec4b8fe41ceee2a8f00cdec1fe81b75c:
> 
>    Merge tag 'pull-maintainer-9.1-rc3-160824-1' ofhttps://gitlab.com/stsquad/qemu into staging (2024-08-17 16:46:45 +1000)
> 
> are available in the Git repository at:
> 
>    https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240819-1
> 
> for you to fetch changes up to 6df664f87c738788891f3bda701e63e23a0dbbc2:
> 
>    Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" (2024-08-19 14:34:49 +1000)
> 
> ----------------------------------------------------------------
> RISC-V PR for 9.1
> 
> This reverts a commit adding `#msi-cells=<0>` to the virt machine
> as that commit results in PCI devices unable to us MSIs. Even though
> it's a kernel bug, we don't want to break existing users.
> 
> * Revert adding #msi-cells to virt machine

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate.

r~

[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

The following changes since commit 53f3a13ac1069975ad47cf8bd05cc96b4ac09962:

  Merge tag 'pull-tcg-20250403' of https://gitlab.com/rth7680/qemu into staging (2025-04-04 10:23:17 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250407-1

for you to fetch changes up to d31d37fded414959713678d2e9e6bc1afab5f376:

  docs: deprecate RISC-V default machine option (2025-04-07 10:12:40 +1000)

----------------------------------------------------------------
Sixth RISC-V PR for 10.0

* Deprecate the default RISC-V machine

----------------------------------------------------------------
Daniel Henrique Barboza (1):
      docs: deprecate RISC-V default machine option

 docs/about/deprecated.rst | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Re: [PULL 0/1] riscv-to-apply queue

[Stefan Hajnoczi]

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Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.

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