* [PATCH v3 01/22] ppc/ppc405: Remove taihu machine
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
` (21 subsequent siblings)
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
It has been deprecated since 7.0.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/about/deprecated.rst | 9 --
docs/about/removed-features.rst | 6 +
docs/system/ppc/embedded.rst | 1 -
hw/ppc/ppc405_boards.c | 232 --------------------------------
MAINTAINERS | 2 +-
5 files changed, 7 insertions(+), 243 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 7ee26626d5cf..2f9b41aaea48 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -233,15 +233,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
better reflects the way this property affects all random data within
the device tree blob, not just the ``kaslr-seed`` node.
-PPC 405 ``taihu`` machine (since 7.0)
-'''''''''''''''''''''''''''''''''''''
-
-The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
-except for some external periphery. However, the periphery of the ``taihu``
-machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
-been implemented), so there is not much value added by this board. Use the
-``ref405ep`` machine instead.
-
``pc-i440fx-1.4`` up to ``pc-i440fx-1.7`` (since 7.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''''
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index 925e22016f98..a4aa3dca6987 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -668,6 +668,12 @@ Aspeed ``swift-bmc`` machine (removed in 7.0)
This machine was removed because it was unused. Alternative AST2500 based
OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
+ppc ``taihu`` machine (removed in 7.2)
+'''''''''''''''''''''''''''''''''''''''''''''
+
+This machine was removed because it was partially emulated and 405
+machines are very similar. Use the ``ref405ep`` machine instead.
+
linux-user mode CPUs
--------------------
diff --git a/docs/system/ppc/embedded.rst b/docs/system/ppc/embedded.rst
index cfffbda24da9..af3b3d9fa460 100644
--- a/docs/system/ppc/embedded.rst
+++ b/docs/system/ppc/embedded.rst
@@ -6,5 +6,4 @@ Embedded family boards
- ``ppce500`` generic paravirt e500 platform
- ``ref405ep`` ref405ep
- ``sam460ex`` aCube Sam460ex
-- ``taihu`` taihu
- ``virtex-ml507`` Xilinx Virtex ML507 reference design
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index a66ad05e3ac3..1a4e7588c584 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -342,241 +342,9 @@ static const TypeInfo ref405ep_type = {
.class_init = ref405ep_class_init,
};
-/*****************************************************************************/
-/* AMCC Taihu evaluation board */
-/* - PowerPC 405EP processor
- * - SDRAM 128 MB at 0x00000000
- * - Boot flash 2 MB at 0xFFE00000
- * - Application flash 32 MB at 0xFC000000
- * - 2 serial ports
- * - 2 ethernet PHY
- * - 1 USB 1.1 device 0x50000000
- * - 1 LCD display 0x50100000
- * - 1 CPLD 0x50100000
- * - 1 I2C EEPROM
- * - 1 I2C thermal sensor
- * - a set of LEDs
- * - bit-bang SPI port using GPIOs
- * - 1 EBC interface connector 0 0x50200000
- * - 1 cardbus controller + expansion slot.
- * - 1 PCI expansion slot.
- */
-typedef struct taihu_cpld_t taihu_cpld_t;
-struct taihu_cpld_t {
- uint8_t reg0;
- uint8_t reg1;
-};
-
-static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
-{
- taihu_cpld_t *cpld;
- uint32_t ret;
-
- cpld = opaque;
- switch (addr) {
- case 0x0:
- ret = cpld->reg0;
- break;
- case 0x1:
- ret = cpld->reg1;
- break;
- default:
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void taihu_cpld_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
-{
- taihu_cpld_t *cpld;
-
- cpld = opaque;
- switch (addr) {
- case 0x0:
- /* Read only */
- break;
- case 0x1:
- cpld->reg1 = value;
- break;
- default:
- break;
- }
-}
-
-static const MemoryRegionOps taihu_cpld_ops = {
- .read = taihu_cpld_read,
- .write = taihu_cpld_write,
- .impl = {
- .min_access_size = 1,
- .max_access_size = 1,
- },
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static void taihu_cpld_reset (void *opaque)
-{
- taihu_cpld_t *cpld;
-
- cpld = opaque;
- cpld->reg0 = 0x01;
- cpld->reg1 = 0x80;
-}
-
-static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
-{
- taihu_cpld_t *cpld;
- MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
-
- cpld = g_new0(taihu_cpld_t, 1);
- memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
- memory_region_add_subregion(sysmem, base, cpld_memory);
- qemu_register_reset(&taihu_cpld_reset, cpld);
-}
-
-static void taihu_405ep_init(MachineState *machine)
-{
- MachineClass *mc = MACHINE_GET_CLASS(machine);
- const char *bios_name = machine->firmware ?: BIOS_FILENAME;
- const char *kernel_filename = machine->kernel_filename;
- const char *initrd_filename = machine->initrd_filename;
- char *filename;
- MemoryRegion *sysmem = get_system_memory();
- MemoryRegion *bios;
- MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
- hwaddr ram_bases[2], ram_sizes[2];
- long bios_size;
- target_ulong kernel_base, initrd_base;
- long kernel_size, initrd_size;
- int linux_boot;
- int fl_idx;
- DriveInfo *dinfo;
- DeviceState *uicdev;
-
- if (machine->ram_size != mc->default_ram_size) {
- char *sz = size_to_str(mc->default_ram_size);
- error_report("Invalid RAM size, should be %s", sz);
- g_free(sz);
- exit(EXIT_FAILURE);
- }
-
- ram_bases[0] = 0;
- ram_sizes[0] = 0x04000000;
- memory_region_init_alias(&ram_memories[0], NULL,
- "taihu_405ep.ram-0", machine->ram, ram_bases[0],
- ram_sizes[0]);
- ram_bases[1] = 0x04000000;
- ram_sizes[1] = 0x04000000;
- memory_region_init_alias(&ram_memories[1], NULL,
- "taihu_405ep.ram-1", machine->ram, ram_bases[1],
- ram_sizes[1]);
- ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
- 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
- /* allocate and load BIOS */
- fl_idx = 0;
-#if defined(USE_FLASH_BIOS)
- dinfo = drive_get(IF_PFLASH, 0, fl_idx);
- if (dinfo) {
- bios_size = 2 * MiB;
- pflash_cfi02_register(0xFFE00000,
- "taihu_405ep.bios", bios_size,
- blk_by_legacy_dinfo(dinfo),
- 64 * KiB, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
- fl_idx++;
- } else
-#endif
- {
- bios = g_new(MemoryRegion, 1);
- memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
- &error_fatal);
- filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- if (filename) {
- bios_size = load_image_size(filename,
- memory_region_get_ram_ptr(bios),
- BIOS_SIZE);
- g_free(filename);
- if (bios_size < 0) {
- error_report("Could not load PowerPC BIOS '%s'", bios_name);
- exit(1);
- }
- bios_size = (bios_size + 0xfff) & ~0xfff;
- memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
- } else if (!qtest_enabled()) {
- error_report("Could not load PowerPC BIOS '%s'", bios_name);
- exit(1);
- }
- }
- /* Register Linux flash */
- dinfo = drive_get(IF_PFLASH, 0, fl_idx);
- if (dinfo) {
- bios_size = 32 * MiB;
- pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
- blk_by_legacy_dinfo(dinfo),
- 64 * KiB, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
- fl_idx++;
- }
- /* Register CLPD & LCD display */
- taihu_cpld_init(sysmem, 0x50100000);
- /* Load kernel */
- linux_boot = (kernel_filename != NULL);
- if (linux_boot) {
- kernel_base = KERNEL_LOAD_ADDR;
- /* now we can load the kernel */
- kernel_size = load_image_targphys(kernel_filename, kernel_base,
- machine->ram_size - kernel_base);
- if (kernel_size < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
- /* load initrd */
- if (initrd_filename) {
- initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image_targphys(initrd_filename, initrd_base,
- machine->ram_size - initrd_base);
- if (initrd_size < 0) {
- error_report("could not load initial ram disk '%s'",
- initrd_filename);
- exit(1);
- }
- } else {
- initrd_base = 0;
- initrd_size = 0;
- }
- } else {
- kernel_base = 0;
- kernel_size = 0;
- initrd_base = 0;
- initrd_size = 0;
- }
-}
-
-static void taihu_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "taihu";
- mc->init = taihu_405ep_init;
- mc->default_ram_size = 0x08000000;
- mc->default_ram_id = "taihu_405ep.ram";
- mc->deprecation_reason = "incomplete, use 'ref405ep' instead";
-}
-
-static const TypeInfo taihu_type = {
- .name = MACHINE_TYPE_NAME("taihu"),
- .parent = TYPE_MACHINE,
- .class_init = taihu_class_init,
-};
-
static void ppc405_machine_init(void)
{
type_register_static(&ref405ep_type);
- type_register_static(&taihu_type);
}
type_init(ppc405_machine_init)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ce4227ff650..1729c0901cea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1282,7 +1282,7 @@ F: hw/openrisc/openrisc_sim.c
PowerPC Machines
----------------
-405 (ref405ep and taihu)
+405 (ref405ep)
L: qemu-ppc@nongnu.org
S: Orphan
F: hw/ppc/ppc405_boards.c
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 01/22] ppc/ppc405: Remove taihu machine Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 12:23 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
` (20 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
We will use this machine as a base to define the ref405ep and possibly
the PPC405 hotfoot board as found in the Linux kernel.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1a4e7588c584..96700be74d08 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -50,6 +50,15 @@
#define USE_FLASH_BIOS
+#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
+
+struct Ppc405MachineState {
+ /* Private */
+ MachineState parent_obj;
+ /* Public */
+};
+
/*****************************************************************************/
/* PPC405EP reference board (IBM) */
/* Standalone board with:
@@ -332,18 +341,34 @@ static void ref405ep_class_init(ObjectClass *oc, void *data)
mc->desc = "ref405ep";
mc->init = ref405ep_init;
- mc->default_ram_size = 0x08000000;
- mc->default_ram_id = "ef405ep.ram";
}
static const TypeInfo ref405ep_type = {
.name = MACHINE_TYPE_NAME("ref405ep"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_PPC405_MACHINE,
.class_init = ref405ep_class_init,
};
+static void ppc405_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "PPC405 generic machine";
+ mc->default_ram_size = 128 * MiB;
+ mc->default_ram_id = "ppc405.ram";
+}
+
+static const TypeInfo ppc405_machine_type = {
+ .name = TYPE_PPC405_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(Ppc405MachineState),
+ .class_init = ppc405_machine_class_init,
+ .abstract = true,
+};
+
static void ppc405_machine_init(void)
{
+ type_register_static(&ppc405_machine_type);
type_register_static(&ref405ep_type);
}
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine
2022-08-08 10:27 ` [PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
@ 2022-08-08 12:23 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 12:23 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 2109 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> We will use this machine as a base to define the ref405ep and possibly
> the PPC405 hotfoot board as found in the Linux kernel.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc405_boards.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 1a4e7588c584..96700be74d08 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -50,6 +50,15 @@
>
> #define USE_FLASH_BIOS
>
> +#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
> +
> +struct Ppc405MachineState {
> + /* Private */
> + MachineState parent_obj;
> + /* Public */
> +};
> +
> /*****************************************************************************/
> /* PPC405EP reference board (IBM) */
> /* Standalone board with:
> @@ -332,18 +341,34 @@ static void ref405ep_class_init(ObjectClass *oc, void *data)
>
> mc->desc = "ref405ep";
> mc->init = ref405ep_init;
> - mc->default_ram_size = 0x08000000;
> - mc->default_ram_id = "ef405ep.ram";
> }
>
> static const TypeInfo ref405ep_type = {
> .name = MACHINE_TYPE_NAME("ref405ep"),
> - .parent = TYPE_MACHINE,
> + .parent = TYPE_PPC405_MACHINE,
> .class_init = ref405ep_class_init,
> };
>
> +static void ppc405_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> + mc->desc = "PPC405 generic machine";
> + mc->default_ram_size = 128 * MiB;
> + mc->default_ram_id = "ppc405.ram";
> +}
> +
> +static const TypeInfo ppc405_machine_type = {
> + .name = TYPE_PPC405_MACHINE,
> + .parent = TYPE_MACHINE,
> + .instance_size = sizeof(Ppc405MachineState),
> + .class_init = ppc405_machine_class_init,
> + .abstract = true,
> +};
> +
> static void ppc405_machine_init(void)
> {
> + type_register_static(&ppc405_machine_type);
> type_register_static(&ref405ep_type);
> }
>
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 01/22] ppc/ppc405: Remove taihu machine Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 12:23 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 04/22] ppc/ppc405: Move SRAM " Cédric Le Goater
` (19 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 31 +++++++++++++++++++------------
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 96700be74d08..f4794ba40ce6 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -230,13 +230,11 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
env->load_info = &boot_info;
}
-static void ref405ep_init(MachineState *machine)
+static void ppc405_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
- DeviceState *dev;
- SysBusDevice *s;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
@@ -294,15 +292,6 @@ static void ref405ep_init(MachineState *machine)
memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
}
- /* Register FPGA */
- ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
- /* Register NVRAM */
- dev = qdev_new("sysbus-m48t08");
- qdev_prop_set_int32(dev, "base-year", 1968);
- s = SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
-
/* Load kernel and initrd using U-Boot images */
if (kernel_filename && machine->firmware) {
target_ulong kernel_base, initrd_base;
@@ -335,6 +324,23 @@ static void ref405ep_init(MachineState *machine)
}
}
+static void ref405ep_init(MachineState *machine)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+
+ ppc405_init(machine);
+
+ /* Register FPGA */
+ ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
+ /* Register NVRAM */
+ dev = qdev_new("sysbus-m48t08");
+ qdev_prop_set_int32(dev, "base-year", 1968);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
+}
+
static void ref405ep_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -354,6 +360,7 @@ static void ppc405_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "PPC405 generic machine";
+ mc->init = ppc405_init;
mc->default_ram_size = 128 * MiB;
mc->default_ram_id = "ppc405.ram";
}
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine
2022-08-08 10:27 ` [PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
@ 2022-08-08 12:23 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 12:23 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 2720 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc405_boards.c | 31 +++++++++++++++++++------------
> 1 file changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 96700be74d08..f4794ba40ce6 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -230,13 +230,11 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
> env->load_info = &boot_info;
> }
>
> -static void ref405ep_init(MachineState *machine)
> +static void ppc405_init(MachineState *machine)
> {
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> PowerPCCPU *cpu;
> - DeviceState *dev;
> - SysBusDevice *s;
> MemoryRegion *sram = g_new(MemoryRegion, 1);
> MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
> hwaddr ram_bases[2], ram_sizes[2];
> @@ -294,15 +292,6 @@ static void ref405ep_init(MachineState *machine)
> memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
> }
>
> - /* Register FPGA */
> - ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
> - /* Register NVRAM */
> - dev = qdev_new("sysbus-m48t08");
> - qdev_prop_set_int32(dev, "base-year", 1968);
> - s = SYS_BUS_DEVICE(dev);
> - sysbus_realize_and_unref(s, &error_fatal);
> - sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
> -
> /* Load kernel and initrd using U-Boot images */
> if (kernel_filename && machine->firmware) {
> target_ulong kernel_base, initrd_base;
> @@ -335,6 +324,23 @@ static void ref405ep_init(MachineState *machine)
> }
> }
>
> +static void ref405ep_init(MachineState *machine)
> +{
> + DeviceState *dev;
> + SysBusDevice *s;
> +
> + ppc405_init(machine);
> +
> + /* Register FPGA */
> + ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
> + /* Register NVRAM */
> + dev = qdev_new("sysbus-m48t08");
> + qdev_prop_set_int32(dev, "base-year", 1968);
> + s = SYS_BUS_DEVICE(dev);
> + sysbus_realize_and_unref(s, &error_fatal);
> + sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
> +}
> +
> static void ref405ep_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -354,6 +360,7 @@ static void ppc405_machine_class_init(ObjectClass *oc, void *data)
> MachineClass *mc = MACHINE_CLASS(oc);
>
> mc->desc = "PPC405 generic machine";
> + mc->init = ppc405_init;
> mc->default_ram_size = 128 * MiB;
> mc->default_ram_id = "ppc405.ram";
> }
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 04/22] ppc/ppc405: Move SRAM under the ref405ep machine
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (2 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 12:25 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
` (18 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
It doesn't belong to the generic machine nor the SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index f4794ba40ce6..c6fa559b03d9 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -235,7 +235,6 @@ static void ppc405_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
- MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
MemoryRegion *sysmem = get_system_memory();
@@ -260,11 +259,6 @@ static void ppc405_init(MachineState *machine)
cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
- /* allocate SRAM */
- memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
- &error_fatal);
- memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
@@ -328,9 +322,16 @@ static void ref405ep_init(MachineState *machine)
{
DeviceState *dev;
SysBusDevice *s;
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
+ MemoryRegion *sysmem = get_system_memory();
ppc405_init(machine);
+ /* allocate SRAM */
+ memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
+ &error_fatal);
+ memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
+
/* Register FPGA */
ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
/* Register NVRAM */
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 04/22] ppc/ppc405: Move SRAM under the ref405ep machine
2022-08-08 10:27 ` [PATCH v3 04/22] ppc/ppc405: Move SRAM " Cédric Le Goater
@ 2022-08-08 12:25 ` BALATON Zoltan
2022-08-08 13:38 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 12:25 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 2147 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> It doesn't belong to the generic machine nor the SoC.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405_boards.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index f4794ba40ce6..c6fa559b03d9 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -235,7 +235,6 @@ static void ppc405_init(MachineState *machine)
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> PowerPCCPU *cpu;
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
> hwaddr ram_bases[2], ram_sizes[2];
> MemoryRegion *sysmem = get_system_memory();
> @@ -260,11 +259,6 @@ static void ppc405_init(MachineState *machine)
> cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
> 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>
> - /* allocate SRAM */
> - memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
> - &error_fatal);
> - memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
> -
> /* allocate and load BIOS */
> if (machine->firmware) {
> MemoryRegion *bios = g_new(MemoryRegion, 1);
> @@ -328,9 +322,16 @@ static void ref405ep_init(MachineState *machine)
> {
> DeviceState *dev;
> SysBusDevice *s;
> + MemoryRegion *sram = g_new(MemoryRegion, 1);
> + MemoryRegion *sysmem = get_system_memory();
You could drop thi "system" local and just use get_system_memory() in
add_subregion
> ppc405_init(machine);
>
> + /* allocate SRAM */
> + memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
> + &error_fatal);
> + memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
> +
> /* Register FPGA */
> ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
or use it everywhere consistently.
Regards,
BALATON Zoltan
> /* Register NVRAM */
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 04/22] ppc/ppc405: Move SRAM under the ref405ep machine
2022-08-08 12:25 ` BALATON Zoltan
@ 2022-08-08 13:38 ` Cédric Le Goater
0 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 13:38 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 14:25, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> It doesn't belong to the generic machine nor the SoC.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405_boards.c | 13 +++++++------
>> 1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index f4794ba40ce6..c6fa559b03d9 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -235,7 +235,6 @@ static void ppc405_init(MachineState *machine)
>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>> const char *kernel_filename = machine->kernel_filename;
>> PowerPCCPU *cpu;
>> - MemoryRegion *sram = g_new(MemoryRegion, 1);
>> MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
>> hwaddr ram_bases[2], ram_sizes[2];
>> MemoryRegion *sysmem = get_system_memory();
>> @@ -260,11 +259,6 @@ static void ppc405_init(MachineState *machine)
>> cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
>> 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>>
>> - /* allocate SRAM */
>> - memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
>> - &error_fatal);
>> - memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
>> -
>> /* allocate and load BIOS */
>> if (machine->firmware) {
>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>> @@ -328,9 +322,16 @@ static void ref405ep_init(MachineState *machine)
>> {
>> DeviceState *dev;
>> SysBusDevice *s;
>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>> + MemoryRegion *sysmem = get_system_memory();
>
> You could drop thi "system" local and just use get_system_memory() in add_subregion
Yes. Let's drop it.
Thanks,
C.
>
>> ppc405_init(machine);
>>
>> + /* allocate SRAM */
>> + memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
>> + &error_fatal);
>> + memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
>> +
>> /* Register FPGA */
>> ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
>
> or use it everywhere consistently.
>
> Regards,
> BALATON Zoltan
>
>> /* Register NVRAM */
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (3 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 04/22] ppc/ppc405: Move SRAM " Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 12:43 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
` (17 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
It is an initial model to start QOMification of the PPC405 board.
QOM'ified devices will be reintroduced one by one. Start with the
memory regions, which name prefix is changed to "ppc405".
Also, initialize only one RAM bank. The second bank is a dummy one
(zero size) which is here to match the hard coded number of banks in
ppc405ep_init().
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 16 ++++++++++++++++
hw/ppc/ppc405_boards.c | 23 ++++++++++++-----------
hw/ppc/ppc405_uc.c | 40 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 68 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 83f156f585c8..66dc21cdfed8 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -25,6 +25,7 @@
#ifndef PPC405_H
#define PPC405_H
+#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#define PPC405EP_SDRAM_BASE 0x00000000
@@ -62,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_SOC "ppc405-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
+
+struct Ppc405SoCState {
+ /* Private */
+ DeviceState parent_obj;
+
+ /* Public */
+ MemoryRegion ram_banks[2];
+ hwaddr ram_bases[2], ram_sizes[2];
+
+ MemoryRegion *dram_mr;
+ hwaddr ram_size;
+};
+
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index c6fa559b03d9..1dc5065fcc1d 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -57,6 +57,8 @@ struct Ppc405MachineState {
/* Private */
MachineState parent_obj;
/* Public */
+
+ Ppc405SoCState soc;
};
/*****************************************************************************/
@@ -232,11 +234,10 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
+ Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
- MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
- hwaddr ram_bases[2], ram_sizes[2];
MemoryRegion *sysmem = get_system_memory();
DeviceState *uicdev;
@@ -247,16 +248,16 @@ static void ppc405_init(MachineState *machine)
exit(EXIT_FAILURE);
}
- /* XXX: fix this */
- memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
- machine->ram, 0, machine->ram_size);
- ram_bases[0] = 0;
- ram_sizes[0] = machine->ram_size;
- memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
- ram_bases[1] = 0x00000000;
- ram_sizes[1] = 0x00000000;
+ object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
+ TYPE_PPC405_SOC);
+ object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
+ machine->ram_size, &error_fatal);
+ object_property_set_link(OBJECT(&ppc405->soc), "dram",
+ OBJECT(machine->ram), &error_abort);
+ qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
- cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
+ cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
+ ppc405->soc.ram_sizes,
33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d6420c88d3a6..adadb3a0ae08 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -30,6 +30,7 @@
#include "hw/ppc/ppc.h"
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "ppc405.h"
#include "hw/char/serial.h"
#include "qemu/timer.h"
@@ -1530,3 +1531,42 @@ PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
return cpu;
}
+
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405SoCState *s = PPC405_SOC(dev);
+
+ /* Initialize only one bank */
+ s->ram_bases[0] = 0;
+ s->ram_sizes[0] = s->ram_size;
+ memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
+ "ppc405.sdram0", s->dram_mr,
+ s->ram_bases[0], s->ram_sizes[0]);
+}
+
+static Property ppc405_soc_properties[] = {
+ DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_soc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_soc_realize;
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc405_soc_properties);
+}
+
+static const TypeInfo ppc405_types[] = {
+ {
+ .name = TYPE_PPC405_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405SoCState),
+ .class_init = ppc405_soc_class_init,
+ }
+};
+
+DEFINE_TYPES(ppc405_types)
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC
2022-08-08 10:27 ` [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
@ 2022-08-08 12:43 ` BALATON Zoltan
2022-08-08 13:51 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 12:43 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 6181 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> It is an initial model to start QOMification of the PPC405 board.
> QOM'ified devices will be reintroduced one by one. Start with the
> memory regions, which name prefix is changed to "ppc405".
>
> Also, initialize only one RAM bank. The second bank is a dummy one
> (zero size) which is here to match the hard coded number of banks in
> ppc405ep_init().
>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 16 ++++++++++++++++
> hw/ppc/ppc405_boards.c | 23 ++++++++++++-----------
> hw/ppc/ppc405_uc.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 68 insertions(+), 11 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 83f156f585c8..66dc21cdfed8 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -25,6 +25,7 @@
> #ifndef PPC405_H
> #define PPC405_H
>
> +#include "qom/object.h"
> #include "hw/ppc/ppc4xx.h"
>
> #define PPC405EP_SDRAM_BASE 0x00000000
> @@ -62,6 +63,21 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> +#define TYPE_PPC405_SOC "ppc405-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
> +
> +struct Ppc405SoCState {
> + /* Private */
> + DeviceState parent_obj;
> +
> + /* Public */
> + MemoryRegion ram_banks[2];
> + hwaddr ram_bases[2], ram_sizes[2];
> +
> + MemoryRegion *dram_mr;
> + hwaddr ram_size;
> +};
> +
> /* PowerPC 405 core */
> ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index c6fa559b03d9..1dc5065fcc1d 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -57,6 +57,8 @@ struct Ppc405MachineState {
> /* Private */
> MachineState parent_obj;
> /* Public */
> +
> + Ppc405SoCState soc;
> };
>
> /*****************************************************************************/
> @@ -232,11 +234,10 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
>
> static void ppc405_init(MachineState *machine)
> {
> + Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> PowerPCCPU *cpu;
> - MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
> - hwaddr ram_bases[2], ram_sizes[2];
> MemoryRegion *sysmem = get_system_memory();
> DeviceState *uicdev;
>
> @@ -247,16 +248,16 @@ static void ppc405_init(MachineState *machine)
> exit(EXIT_FAILURE);
> }
>
> - /* XXX: fix this */
> - memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
> - machine->ram, 0, machine->ram_size);
> - ram_bases[0] = 0;
> - ram_sizes[0] = machine->ram_size;
> - memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
> - ram_bases[1] = 0x00000000;
> - ram_sizes[1] = 0x00000000;
> + object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
> + TYPE_PPC405_SOC);
> + object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
> + machine->ram_size, &error_fatal);
> + object_property_set_link(OBJECT(&ppc405->soc), "dram",
> + OBJECT(machine->ram), &error_abort);
> + qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>
> - cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
> + cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
> + ppc405->soc.ram_sizes,
> 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>
> /* allocate and load BIOS */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index d6420c88d3a6..adadb3a0ae08 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -30,6 +30,7 @@
> #include "hw/ppc/ppc.h"
> #include "hw/i2c/ppc4xx_i2c.h"
> #include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> #include "ppc405.h"
> #include "hw/char/serial.h"
> #include "qemu/timer.h"
> @@ -1530,3 +1531,42 @@ PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>
> return cpu;
> }
> +
> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> +{
> + Ppc405SoCState *s = PPC405_SOC(dev);
> +
> + /* Initialize only one bank */
> + s->ram_bases[0] = 0;
> + s->ram_sizes[0] = s->ram_size;
> + memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
> + "ppc405.sdram0", s->dram_mr,
> + s->ram_bases[0], s->ram_sizes[0]);
> +}
> +
> +static Property ppc405_soc_properties[] = {
> + DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> + MemoryRegion *),
> + DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
I'm not sure why we need to duplicate these in the soc if they are always
the same as machine->ram and machine->ram_size. Is it theoretically
possible to have a soc where it uses ram that's not the whole ram? If not
then you could just uose machine which is accessible either as
current_machine or qdev_get_machine() (also the parent of out soc but we
don't know how to get that). If setting ram this way is still desired do
we separately need to set its size or we could use memory_region_size()
instead?
> +
> +static void ppc405_soc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_soc_realize;
> + dc->user_creatable = false;
May need a comment explaining why user_creatable = false. (Also for all
other similar lines in other patches, I won't repeat this there.)
Regards,
BALATON Zoltan
> + device_class_set_props(dc, ppc405_soc_properties);
> +}
> +
> +static const TypeInfo ppc405_types[] = {
> + {
> + .name = TYPE_PPC405_SOC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(Ppc405SoCState),
> + .class_init = ppc405_soc_class_init,
> + }
> +};
> +
> +DEFINE_TYPES(ppc405_types)
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC
2022-08-08 12:43 ` BALATON Zoltan
@ 2022-08-08 13:51 ` Cédric Le Goater
2022-08-08 14:02 ` BALATON Zoltan
0 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 13:51 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 14:43, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> It is an initial model to start QOMification of the PPC405 board.
>> QOM'ified devices will be reintroduced one by one. Start with the
>> memory regions, which name prefix is changed to "ppc405".
>>
>> Also, initialize only one RAM bank. The second bank is a dummy one
>> (zero size) which is here to match the hard coded number of banks in
>> ppc405ep_init().
>>
>> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h | 16 ++++++++++++++++
>> hw/ppc/ppc405_boards.c | 23 ++++++++++++-----------
>> hw/ppc/ppc405_uc.c | 40 ++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 68 insertions(+), 11 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index 83f156f585c8..66dc21cdfed8 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -25,6 +25,7 @@
>> #ifndef PPC405_H
>> #define PPC405_H
>>
>> +#include "qom/object.h"
>> #include "hw/ppc/ppc4xx.h"
>>
>> #define PPC405EP_SDRAM_BASE 0x00000000
>> @@ -62,6 +63,21 @@ struct ppc4xx_bd_info_t {
>> uint32_t bi_iic_fast[2];
>> };
>>
>> +#define TYPE_PPC405_SOC "ppc405-soc"
>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
>> +
>> +struct Ppc405SoCState {
>> + /* Private */
>> + DeviceState parent_obj;
>> +
>> + /* Public */
>> + MemoryRegion ram_banks[2];
>> + hwaddr ram_bases[2], ram_sizes[2];
>> +
>> + MemoryRegion *dram_mr;
>> + hwaddr ram_size;
>> +};
>> +
>> /* PowerPC 405 core */
>> ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>>
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index c6fa559b03d9..1dc5065fcc1d 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -57,6 +57,8 @@ struct Ppc405MachineState {
>> /* Private */
>> MachineState parent_obj;
>> /* Public */
>> +
>> + Ppc405SoCState soc;
>> };
>>
>> /*****************************************************************************/
>> @@ -232,11 +234,10 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
>>
>> static void ppc405_init(MachineState *machine)
>> {
>> + Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>> const char *kernel_filename = machine->kernel_filename;
>> PowerPCCPU *cpu;
>> - MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
>> - hwaddr ram_bases[2], ram_sizes[2];
>> MemoryRegion *sysmem = get_system_memory();
>> DeviceState *uicdev;
>>
>> @@ -247,16 +248,16 @@ static void ppc405_init(MachineState *machine)
>> exit(EXIT_FAILURE);
>> }
>>
>> - /* XXX: fix this */
>> - memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
>> - machine->ram, 0, machine->ram_size);
>> - ram_bases[0] = 0;
>> - ram_sizes[0] = machine->ram_size;
>> - memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
>> - ram_bases[1] = 0x00000000;
>> - ram_sizes[1] = 0x00000000;
>> + object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
>> + TYPE_PPC405_SOC);
>> + object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
>> + machine->ram_size, &error_fatal);
>> + object_property_set_link(OBJECT(&ppc405->soc), "dram",
>> + OBJECT(machine->ram), &error_abort);
>> + qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>>
>> - cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
>> + cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
>> + ppc405->soc.ram_sizes,
>> 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>>
>> /* allocate and load BIOS */
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index d6420c88d3a6..adadb3a0ae08 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -30,6 +30,7 @@
>> #include "hw/ppc/ppc.h"
>> #include "hw/i2c/ppc4xx_i2c.h"
>> #include "hw/irq.h"
>> +#include "hw/qdev-properties.h"
>> #include "ppc405.h"
>> #include "hw/char/serial.h"
>> #include "qemu/timer.h"
>> @@ -1530,3 +1531,42 @@ PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>>
>> return cpu;
>> }
>> +
>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> +{
>> + Ppc405SoCState *s = PPC405_SOC(dev);
>> +
>> + /* Initialize only one bank */
>> + s->ram_bases[0] = 0;
>> + s->ram_sizes[0] = s->ram_size;
>> + memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
>> + "ppc405.sdram0", s->dram_mr,
>> + s->ram_bases[0], s->ram_sizes[0]);
>> +}
>> +
>> +static Property ppc405_soc_properties[] = {
>> + DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>> + MemoryRegion *),
>> + DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>
> I'm not sure why we need to duplicate these in the soc if they are always the same as machine->ram and machine->ram_size.
There are machines with multi SoCs. PowerNV can have 16.
But that's not the reason here, we pass the dram memory region to the SoC
for controllers that might need it for memory transactions, typically DMAs.
In this case, it's the SDRAM controller which creates slices of RAM for
each available RAM bank.
> Is it theoretically possible to have a soc where it uses ram that's not the whole ram?
Yes.
> If not then you could just uose machine which is accessible either as current_machine
> or qdev_get_machine()
These are QEMU globals. We should avoid using them in device models.
> (also the parent of out soc but we don't know how to get that). If setting ram this way
> is still desired do we separately need to set its size or we could use memory_region_size()
> instead?
Let's keep SDRAM modeling for the next patchset.
>> +
>> +static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + dc->realize = ppc405_soc_realize;
>> + dc->user_creatable = false;
>
> May need a comment explaining why user_creatable = false. (Also for all other similar lines in other patches, I won't repeat this there.)
TYPE_PPC405_SOC devices can not be created from the QEMU command line.
it doesn't make sense. That's what 'dc->user_creatable = false' means.
Thanks,
C.
>
> Regards,
> BALATON Zoltan
>
>> + device_class_set_props(dc, ppc405_soc_properties);
>> +}
>> +
>> +static const TypeInfo ppc405_types[] = {
>> + {
>> + .name = TYPE_PPC405_SOC,
>> + .parent = TYPE_DEVICE,
>> + .instance_size = sizeof(Ppc405SoCState),
>> + .class_init = ppc405_soc_class_init,
>> + }
>> +};
>> +
>> +DEFINE_TYPES(ppc405_types)
>>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC
2022-08-08 13:51 ` Cédric Le Goater
@ 2022-08-08 14:02 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:02 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 7929 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> On 8/8/22 14:43, BALATON Zoltan wrote:
>> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>>> It is an initial model to start QOMification of the PPC405 board.
>>> QOM'ified devices will be reintroduced one by one. Start with the
>>> memory regions, which name prefix is changed to "ppc405".
>>>
>>> Also, initialize only one RAM bank. The second bank is a dummy one
>>> (zero size) which is here to match the hard coded number of banks in
>>> ppc405ep_init().
>>>
>>> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>> hw/ppc/ppc405.h | 16 ++++++++++++++++
>>> hw/ppc/ppc405_boards.c | 23 ++++++++++++-----------
>>> hw/ppc/ppc405_uc.c | 40 ++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 68 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>> index 83f156f585c8..66dc21cdfed8 100644
>>> --- a/hw/ppc/ppc405.h
>>> +++ b/hw/ppc/ppc405.h
>>> @@ -25,6 +25,7 @@
>>> #ifndef PPC405_H
>>> #define PPC405_H
>>>
>>> +#include "qom/object.h"
>>> #include "hw/ppc/ppc4xx.h"
>>>
>>> #define PPC405EP_SDRAM_BASE 0x00000000
>>> @@ -62,6 +63,21 @@ struct ppc4xx_bd_info_t {
>>> uint32_t bi_iic_fast[2];
>>> };
>>>
>>> +#define TYPE_PPC405_SOC "ppc405-soc"
>>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
>>> +
>>> +struct Ppc405SoCState {
>>> + /* Private */
>>> + DeviceState parent_obj;
>>> +
>>> + /* Public */
>>> + MemoryRegion ram_banks[2];
>>> + hwaddr ram_bases[2], ram_sizes[2];
>>> +
>>> + MemoryRegion *dram_mr;
>>> + hwaddr ram_size;
>>> +};
>>> +
>>> /* PowerPC 405 core */
>>> ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>>>
>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>> index c6fa559b03d9..1dc5065fcc1d 100644
>>> --- a/hw/ppc/ppc405_boards.c
>>> +++ b/hw/ppc/ppc405_boards.c
>>> @@ -57,6 +57,8 @@ struct Ppc405MachineState {
>>> /* Private */
>>> MachineState parent_obj;
>>> /* Public */
>>> +
>>> + Ppc405SoCState soc;
>>> };
>>>
>>> /*****************************************************************************/
>>> @@ -232,11 +234,10 @@ static void boot_from_kernel(MachineState *machine,
>>> PowerPCCPU *cpu)
>>>
>>> static void ppc405_init(MachineState *machine)
>>> {
>>> + Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>> const char *kernel_filename = machine->kernel_filename;
>>> PowerPCCPU *cpu;
>>> - MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
>>> - hwaddr ram_bases[2], ram_sizes[2];
>>> MemoryRegion *sysmem = get_system_memory();
>>> DeviceState *uicdev;
>>>
>>> @@ -247,16 +248,16 @@ static void ppc405_init(MachineState *machine)
>>> exit(EXIT_FAILURE);
>>> }
>>>
>>> - /* XXX: fix this */
>>> - memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
>>> - machine->ram, 0, machine->ram_size);
>>> - ram_bases[0] = 0;
>>> - ram_sizes[0] = machine->ram_size;
>>> - memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
>>> - ram_bases[1] = 0x00000000;
>>> - ram_sizes[1] = 0x00000000;
>>> + object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
>>> + TYPE_PPC405_SOC);
>>> + object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
>>> + machine->ram_size, &error_fatal);
>>> + object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>> + OBJECT(machine->ram), &error_abort);
>>> + qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>>>
>>> - cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
>>> + cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks,
>>> ppc405->soc.ram_bases,
>>> + ppc405->soc.ram_sizes,
>>> 33333333, &uicdev, kernel_filename == NULL ? 0 :
>>> 1);
>>>
>>> /* allocate and load BIOS */
>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>> index d6420c88d3a6..adadb3a0ae08 100644
>>> --- a/hw/ppc/ppc405_uc.c
>>> +++ b/hw/ppc/ppc405_uc.c
>>> @@ -30,6 +30,7 @@
>>> #include "hw/ppc/ppc.h"
>>> #include "hw/i2c/ppc4xx_i2c.h"
>>> #include "hw/irq.h"
>>> +#include "hw/qdev-properties.h"
>>> #include "ppc405.h"
>>> #include "hw/char/serial.h"
>>> #include "qemu/timer.h"
>>> @@ -1530,3 +1531,42 @@ PowerPCCPU *ppc405ep_init(MemoryRegion
>>> *address_space_mem,
>>>
>>> return cpu;
>>> }
>>> +
>>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>> +{
>>> + Ppc405SoCState *s = PPC405_SOC(dev);
>>> +
>>> + /* Initialize only one bank */
>>> + s->ram_bases[0] = 0;
>>> + s->ram_sizes[0] = s->ram_size;
>>> + memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
>>> + "ppc405.sdram0", s->dram_mr,
>>> + s->ram_bases[0], s->ram_sizes[0]);
>>> +}
>>> +
>>> +static Property ppc405_soc_properties[] = {
>>> + DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>>> + MemoryRegion *),
>>> + DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>
>> I'm not sure why we need to duplicate these in the soc if they are always
>> the same as machine->ram and machine->ram_size.
>
> There are machines with multi SoCs. PowerNV can have 16.
>
> But that's not the reason here, we pass the dram memory region to the SoC
> for controllers that might need it for memory transactions, typically DMAs.
> In this case, it's the SDRAM controller which creates slices of RAM for
> each available RAM bank.
>
>> Is it theoretically possible to have a soc where it uses ram that's not the
>> whole ram?
>
> Yes.
>
>> If not then you could just uose machine which is accessible either as
>> current_machine or qdev_get_machine()
>
> These are QEMU globals. We should avoid using them in device models.
>
>> (also the parent of out soc but we don't know how to get that). If setting
>> ram this way
>> is still desired do we separately need to set its size or we could use
>> memory_region_size() instead?
>
> Let's keep SDRAM modeling for the next patchset.
OK.
>
>>> +
>>> +static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(oc);
>>> +
>>> + dc->realize = ppc405_soc_realize;
>>> + dc->user_creatable = false;
>>
>> May need a comment explaining why user_creatable = false. (Also for all
>> other similar lines in other patches, I won't repeat this there.)
>
> TYPE_PPC405_SOC devices can not be created from the QEMU command line.
> it doesn't make sense. That's what 'dc->user_creatable = false' means.
I know but near the definition of user_creatable there's a comment
demanding that each occurance has to have a comment explaining why.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
>>
>> Regards,
>> BALATON Zoltan
>>
>>> + device_class_set_props(dc, ppc405_soc_properties);
>>> +}
>>> +
>>> +static const TypeInfo ppc405_types[] = {
>>> + {
>>> + .name = TYPE_PPC405_SOC,
>>> + .parent = TYPE_DEVICE,
>>> + .instance_size = sizeof(Ppc405SoCState),
>>> + .class_init = ppc405_soc_class_init,
>>> + }
>>> +};
>>> +
>>> +DEFINE_TYPES(ppc405_types)
>>>
>
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (4 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 12:59 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU Cédric Le Goater
` (16 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize(). We can also adjust the number of banks now
that we have control on ppc4xx_sdram_init().
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 12 ++--
hw/ppc/ppc405_boards.c | 12 ++--
hw/ppc/ppc405_uc.c | 123 ++++++++++++++++++++---------------------
3 files changed, 70 insertions(+), 77 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 66dc21cdfed8..dc862bc8614c 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -73,9 +73,14 @@ struct Ppc405SoCState {
/* Public */
MemoryRegion ram_banks[2];
hwaddr ram_bases[2], ram_sizes[2];
+ bool do_dram_init;
MemoryRegion *dram_mr;
hwaddr ram_size;
+
+ uint32_t sysclk;
+ PowerPCCPU *cpu;
+ DeviceState *uic;
};
/* PowerPC 405 core */
@@ -84,11 +89,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
void ppc405_ebc_init(CPUPPCState *env);
-PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
- MemoryRegion ram_memories[2],
- hwaddr ram_bases[2],
- hwaddr ram_sizes[2],
- uint32_t sysclk, DeviceState **uicdev,
- int do_init);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1dc5065fcc1d..0b39ff08bd65 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
- PowerPCCPU *cpu;
MemoryRegion *sysmem = get_system_memory();
- DeviceState *uicdev;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
+ object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
+ !(kernel_filename == NULL), &error_abort);
+ object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
+ &error_abort);
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
- cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
- ppc405->soc.ram_sizes,
- 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
@@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- boot_from_kernel(machine, cpu);
+ boot_from_kernel(machine, ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index adadb3a0ae08..abcc2537140c 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1432,121 +1432,118 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
#endif
}
-PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
- MemoryRegion ram_memories[2],
- hwaddr ram_bases[2],
- hwaddr ram_sizes[2],
- uint32_t sysclk, DeviceState **uicdevp,
- int do_init)
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
+ Ppc405SoCState *s = PPC405_SOC(dev);
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
- PowerPCCPU *cpu;
CPUPPCState *env;
- DeviceState *uicdev;
- SysBusDevice *uicsbd;
memset(clk_setup, 0, sizeof(clk_setup));
+
/* init CPUs */
- cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
+ s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
&clk_setup[PPC405EP_CPU_CLK],
- &tlb_clk_setup, sysclk);
- env = &cpu->env;
+ &tlb_clk_setup, s->sysclk);
+ env = &s->cpu->env;
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
- /* Internal devices init */
- /* Memory mapped devices registers */
+
+ /* CPU control */
+ ppc405ep_cpc_init(env, clk_setup, s->sysclk);
+
/* PLB arbitrer */
ppc4xx_plb_init(env);
+
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
+
/* OBP arbitrer */
ppc4xx_opba_init(0xef600600);
+
/* Universal interrupt controller */
- uicdev = qdev_new(TYPE_PPC_UIC);
- uicsbd = SYS_BUS_DEVICE(uicdev);
+ s->uic = qdev_new(TYPE_PPC_UIC);
- object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
+ object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
&error_fatal);
- sysbus_realize_and_unref(uicsbd, &error_fatal);
-
- sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
- qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
- sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
- qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
+ if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
+ return;
+ }
- *uicdevp = uicdev;
+ sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
+ qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
+ sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
+ qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
- ram_bases, ram_sizes, do_init);
+ s->ram_bases[0] = 0;
+ s->ram_sizes[0] = s->ram_size;
+ memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
+ "ppc405.sdram0", s->dram_mr,
+ s->ram_bases[0], s->ram_sizes[0]);
+
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1,
+ s->ram_banks, s->ram_bases, s->ram_sizes,
+ s->do_dram_init);
+
/* External bus controller */
ppc405_ebc_init(env);
+
/* DMA controller */
- dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
- dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
- dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
- dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
+ dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
+ dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
+ dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
+ dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
ppc405_dma_init(env, dma_irqs);
- /* IIC controller */
+
+ /* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(uicdev, 2));
+ qdev_get_gpio_in(s->uic, 2));
/* GPIO */
ppc405_gpio_init(0xef600700);
+
/* Serial ports */
if (serial_hd(0) != NULL) {
- serial_mm_init(address_space_mem, 0xef600300, 0,
- qdev_get_gpio_in(uicdev, 0),
+ serial_mm_init(get_system_memory(), 0xef600300, 0,
+ qdev_get_gpio_in(s->uic, 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
- serial_mm_init(address_space_mem, 0xef600400, 0,
- qdev_get_gpio_in(uicdev, 1),
+ serial_mm_init(get_system_memory(), 0xef600400, 0,
+ qdev_get_gpio_in(s->uic, 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
+
/* OCM */
ppc405_ocm_init(env);
+
/* GPT */
- gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
- gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
- gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
- gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
- gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
+ gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
+ gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
+ gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
+ gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
+ gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
ppc4xx_gpt_init(0xef600000, gpt_irqs);
- /* PCI */
- /* Uses UIC IRQs 3, 16, 18 */
+
/* MAL */
- mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
- mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
- mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
- mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
+ mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
+ mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
+ mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
+ mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
ppc4xx_mal_init(env, 4, 2, mal_irqs);
+
/* Ethernet */
/* Uses UIC IRQs 9, 15, 17 */
- /* CPU control */
- ppc405ep_cpc_init(env, clk_setup, sysclk);
-
- return cpu;
-}
-
-static void ppc405_soc_realize(DeviceState *dev, Error **errp)
-{
- Ppc405SoCState *s = PPC405_SOC(dev);
-
- /* Initialize only one bank */
- s->ram_bases[0] = 0;
- s->ram_sizes[0] = s->ram_size;
- memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
- "ppc405.sdram0", s->dram_mr,
- s->ram_bases[0], s->ram_sizes[0]);
}
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
+ DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
+ DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC
2022-08-08 10:27 ` [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
@ 2022-08-08 12:59 ` BALATON Zoltan
2022-08-08 15:20 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 12:59 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 10963 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> This moves all the code previously done in the ppc405ep_init() routine
> under ppc405_soc_realize(). We can also adjust the number of banks now
> that we have control on ppc4xx_sdram_init().
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 12 ++--
> hw/ppc/ppc405_boards.c | 12 ++--
> hw/ppc/ppc405_uc.c | 123 ++++++++++++++++++++---------------------
> 3 files changed, 70 insertions(+), 77 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 66dc21cdfed8..dc862bc8614c 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -73,9 +73,14 @@ struct Ppc405SoCState {
> /* Public */
> MemoryRegion ram_banks[2];
> hwaddr ram_bases[2], ram_sizes[2];
> + bool do_dram_init;
>
> MemoryRegion *dram_mr;
> hwaddr ram_size;
> +
> + uint32_t sysclk;
Putting this together with dram_init would keep properties set from
outside together which is clearer than here with others set by to object
itself but this is just a small thing, not really important.
> + PowerPCCPU *cpu;
> + DeviceState *uic;
> };
>
> /* PowerPC 405 core */
> @@ -84,11 +89,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
> void ppc4xx_plb_init(CPUPPCState *env);
> void ppc405_ebc_init(CPUPPCState *env);
>
> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
> - MemoryRegion ram_memories[2],
> - hwaddr ram_bases[2],
> - hwaddr ram_sizes[2],
> - uint32_t sysclk, DeviceState **uicdev,
> - int do_init);
> -
> #endif /* PPC405_H */
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 1dc5065fcc1d..0b39ff08bd65 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> - PowerPCCPU *cpu;
> MemoryRegion *sysmem = get_system_memory();
> - DeviceState *uicdev;
>
> if (machine->ram_size != mc->default_ram_size) {
> char *sz = size_to_str(mc->default_ram_size);
> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
> machine->ram_size, &error_fatal);
> object_property_set_link(OBJECT(&ppc405->soc), "dram",
> OBJECT(machine->ram), &error_abort);
> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
> + !(kernel_filename == NULL), &error_abort);
Maybe clearer as kernel_filename != NULL
Is there a problem with indentation in this patch? Does it pass
checkpatch.pl?
Regards,
BALATON Zoltan
> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
> + &error_abort);
> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>
> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
> - ppc405->soc.ram_sizes,
> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
> -
> /* allocate and load BIOS */
> if (machine->firmware) {
> MemoryRegion *bios = g_new(MemoryRegion, 1);
> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>
> /* Load ELF kernel and rootfs.cpio */
> } else if (kernel_filename && !machine->firmware) {
> - boot_from_kernel(machine, cpu);
> + boot_from_kernel(machine, ppc405->soc.cpu);
> }
> }
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index adadb3a0ae08..abcc2537140c 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1432,121 +1432,118 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
> #endif
> }
>
> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
> - MemoryRegion ram_memories[2],
> - hwaddr ram_bases[2],
> - hwaddr ram_sizes[2],
> - uint32_t sysclk, DeviceState **uicdevp,
> - int do_init)
> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> + Ppc405SoCState *s = PPC405_SOC(dev);
> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> - PowerPCCPU *cpu;
> CPUPPCState *env;
> - DeviceState *uicdev;
> - SysBusDevice *uicsbd;
>
> memset(clk_setup, 0, sizeof(clk_setup));
> +
> /* init CPUs */
> - cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
> + s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
> &clk_setup[PPC405EP_CPU_CLK],
> - &tlb_clk_setup, sysclk);
> - env = &cpu->env;
> + &tlb_clk_setup, s->sysclk);
> + env = &s->cpu->env;
> clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
> clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
> - /* Internal devices init */
> - /* Memory mapped devices registers */
> +
> + /* CPU control */
> + ppc405ep_cpc_init(env, clk_setup, s->sysclk);
> +
> /* PLB arbitrer */
> ppc4xx_plb_init(env);
> +
> /* PLB to OPB bridge */
> ppc4xx_pob_init(env);
> +
> /* OBP arbitrer */
> ppc4xx_opba_init(0xef600600);
> +
> /* Universal interrupt controller */
> - uicdev = qdev_new(TYPE_PPC_UIC);
> - uicsbd = SYS_BUS_DEVICE(uicdev);
> + s->uic = qdev_new(TYPE_PPC_UIC);
>
> - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
> &error_fatal);
> - sysbus_realize_and_unref(uicsbd, &error_fatal);
> -
> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
> + if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
> + return;
> + }
>
> - *uicdevp = uicdev;
> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> /* XXX 405EP has no ECC interrupt */
> - ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
> - ram_bases, ram_sizes, do_init);
> + s->ram_bases[0] = 0;
> + s->ram_sizes[0] = s->ram_size;
> + memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
> + "ppc405.sdram0", s->dram_mr,
> + s->ram_bases[0], s->ram_sizes[0]);
> +
> + ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1,
> + s->ram_banks, s->ram_bases, s->ram_sizes,
> + s->do_dram_init);
> +
> /* External bus controller */
> ppc405_ebc_init(env);
> +
> /* DMA controller */
> - dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
> - dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
> - dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
> - dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
> + dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
> + dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
> + dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
> + dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
> ppc405_dma_init(env, dma_irqs);
> - /* IIC controller */
> +
> + /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> - qdev_get_gpio_in(uicdev, 2));
> + qdev_get_gpio_in(s->uic, 2));
> /* GPIO */
> ppc405_gpio_init(0xef600700);
> +
> /* Serial ports */
> if (serial_hd(0) != NULL) {
> - serial_mm_init(address_space_mem, 0xef600300, 0,
> - qdev_get_gpio_in(uicdev, 0),
> + serial_mm_init(get_system_memory(), 0xef600300, 0,
> + qdev_get_gpio_in(s->uic, 0),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
> DEVICE_BIG_ENDIAN);
> }
> if (serial_hd(1) != NULL) {
> - serial_mm_init(address_space_mem, 0xef600400, 0,
> - qdev_get_gpio_in(uicdev, 1),
> + serial_mm_init(get_system_memory(), 0xef600400, 0,
> + qdev_get_gpio_in(s->uic, 1),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
> DEVICE_BIG_ENDIAN);
> }
> +
> /* OCM */
> ppc405_ocm_init(env);
> +
> /* GPT */
> - gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
> - gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
> - gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
> - gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
> - gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
> + gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
> + gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
> + gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
> + gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
> + gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
> ppc4xx_gpt_init(0xef600000, gpt_irqs);
> - /* PCI */
> - /* Uses UIC IRQs 3, 16, 18 */
> +
> /* MAL */
> - mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
> - mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
> - mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
> - mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
> + mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
> + mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
> + mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
> + mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
> ppc4xx_mal_init(env, 4, 2, mal_irqs);
> +
> /* Ethernet */
> /* Uses UIC IRQs 9, 15, 17 */
> - /* CPU control */
> - ppc405ep_cpc_init(env, clk_setup, sysclk);
> -
> - return cpu;
> -}
> -
> -static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> -{
> - Ppc405SoCState *s = PPC405_SOC(dev);
> -
> - /* Initialize only one bank */
> - s->ram_bases[0] = 0;
> - s->ram_sizes[0] = s->ram_size;
> - memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
> - "ppc405.sdram0", s->dram_mr,
> - s->ram_bases[0], s->ram_sizes[0]);
> }
>
> static Property ppc405_soc_properties[] = {
> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> MemoryRegion *),
> + DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
> + DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC
2022-08-08 12:59 ` BALATON Zoltan
@ 2022-08-08 15:20 ` Cédric Le Goater
0 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 15:20 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 14:59, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> This moves all the code previously done in the ppc405ep_init() routine
>> under ppc405_soc_realize(). We can also adjust the number of banks now
>> that we have control on ppc4xx_sdram_init().
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h | 12 ++--
>> hw/ppc/ppc405_boards.c | 12 ++--
>> hw/ppc/ppc405_uc.c | 123 ++++++++++++++++++++---------------------
>> 3 files changed, 70 insertions(+), 77 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index 66dc21cdfed8..dc862bc8614c 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -73,9 +73,14 @@ struct Ppc405SoCState {
>> /* Public */
>> MemoryRegion ram_banks[2];
>> hwaddr ram_bases[2], ram_sizes[2];
>> + bool do_dram_init;
>>
>> MemoryRegion *dram_mr;
>> hwaddr ram_size;
>> +
>> + uint32_t sysclk;
>
> Putting this together with dram_init would keep properties set from outside together which is clearer than here with others set by to object itself but this is just a small thing, not really important.
Makes sense but I am removing SoC::sysclk in the following patches.
>
>> + PowerPCCPU *cpu;
>> + DeviceState *uic;
>> };
>>
>> /* PowerPC 405 core */
>> @@ -84,11 +89,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
>> void ppc4xx_plb_init(CPUPPCState *env);
>> void ppc405_ebc_init(CPUPPCState *env);
>>
>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>> - MemoryRegion ram_memories[2],
>> - hwaddr ram_bases[2],
>> - hwaddr ram_sizes[2],
>> - uint32_t sysclk, DeviceState **uicdev,
>> - int do_init);
>> -
>> #endif /* PPC405_H */
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 1dc5065fcc1d..0b39ff08bd65 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>> const char *kernel_filename = machine->kernel_filename;
>> - PowerPCCPU *cpu;
>> MemoryRegion *sysmem = get_system_memory();
>> - DeviceState *uicdev;
>>
>> if (machine->ram_size != mc->default_ram_size) {
>> char *sz = size_to_str(mc->default_ram_size);
>> @@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
>> machine->ram_size, &error_fatal);
>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>> OBJECT(machine->ram), &error_abort);
>> + object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>> + !(kernel_filename == NULL), &error_abort);
>
> Maybe clearer as kernel_filename != NULL
ok.
> Is there a problem with indentation in this patch? Does it pass checkpatch.pl?
No. All is fine.
Thanks,
C.
>
> Regards,
> BALATON Zoltan
>
>> + object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>> + &error_abort);
>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
>>
>> - cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
>> - ppc405->soc.ram_sizes,
>> - 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>> -
>> /* allocate and load BIOS */
>> if (machine->firmware) {
>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>> @@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>>
>> /* Load ELF kernel and rootfs.cpio */
>> } else if (kernel_filename && !machine->firmware) {
>> - boot_from_kernel(machine, cpu);
>> + boot_from_kernel(machine, ppc405->soc.cpu);
>> }
>> }
>>
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index adadb3a0ae08..abcc2537140c 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -1432,121 +1432,118 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
>> #endif
>> }
>>
>> -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
>> - MemoryRegion ram_memories[2],
>> - hwaddr ram_bases[2],
>> - hwaddr ram_sizes[2],
>> - uint32_t sysclk, DeviceState **uicdevp,
>> - int do_init)
>> +static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> {
>> + Ppc405SoCState *s = PPC405_SOC(dev);
>> clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>> - PowerPCCPU *cpu;
>> CPUPPCState *env;
>> - DeviceState *uicdev;
>> - SysBusDevice *uicsbd;
>>
>> memset(clk_setup, 0, sizeof(clk_setup));
>> +
>> /* init CPUs */
>> - cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
>> + s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
>> &clk_setup[PPC405EP_CPU_CLK],
>> - &tlb_clk_setup, sysclk);
>> - env = &cpu->env;
>> + &tlb_clk_setup, s->sysclk);
>> + env = &s->cpu->env;
>> clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
>> clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
>> - /* Internal devices init */
>> - /* Memory mapped devices registers */
>> +
>> + /* CPU control */
>> + ppc405ep_cpc_init(env, clk_setup, s->sysclk);
>> +
>> /* PLB arbitrer */
>> ppc4xx_plb_init(env);
>> +
>> /* PLB to OPB bridge */
>> ppc4xx_pob_init(env);
>> +
>> /* OBP arbitrer */
>> ppc4xx_opba_init(0xef600600);
>> +
>> /* Universal interrupt controller */
>> - uicdev = qdev_new(TYPE_PPC_UIC);
>> - uicsbd = SYS_BUS_DEVICE(uicdev);
>> + s->uic = qdev_new(TYPE_PPC_UIC);
>>
>> - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
>> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
>> &error_fatal);
>> - sysbus_realize_and_unref(uicsbd, &error_fatal);
>> -
>> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
>> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
>> - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
>> - qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
>> + if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
>> + return;
>> + }
>>
>> - *uicdevp = uicdev;
>> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
>> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
>> + sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
>> + qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
>>
>> /* SDRAM controller */
>> /* XXX 405EP has no ECC interrupt */
>> - ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
>> - ram_bases, ram_sizes, do_init);
>> + s->ram_bases[0] = 0;
>> + s->ram_sizes[0] = s->ram_size;
>> + memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
>> + "ppc405.sdram0", s->dram_mr,
>> + s->ram_bases[0], s->ram_sizes[0]);
>> +
>> + ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1,
>> + s->ram_banks, s->ram_bases, s->ram_sizes,
>> + s->do_dram_init);
>> +
>> /* External bus controller */
>> ppc405_ebc_init(env);
>> +
>> /* DMA controller */
>> - dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
>> - dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
>> - dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
>> - dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
>> + dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
>> + dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
>> + dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
>> + dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
>> ppc405_dma_init(env, dma_irqs);
>> - /* IIC controller */
>> +
>> + /* I2C controller */
>> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
>> - qdev_get_gpio_in(uicdev, 2));
>> + qdev_get_gpio_in(s->uic, 2));
>> /* GPIO */
>> ppc405_gpio_init(0xef600700);
>> +
>> /* Serial ports */
>> if (serial_hd(0) != NULL) {
>> - serial_mm_init(address_space_mem, 0xef600300, 0,
>> - qdev_get_gpio_in(uicdev, 0),
>> + serial_mm_init(get_system_memory(), 0xef600300, 0,
>> + qdev_get_gpio_in(s->uic, 0),
>> PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
>> DEVICE_BIG_ENDIAN);
>> }
>> if (serial_hd(1) != NULL) {
>> - serial_mm_init(address_space_mem, 0xef600400, 0,
>> - qdev_get_gpio_in(uicdev, 1),
>> + serial_mm_init(get_system_memory(), 0xef600400, 0,
>> + qdev_get_gpio_in(s->uic, 1),
>> PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
>> DEVICE_BIG_ENDIAN);
>> }
>> +
>> /* OCM */
>> ppc405_ocm_init(env);
>> +
>> /* GPT */
>> - gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
>> - gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
>> - gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
>> - gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
>> - gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
>> + gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
>> + gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
>> + gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
>> + gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
>> + gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
>> ppc4xx_gpt_init(0xef600000, gpt_irqs);
>> - /* PCI */
>> - /* Uses UIC IRQs 3, 16, 18 */
>> +
>> /* MAL */
>> - mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
>> - mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
>> - mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
>> - mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
>> + mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
>> + mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
>> + mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
>> + mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
>> ppc4xx_mal_init(env, 4, 2, mal_irqs);
>> +
>> /* Ethernet */
>> /* Uses UIC IRQs 9, 15, 17 */
>> - /* CPU control */
>> - ppc405ep_cpc_init(env, clk_setup, sysclk);
>> -
>> - return cpu;
>> -}
>> -
>> -static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> -{
>> - Ppc405SoCState *s = PPC405_SOC(dev);
>> -
>> - /* Initialize only one bank */
>> - s->ram_bases[0] = 0;
>> - s->ram_sizes[0] = s->ram_size;
>> - memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
>> - "ppc405.sdram0", s->dram_mr,
>> - s->ram_bases[0], s->ram_sizes[0]);
>> }
>>
>> static Property ppc405_soc_properties[] = {
>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>> MemoryRegion *),
>> + DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
>> + DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>> DEFINE_PROP_END_OF_LIST(),
>> };
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (5 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 13:17 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model Cédric Le Goater
` (15 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in the SoC realize routine. We will clean that up in the
following patches.
ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
this could be done in model initializer of the CPU families needing it.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 2 +-
include/hw/ppc/ppc4xx.h | 1 +
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc405_uc.c | 35 +++++++++++++++++++++++++----------
hw/ppc/ppc4xx_devs.c | 2 +-
5 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index dc862bc8614c..8cc76cc8b3fe 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -79,7 +79,7 @@ struct Ppc405SoCState {
hwaddr ram_size;
uint32_t sysclk;
- PowerPCCPU *cpu;
+ PowerPCCPU cpu;
DeviceState *uic;
};
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 980f964b5a91..021376c2d260 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -29,6 +29,7 @@
#include "exec/memory.h"
/* PowerPC 4xx core initialization */
+void ppc4xx_reset(void *opaque);
PowerPCCPU *ppc4xx_init(const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 0b39ff08bd65..5ba12d60bc00 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- boot_from_kernel(machine, ppc405->soc.cpu);
+ boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index abcc2537140c..fa3853df2233 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1432,22 +1432,36 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
#endif
}
+static void ppc405_soc_instance_init(Object *obj)
+{
+ Ppc405SoCState *s = PPC405_SOC(obj);
+
+ object_initialize_child(obj, "cpu", &s->cpu,
+ POWERPC_CPU_TYPE_NAME("405ep"));
+}
+
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
+ clk_setup_t clk_setup[PPC405EP_CLK_NB];
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUPPCState *env;
memset(clk_setup, 0, sizeof(clk_setup));
/* init CPUs */
- s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
- &clk_setup[PPC405EP_CPU_CLK],
- &tlb_clk_setup, s->sysclk);
- env = &s->cpu->env;
- clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
- clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
+ if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
+ return;
+ }
+ qemu_register_reset(ppc4xx_reset, &s->cpu);
+
+ env = &s->cpu.env;
+
+ clk_setup[PPC405EP_CPU_CLK].cb =
+ ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
+ clk_setup[PPC405EP_CPU_CLK].opaque = env;
+
+ ppc_dcr_init(env, NULL, NULL);
/* CPU control */
ppc405ep_cpc_init(env, clk_setup, s->sysclk);
@@ -1464,16 +1478,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
- object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
+ object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
&error_fatal);
if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
- qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
+ qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
- qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
+ qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
@@ -1562,6 +1576,7 @@ static const TypeInfo ppc405_types[] = {
.name = TYPE_PPC405_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405SoCState),
+ .instance_init = ppc405_soc_instance_init,
.class_init = ppc405_soc_class_init,
}
};
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 737c0896b4f8..f20098cf417c 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -37,7 +37,7 @@
#include "qapi/error.h"
#include "trace.h"
-static void ppc4xx_reset(void *opaque)
+void ppc4xx_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU
2022-08-08 10:27 ` [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU Cédric Le Goater
@ 2022-08-08 13:17 ` BALATON Zoltan
2022-08-08 16:06 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 13:17 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 5888 bytes --]
Patch title is wrong. It should be Embed CPU object in SoC as it's not
QOMifies the CPU just moves it from dinamically allocated to embedded.
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> Drop the use of ppc4xx_init() and duplicate a bit of code related to
> clocks in the SoC realize routine. We will clean that up in the
> following patches.
Could this be split off into a separate patch? Maybe it would be clearer
that way what's related to stop using ppc4xx_init() (which is needed
because it dinamically allocates CPU) and what's the embedding it in the
soc object.
> ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
> this could be done in model initializer of the CPU families needing it.
>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 2 +-
> include/hw/ppc/ppc4xx.h | 1 +
> hw/ppc/ppc405_boards.c | 2 +-
> hw/ppc/ppc405_uc.c | 35 +++++++++++++++++++++++++----------
> hw/ppc/ppc4xx_devs.c | 2 +-
> 5 files changed, 29 insertions(+), 13 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index dc862bc8614c..8cc76cc8b3fe 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -79,7 +79,7 @@ struct Ppc405SoCState {
> hwaddr ram_size;
>
> uint32_t sysclk;
> - PowerPCCPU *cpu;
> + PowerPCCPU cpu;
> DeviceState *uic;
> };
>
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 980f964b5a91..021376c2d260 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -29,6 +29,7 @@
> #include "exec/memory.h"
>
> /* PowerPC 4xx core initialization */
> +void ppc4xx_reset(void *opaque);
> PowerPCCPU *ppc4xx_init(const char *cpu_model,
> clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
> uint32_t sysclk);
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 0b39ff08bd65..5ba12d60bc00 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>
> /* Load ELF kernel and rootfs.cpio */
> } else if (kernel_filename && !machine->firmware) {
> - boot_from_kernel(machine, ppc405->soc.cpu);
> + boot_from_kernel(machine, &ppc405->soc.cpu);
> }
> }
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index abcc2537140c..fa3853df2233 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1432,22 +1432,36 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
> #endif
> }
>
> +static void ppc405_soc_instance_init(Object *obj)
> +{
> + Ppc405SoCState *s = PPC405_SOC(obj);
> +
> + object_initialize_child(obj, "cpu", &s->cpu,
> + POWERPC_CPU_TYPE_NAME("405ep"));
> +}
> +
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
> + clk_setup_t clk_setup[PPC405EP_CLK_NB];
> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> CPUPPCState *env;
>
> memset(clk_setup, 0, sizeof(clk_setup));
>
> /* init CPUs */
> - s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
> - &clk_setup[PPC405EP_CPU_CLK],
> - &tlb_clk_setup, s->sysclk);
> - env = &s->cpu->env;
> - clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
> - clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
> + if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
> + return;
> + }
> + qemu_register_reset(ppc4xx_reset, &s->cpu);
> +
> + env = &s->cpu.env;
> +
> + clk_setup[PPC405EP_CPU_CLK].cb =
> + ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
> + clk_setup[PPC405EP_CPU_CLK].opaque = env;
> +
> + ppc_dcr_init(env, NULL, NULL);
>
> /* CPU control */
> ppc405ep_cpc_init(env, clk_setup, s->sysclk);
> @@ -1464,16 +1478,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* Universal interrupt controller */
> s->uic = qdev_new(TYPE_PPC_UIC);
>
> - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
> &error_fatal);
> if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
> return;
> }
>
> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
> - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
> + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
> - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
> + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> /* XXX 405EP has no ECC interrupt */
> @@ -1562,6 +1576,7 @@ static const TypeInfo ppc405_types[] = {
> .name = TYPE_PPC405_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(Ppc405SoCState),
> + .instance_init = ppc405_soc_instance_init,
> .class_init = ppc405_soc_class_init,
> }
> };
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 737c0896b4f8..f20098cf417c 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -37,7 +37,7 @@
> #include "qapi/error.h"
> #include "trace.h"
>
> -static void ppc4xx_reset(void *opaque)
> +void ppc4xx_reset(void *opaque)
> {
> PowerPCCPU *cpu = opaque;
This just calls cpu_reset() and does nothing else. Can't that be
registered directly so this could be kept static to this file? Why do we
need this at all? Isn't the cpu object reset automatically? Why do we need
to register it separately?
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU
2022-08-08 13:17 ` BALATON Zoltan
@ 2022-08-08 16:06 ` Cédric Le Goater
2022-08-08 17:05 ` BALATON Zoltan
0 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 16:06 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 15:17, BALATON Zoltan wrote:
>
> Patch title is wrong. It should be Embed CPU object in SoC as it's not QOMifies the CPU just moves it from dinamically allocated to embedded.
>
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> Drop the use of ppc4xx_init() and duplicate a bit of code related to
>> clocks in the SoC realize routine. We will clean that up in the
>> following patches.
>
> Could this be split off into a separate patch? Maybe it would be clearer that way what's related to stop using ppc4xx_init() (which is needed because it dinamically allocates CPU) and what's the embedding it in the soc object.
I'd rather not. It has been painful enough to untangle. Let's keep it that
way. And, this part is further changed in the CPC patch.
>> ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
>> this could be done in model initializer of the CPU families needing it.
>>
>> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h | 2 +-
>> include/hw/ppc/ppc4xx.h | 1 +
>> hw/ppc/ppc405_boards.c | 2 +-
>> hw/ppc/ppc405_uc.c | 35 +++++++++++++++++++++++++----------
>> hw/ppc/ppc4xx_devs.c | 2 +-
>> 5 files changed, 29 insertions(+), 13 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index dc862bc8614c..8cc76cc8b3fe 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -79,7 +79,7 @@ struct Ppc405SoCState {
>> hwaddr ram_size;
>>
>> uint32_t sysclk;
>> - PowerPCCPU *cpu;
>> + PowerPCCPU cpu;
>> DeviceState *uic;
>> };
>>
>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>> index 980f964b5a91..021376c2d260 100644
>> --- a/include/hw/ppc/ppc4xx.h
>> +++ b/include/hw/ppc/ppc4xx.h
>> @@ -29,6 +29,7 @@
>> #include "exec/memory.h"
>>
>> /* PowerPC 4xx core initialization */
>> +void ppc4xx_reset(void *opaque);
>> PowerPCCPU *ppc4xx_init(const char *cpu_model,
>> clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
>> uint32_t sysclk);
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 0b39ff08bd65..5ba12d60bc00 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>>
>> /* Load ELF kernel and rootfs.cpio */
>> } else if (kernel_filename && !machine->firmware) {
>> - boot_from_kernel(machine, ppc405->soc.cpu);
>> + boot_from_kernel(machine, &ppc405->soc.cpu);
>> }
>> }
>>
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index abcc2537140c..fa3853df2233 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -1432,22 +1432,36 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
>> #endif
>> }
>>
>> +static void ppc405_soc_instance_init(Object *obj)
>> +{
>> + Ppc405SoCState *s = PPC405_SOC(obj);
>> +
>> + object_initialize_child(obj, "cpu", &s->cpu,
>> + POWERPC_CPU_TYPE_NAME("405ep"));
>> +}
>> +
>> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> {
>> Ppc405SoCState *s = PPC405_SOC(dev);
>> - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>> + clk_setup_t clk_setup[PPC405EP_CLK_NB];
>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>> CPUPPCState *env;
>>
>> memset(clk_setup, 0, sizeof(clk_setup));
>>
>> /* init CPUs */
>> - s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
>> - &clk_setup[PPC405EP_CPU_CLK],
>> - &tlb_clk_setup, s->sysclk);
>> - env = &s->cpu->env;
>> - clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
>> - clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
>> + if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
>> + return;
>> + }
>> + qemu_register_reset(ppc4xx_reset, &s->cpu);
>> +
>> + env = &s->cpu.env;
>> +
>> + clk_setup[PPC405EP_CPU_CLK].cb =
>> + ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
>> + clk_setup[PPC405EP_CPU_CLK].opaque = env;
>> +
>> + ppc_dcr_init(env, NULL, NULL);
>>
>> /* CPU control */
>> ppc405ep_cpc_init(env, clk_setup, s->sysclk);
>> @@ -1464,16 +1478,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> /* Universal interrupt controller */
>> s->uic = qdev_new(TYPE_PPC_UIC);
>>
>> - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
>> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
>> &error_fatal);
>> if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
>> return;
>> }
>>
>> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
>> - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
>> + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
>> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
>> - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
>> + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>>
>> /* SDRAM controller */
>> /* XXX 405EP has no ECC interrupt */
>> @@ -1562,6 +1576,7 @@ static const TypeInfo ppc405_types[] = {
>> .name = TYPE_PPC405_SOC,
>> .parent = TYPE_DEVICE,
>> .instance_size = sizeof(Ppc405SoCState),
>> + .instance_init = ppc405_soc_instance_init,
>> .class_init = ppc405_soc_class_init,
>> }
>> };
>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>> index 737c0896b4f8..f20098cf417c 100644
>> --- a/hw/ppc/ppc4xx_devs.c
>> +++ b/hw/ppc/ppc4xx_devs.c
>> @@ -37,7 +37,7 @@
>> #include "qapi/error.h"
>> #include "trace.h"
>>
>> -static void ppc4xx_reset(void *opaque)
>> +void ppc4xx_reset(void *opaque)
>> {
>> PowerPCCPU *cpu = opaque;
>
> This just calls cpu_reset() and does nothing else. Can't that be registered directly so this could be kept static to this file?
what do you mean ?
> Why do we need this at all?
Oh yes. We need the CPU to start in a reset state, for U-boot at least.
> Isn't the cpu object reset automatically? Why do we need to register it separately?
All devices need a reset handler. The handler of the PPC405 CPU is registered
in ppc405_soc_realize() :
qemu_register_reset(ppc4xx_reset, &s->cpu);
If we had a more complex model, like pseries or PowerNV, we would install the
reset handler in the realize routine of the CPU model. But we don't.
Thanks,
C.
>
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU
2022-08-08 16:06 ` Cédric Le Goater
@ 2022-08-08 17:05 ` BALATON Zoltan
2022-08-08 17:14 ` Peter Maydell
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 17:05 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 8339 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> On 8/8/22 15:17, BALATON Zoltan wrote:
>>
>> Patch title is wrong. It should be Embed CPU object in SoC as it's not
>> QOMifies the CPU just moves it from dinamically allocated to embedded.
>>
>> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>>> Drop the use of ppc4xx_init() and duplicate a bit of code related to
>>> clocks in the SoC realize routine. We will clean that up in the
>>> following patches.
>>
>> Could this be split off into a separate patch? Maybe it would be clearer
>> that way what's related to stop using ppc4xx_init() (which is needed
>> because it dinamically allocates CPU) and what's the embedding it in the
>> soc object.
>
> I'd rather not. It has been painful enough to untangle. Let's keep it that
> way. And, this part is further changed in the CPC patch.
OK, if nobody else thinks this should be split I'm OK with it.
>>> ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
>>> this could be done in model initializer of the CPU families needing it.
>>>
>>> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>> hw/ppc/ppc405.h | 2 +-
>>> include/hw/ppc/ppc4xx.h | 1 +
>>> hw/ppc/ppc405_boards.c | 2 +-
>>> hw/ppc/ppc405_uc.c | 35 +++++++++++++++++++++++++----------
>>> hw/ppc/ppc4xx_devs.c | 2 +-
>>> 5 files changed, 29 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>> index dc862bc8614c..8cc76cc8b3fe 100644
>>> --- a/hw/ppc/ppc405.h
>>> +++ b/hw/ppc/ppc405.h
>>> @@ -79,7 +79,7 @@ struct Ppc405SoCState {
>>> hwaddr ram_size;
>>>
>>> uint32_t sysclk;
>>> - PowerPCCPU *cpu;
>>> + PowerPCCPU cpu;
>>> DeviceState *uic;
>>> };
>>>
>>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>>> index 980f964b5a91..021376c2d260 100644
>>> --- a/include/hw/ppc/ppc4xx.h
>>> +++ b/include/hw/ppc/ppc4xx.h
>>> @@ -29,6 +29,7 @@
>>> #include "exec/memory.h"
>>>
>>> /* PowerPC 4xx core initialization */
>>> +void ppc4xx_reset(void *opaque);
>>> PowerPCCPU *ppc4xx_init(const char *cpu_model,
>>> clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
>>> uint32_t sysclk);
>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>> index 0b39ff08bd65..5ba12d60bc00 100644
>>> --- a/hw/ppc/ppc405_boards.c
>>> +++ b/hw/ppc/ppc405_boards.c
>>> @@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine)
>>>
>>> /* Load ELF kernel and rootfs.cpio */
>>> } else if (kernel_filename && !machine->firmware) {
>>> - boot_from_kernel(machine, ppc405->soc.cpu);
>>> + boot_from_kernel(machine, &ppc405->soc.cpu);
>>> }
>>> }
>>>
>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>> index abcc2537140c..fa3853df2233 100644
>>> --- a/hw/ppc/ppc405_uc.c
>>> +++ b/hw/ppc/ppc405_uc.c
>>> @@ -1432,22 +1432,36 @@ static void ppc405ep_cpc_init (CPUPPCState *env,
>>> clk_setup_t clk_setup[8],
>>> #endif
>>> }
>>>
>>> +static void ppc405_soc_instance_init(Object *obj)
>>> +{
>>> + Ppc405SoCState *s = PPC405_SOC(obj);
>>> +
>>> + object_initialize_child(obj, "cpu", &s->cpu,
>>> + POWERPC_CPU_TYPE_NAME("405ep"));
>>> +}
>>> +
>>> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>> {
>>> Ppc405SoCState *s = PPC405_SOC(dev);
>>> - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
>>> + clk_setup_t clk_setup[PPC405EP_CLK_NB];
>>> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
>>> CPUPPCState *env;
>>>
>>> memset(clk_setup, 0, sizeof(clk_setup));
>>>
>>> /* init CPUs */
>>> - s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
>>> - &clk_setup[PPC405EP_CPU_CLK],
>>> - &tlb_clk_setup, s->sysclk);
>>> - env = &s->cpu->env;
>>> - clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
>>> - clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
>>> + if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
>>> + return;
>>> + }
>>> + qemu_register_reset(ppc4xx_reset, &s->cpu);
>>> +
>>> + env = &s->cpu.env;
>>> +
>>> + clk_setup[PPC405EP_CPU_CLK].cb =
>>> + ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
>>> + clk_setup[PPC405EP_CPU_CLK].opaque = env;
>>> +
>>> + ppc_dcr_init(env, NULL, NULL);
>>>
>>> /* CPU control */
>>> ppc405ep_cpc_init(env, clk_setup, s->sysclk);
>>> @@ -1464,16 +1478,16 @@ static void ppc405_soc_realize(DeviceState *dev,
>>> Error **errp)
>>> /* Universal interrupt controller */
>>> s->uic = qdev_new(TYPE_PPC_UIC);
>>>
>>> - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
>>> + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
>>> &error_fatal);
>>> if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
>>> return;
>>> }
>>>
>>> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
>>> - qdev_get_gpio_in(DEVICE(s->cpu),
>>> PPC40x_INPUT_INT));
>>> + qdev_get_gpio_in(DEVICE(&s->cpu),
>>> PPC40x_INPUT_INT));
>>> sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
>>> - qdev_get_gpio_in(DEVICE(s->cpu),
>>> PPC40x_INPUT_CINT));
>>> + qdev_get_gpio_in(DEVICE(&s->cpu),
>>> PPC40x_INPUT_CINT));
>>>
>>> /* SDRAM controller */
>>> /* XXX 405EP has no ECC interrupt */
>>> @@ -1562,6 +1576,7 @@ static const TypeInfo ppc405_types[] = {
>>> .name = TYPE_PPC405_SOC,
>>> .parent = TYPE_DEVICE,
>>> .instance_size = sizeof(Ppc405SoCState),
>>> + .instance_init = ppc405_soc_instance_init,
>>> .class_init = ppc405_soc_class_init,
>>> }
>>> };
>>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>>> index 737c0896b4f8..f20098cf417c 100644
>>> --- a/hw/ppc/ppc4xx_devs.c
>>> +++ b/hw/ppc/ppc4xx_devs.c
>>> @@ -37,7 +37,7 @@
>>> #include "qapi/error.h"
>>> #include "trace.h"
>>>
>>> -static void ppc4xx_reset(void *opaque)
>>> +void ppc4xx_reset(void *opaque)
>>> {
>>> PowerPCCPU *cpu = opaque;
>>
>> This just calls cpu_reset() and does nothing else. Can't that be registered
>> directly so this could be kept static to this file?
>
> what do you mean ?
Something like qemu_register_reset(cpu_reset, &s->cpu); but I'm not sure
this is even needed.
>> Why do we need this at all?
>
> Oh yes. We need the CPU to start in a reset state, for U-boot at least.
>
>> Isn't the cpu object reset automatically? Why do we need to register it
>> separately?
>
> All devices need a reset handler. The handler of the PPC405 CPU is registered
> in ppc405_soc_realize() :
>
> qemu_register_reset(ppc4xx_reset, &s->cpu);
But the handler we register here just calls cpu_reset which seems to just
call the reset method of the CPU object. If we have nothing else to do
here do we need to explicitly call cpi_reset like this? Wouldn't the CPU
object be reset by qdev when resetting the machine or the soc its in? If
we have our own reset method we may call cpu_reset from there to make sure
the CPU is in a known state but is this needed when we don't want to do
anything else? I don't know how reset handling works but some machines
seems to do this and others don't.
> If we had a more complex model, like pseries or PowerNV, we would install the
> reset handler in the realize routine of the CPU model. But we don't.
If this is needed maybe you should add a soc_reset method and call
cpu_reset() from there and get rid of ppc4xx_reset or move it to
ppc405_uc.c if it's not used anywhere else, so it can be kept static and
does not need to be added to ppc4xx.h.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU
2022-08-08 17:05 ` BALATON Zoltan
@ 2022-08-08 17:14 ` Peter Maydell
2022-08-08 17:25 ` BALATON Zoltan
0 siblings, 1 reply; 51+ messages in thread
From: Peter Maydell @ 2022-08-08 17:14 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Cédric Le Goater, qemu-ppc, Daniel Henrique Barboza,
qemu-devel
On Mon, 8 Aug 2022 at 18:05, BALATON Zoltan <balaton@eik.bme.hu> wrote:
> But the handler we register here just calls cpu_reset which seems to just
> call the reset method of the CPU object. If we have nothing else to do
> here do we need to explicitly call cpi_reset like this? Wouldn't the CPU
> object be reset by qdev when resetting the machine or the soc its in? If
> we have our own reset method we may call cpu_reset from there to make sure
> the CPU is in a known state but is this needed when we don't want to do
> anything else? I don't know how reset handling works but some machines
> seems to do this and others don't.
You do unfortunately need to manually reset the CPU object. This is
because the 'automatic' qdev reset only works for devices that hang
off a bus (including sysbus devices). This is because it works by
having qdev_machine_creation_done() register a reset function which
does "reset the sysbus". Resetting a bus resets every device on it.
Resetting a device resets every bus it owns. (This means that for
instance PCI devices get reset because the PCI controller is on the
sysbus, so it gets reset, and it owns the PCI bus, so the PCI bus
resets when the controller is reset, and when the PCI bus resets
then all the devices on it are reset.) So reset propagates down
the bus tree, but it won't reach devices which aren't on that bus
tree at all. The most common case of "device which isn't on a bus"
is the CPU objects.
This is, clearly, a complete mess. I would strongly like to sort it
out, but to do that we need (a) a plan for what reset handling ought
to look like and (b) a transition plan for getting from here to there
without breaking everything in the process. I haven't had the time
to focus on that, though it's been nominally on my todo list for years.
In the meantime, it's the responsibility of something in architecture
specific code to arrange for the CPU objects to be reset -- whether
that's done directly by the board, or hidden in some other layer
of code, depends on the target arch. For instance for arm it's
hidden inside arm_load_kernel() and board models must therefore
call that function even if they have no intention of supporting
loading Linux kernels. For sparc it's done directly in the board code.
thanks
-- PMM
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU
2022-08-08 17:14 ` Peter Maydell
@ 2022-08-08 17:25 ` BALATON Zoltan
2022-08-09 10:09 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 17:25 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, qemu-ppc, Daniel Henrique Barboza,
qemu-devel
On Mon, 8 Aug 2022, Peter Maydell wrote:
> On Mon, 8 Aug 2022 at 18:05, BALATON Zoltan <balaton@eik.bme.hu> wrote:
>> But the handler we register here just calls cpu_reset which seems to just
>> call the reset method of the CPU object. If we have nothing else to do
>> here do we need to explicitly call cpi_reset like this? Wouldn't the CPU
>> object be reset by qdev when resetting the machine or the soc its in? If
>> we have our own reset method we may call cpu_reset from there to make sure
>> the CPU is in a known state but is this needed when we don't want to do
>> anything else? I don't know how reset handling works but some machines
>> seems to do this and others don't.
>
> You do unfortunately need to manually reset the CPU object. This is
> because the 'automatic' qdev reset only works for devices that hang
> off a bus (including sysbus devices). This is because it works by
> having qdev_machine_creation_done() register a reset function which
> does "reset the sysbus". Resetting a bus resets every device on it.
> Resetting a device resets every bus it owns. (This means that for
> instance PCI devices get reset because the PCI controller is on the
> sysbus, so it gets reset, and it owns the PCI bus, so the PCI bus
> resets when the controller is reset, and when the PCI bus resets
> then all the devices on it are reset.) So reset propagates down
> the bus tree, but it won't reach devices which aren't on that bus
> tree at all. The most common case of "device which isn't on a bus"
> is the CPU objects.
>
> This is, clearly, a complete mess. I would strongly like to sort it
> out, but to do that we need (a) a plan for what reset handling ought
> to look like and (b) a transition plan for getting from here to there
> without breaking everything in the process. I haven't had the time
> to focus on that, though it's been nominally on my todo list for years.
>
> In the meantime, it's the responsibility of something in architecture
> specific code to arrange for the CPU objects to be reset -- whether
> that's done directly by the board, or hidden in some other layer
> of code, depends on the target arch. For instance for arm it's
> hidden inside arm_load_kernel() and board models must therefore
> call that function even if they have no intention of supporting
> loading Linux kernels. For sparc it's done directly in the board code.
OK thanks for the clarification. Both bamboo and sam460ex has a
main_cpu_reset function that is registered from the machine init func
which calls cpu_reset. Maybe 405 boards could do the same for consistency?
It could also be added to the soc object's reset method as that owns the
cpu so maybe it may make more sense that way. This is probably also OK as
440 machines don't have soc object yet so it wouldn't cause any problems.
I think the ppc4xx_reset func was kept around because ppc4xx_init was also
kept but nothing else seems to use it so maybe these should become the soc
object's realize and reset methods and drop the current ppc4xx_init and
reset funcs?
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU
2022-08-08 17:25 ` BALATON Zoltan
@ 2022-08-09 10:09 ` Cédric Le Goater
0 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-09 10:09 UTC (permalink / raw)
To: BALATON Zoltan, Peter Maydell
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel
On 8/8/22 19:25, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Peter Maydell wrote:
>> On Mon, 8 Aug 2022 at 18:05, BALATON Zoltan <balaton@eik.bme.hu> wrote:
>>> But the handler we register here just calls cpu_reset which seems to just
>>> call the reset method of the CPU object. If we have nothing else to do
>>> here do we need to explicitly call cpi_reset like this? Wouldn't the CPU
>>> object be reset by qdev when resetting the machine or the soc its in? If
>>> we have our own reset method we may call cpu_reset from there to make sure
>>> the CPU is in a known state but is this needed when we don't want to do
>>> anything else? I don't know how reset handling works but some machines
>>> seems to do this and others don't.
>>
>> You do unfortunately need to manually reset the CPU object. This is
>> because the 'automatic' qdev reset only works for devices that hang
>> off a bus (including sysbus devices). This is because it works by
>> having qdev_machine_creation_done() register a reset function which
>> does "reset the sysbus". Resetting a bus resets every device on it.
>> Resetting a device resets every bus it owns. (This means that for
>> instance PCI devices get reset because the PCI controller is on the
>> sysbus, so it gets reset, and it owns the PCI bus, so the PCI bus
>> resets when the controller is reset, and when the PCI bus resets
>> then all the devices on it are reset.) So reset propagates down
>> the bus tree, but it won't reach devices which aren't on that bus
>> tree at all. The most common case of "device which isn't on a bus"
>> is the CPU objects.
>>
>> This is, clearly, a complete mess. I would strongly like to sort it
>> out, but to do that we need (a) a plan for what reset handling ought
>> to look like and (b) a transition plan for getting from here to there
>> without breaking everything in the process. I haven't had the time
>> to focus on that, though it's been nominally on my todo list for years.
>>
>> In the meantime, it's the responsibility of something in architecture
>> specific code to arrange for the CPU objects to be reset -- whether
>> that's done directly by the board, or hidden in some other layer
>> of code, depends on the target arch. For instance for arm it's
>> hidden inside arm_load_kernel() and board models must therefore
>> call that function even if they have no intention of supporting
>> loading Linux kernels. For sparc it's done directly in the board code.
>
> OK thanks for the clarification. Both bamboo and sam460ex has a main_cpu_reset function that is registered from the machine init func which calls cpu_reset. Maybe 405 boards could do the same for consistency? It could also be added to the soc object's reset method as that owns the cpu so maybe it may make more sense that way. This is probably also OK as 440 machines don't have soc object yet so it wouldn't cause any problems.
>
> I think the ppc4xx_reset func was kept around because ppc4xx_init was also kept but nothing else seems to use it so maybe these should become the soc object's realize and reset methods and drop the current ppc4xx_init and reset funcs?
Yes. I have moved the CPU reset routine under ppc405_uc.c and removed
ppc4xx_init() which is now unused.
Thanks,
C.
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (6 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 13:29 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 09/22] ppc/ppc405: QOM'ify CPC Cédric Le Goater
` (14 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model these accesses with a DCR namespace and DCR
memory regions but today the DCR handlers are installed in a DCR table
under the CPU. Instead introduce a little device model wrapper to hold
a CPU link and handle registration of DCR handlers.
The DCR device inherits from SysBus because most of these devices also
have a MMIO regions and/or IRQs. Being a SysBusDevice makes things
easier to install the device model in the overall SoC.
The "cpu" link should be considered as modeling the piece of HW logic
connecting the device to the DCR bus.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/ppc4xx.h | 17 +++++++++++++++
hw/ppc/ppc4xx_devs.c | 46 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 021376c2d260..bb373db0ba10 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -27,6 +27,7 @@
#include "hw/ppc/ppc.h"
#include "exec/memory.h"
+#include "hw/sysbus.h"
/* PowerPC 4xx core initialization */
void ppc4xx_reset(void *opaque);
@@ -50,4 +51,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
+/*
+ * Generic DCR device
+ */
+#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
+struct Ppc4xxDcrDeviceState {
+ SysBusDevice parent_obj;
+
+ PowerPCCPU *cpu;
+};
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write);
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp);
+
#endif /* PPC4XX_H */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f20098cf417c..e07bdba0f912 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -696,3 +696,49 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
mal, &dcr_read_mal, &dcr_write_mal);
}
}
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write)
+{
+ CPUPPCState *env;
+
+ assert(dev->cpu);
+
+ env = &dev->cpu->env;
+
+ ppc_dcr_register(env, dcrn, dev, dcr_read, dcr_write);
+}
+
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp)
+{
+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+ return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
+}
+
+
+static Property ppc4xx_dcr_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_dcr_properties);
+}
+
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_DCR_DEVICE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc4xxDcrDeviceState),
+ .class_init = ppc4xx_dcr_class_init,
+ .abstract = true,
+ }
+};
+
+DEFINE_TYPES(ppc4xx_types)
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model
2022-08-08 10:27 ` [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model Cédric Le Goater
@ 2022-08-08 13:29 ` BALATON Zoltan
2022-08-08 15:35 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 13:29 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 4348 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> The Device Control Registers (DCR) of on-SoC devices are accessed by
> software through the use of the mtdcr and mfdcr instructions. These
> are converted in transactions on a side band bus, the DCR bus, which
> connects the on-SoC devices to the CPU.
>
> Ideally, we should model these accesses with a DCR namespace and DCR
> memory regions but today the DCR handlers are installed in a DCR table
> under the CPU. Instead introduce a little device model wrapper to hold
> a CPU link and handle registration of DCR handlers.
>
> The DCR device inherits from SysBus because most of these devices also
> have a MMIO regions and/or IRQs. Being a SysBusDevice makes things
Drop "a", just "MMIO regions" due to plural. Also "makes it easier to
install" or "makes things easier".
> easier to install the device model in the overall SoC.
>
> The "cpu" link should be considered as modeling the piece of HW logic
> connecting the device to the DCR bus.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/ppc/ppc4xx.h | 17 +++++++++++++++
> hw/ppc/ppc4xx_devs.c | 46 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 63 insertions(+)
>
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 021376c2d260..bb373db0ba10 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -27,6 +27,7 @@
>
> #include "hw/ppc/ppc.h"
> #include "exec/memory.h"
> +#include "hw/sysbus.h"
>
> /* PowerPC 4xx core initialization */
> void ppc4xx_reset(void *opaque);
> @@ -50,4 +51,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
>
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
> +/*
> + * Generic DCR device
> + */
> +#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr"
Should it be named ppc4xx-dcr-device for clarity? This probably won't
appear anywhere where users have to type it.
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
> +struct Ppc4xxDcrDeviceState {
> + SysBusDevice parent_obj;
> +
> + PowerPCCPU *cpu;
> +};
> +
> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
> + dcr_read_cb dcr_read, dcr_write_cb dcr_write);
> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
> + Error **errp);
> +
> #endif /* PPC4XX_H */
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index f20098cf417c..e07bdba0f912 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -696,3 +696,49 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> mal, &dcr_read_mal, &dcr_write_mal);
> }
> }
> +
> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
> + dcr_read_cb dcr_read, dcr_write_cb dcr_write)
> +{
> + CPUPPCState *env;
> +
> + assert(dev->cpu);
> +
> + env = &dev->cpu->env;
> +
> + ppc_dcr_register(env, dcrn, dev, dcr_read, dcr_write);
> +}
> +
> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
> + Error **errp)
> +{
> + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
> + return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
> +}
> +
> +
> +static Property ppc4xx_dcr_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->user_creatable = false;
Should this be .abstract instead? We expect this to not be used directly
but only via SoC devices which is what abstract is for AFAIK.
> + device_class_set_props(dc, ppc4xx_dcr_properties);
> +}
> +
> +static const TypeInfo ppc4xx_types[] = {
> + {
> + .name = TYPE_PPC4xx_DCR_DEVICE,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc4xxDcrDeviceState),
> + .class_init = ppc4xx_dcr_class_init,
> + .abstract = true,
Oh, it's abstract already. So does it also need user_creatable for an
abstract class then? Maybe you can drop the user_creatable.
Regards,
BALATON Zoltan
> + }
> +};
> +
> +DEFINE_TYPES(ppc4xx_types)
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model
2022-08-08 13:29 ` BALATON Zoltan
@ 2022-08-08 15:35 ` Cédric Le Goater
0 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 15:35 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 15:29, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> The Device Control Registers (DCR) of on-SoC devices are accessed by
>> software through the use of the mtdcr and mfdcr instructions. These
>> are converted in transactions on a side band bus, the DCR bus, which
>> connects the on-SoC devices to the CPU.
>>
>> Ideally, we should model these accesses with a DCR namespace and DCR
>> memory regions but today the DCR handlers are installed in a DCR table
>> under the CPU. Instead introduce a little device model wrapper to hold
>> a CPU link and handle registration of DCR handlers.
>>
>> The DCR device inherits from SysBus because most of these devices also
>> have a MMIO regions and/or IRQs. Being a SysBusDevice makes things
>
> Drop "a", just "MMIO regions" due to plural. Also "makes it easier to install" or "makes things easier".
>
>> easier to install the device model in the overall SoC.
>>
>> The "cpu" link should be considered as modeling the piece of HW logic
>> connecting the device to the DCR bus.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/ppc/ppc4xx.h | 17 +++++++++++++++
>> hw/ppc/ppc4xx_devs.c | 46 +++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 63 insertions(+)
>>
>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>> index 021376c2d260..bb373db0ba10 100644
>> --- a/include/hw/ppc/ppc4xx.h
>> +++ b/include/hw/ppc/ppc4xx.h
>> @@ -27,6 +27,7 @@
>>
>> #include "hw/ppc/ppc.h"
>> #include "exec/memory.h"
>> +#include "hw/sysbus.h"
>>
>> /* PowerPC 4xx core initialization */
>> void ppc4xx_reset(void *opaque);
>> @@ -50,4 +51,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
>>
>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>
>> +/*
>> + * Generic DCR device
>> + */
>> +#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr"
>
> Should it be named ppc4xx-dcr-device for clarity? This probably won't appear anywhere where users have to type it.
ok.
>
>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
>> +struct Ppc4xxDcrDeviceState {
>> + SysBusDevice parent_obj;
>> +
>> + PowerPCCPU *cpu;
>> +};
>> +
>> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
>> + dcr_read_cb dcr_read, dcr_write_cb dcr_write);
>> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>> + Error **errp);
>> +
>> #endif /* PPC4XX_H */
>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>> index f20098cf417c..e07bdba0f912 100644
>> --- a/hw/ppc/ppc4xx_devs.c
>> +++ b/hw/ppc/ppc4xx_devs.c
>> @@ -696,3 +696,49 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
>> mal, &dcr_read_mal, &dcr_write_mal);
>> }
>> }
>> +
>> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
>> + dcr_read_cb dcr_read, dcr_write_cb dcr_write)
>> +{
>> + CPUPPCState *env;
>> +
>> + assert(dev->cpu);
>> +
>> + env = &dev->cpu->env;
>> +
>> + ppc_dcr_register(env, dcrn, dev, dcr_read, dcr_write);
>> +}
>> +
>> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>> + Error **errp)
>> +{
>> + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
>> + return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
>> +}
>> +
>> +
>> +static Property ppc4xx_dcr_properties[] = {
>> + DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
>> + PowerPCCPU *),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + dc->user_creatable = false;
>
> Should this be .abstract instead? We expect this to not be used directly but only via SoC devices which is what abstract is for AFAIK.
>
>
>> + device_class_set_props(dc, ppc4xx_dcr_properties);
>> +}
>> +
>> +static const TypeInfo ppc4xx_types[] = {
>> + {
>> + .name = TYPE_PPC4xx_DCR_DEVICE,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(Ppc4xxDcrDeviceState),
>> + .class_init = ppc4xx_dcr_class_init,
>> + .abstract = true,
>
> Oh, it's abstract already. So does it also need user_creatable for an abstract class then? Maybe you can drop the user_creatable.
Indeed.
Thanks,
C.
> Regards,
> BALATON Zoltan
>
>> + }
>> +};
>> +
>> +DEFINE_TYPES(ppc4xx_types)
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 09/22] ppc/ppc405: QOM'ify CPC
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (7 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 14:12 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 10/22] ppc/ppc405: QOM'ify GPT Cédric Le Goater
` (13 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The OCM controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 35 ++++++++++++-
hw/ppc/ppc405_uc.c | 122 +++++++++++++++++++--------------------------
2 files changed, 86 insertions(+), 71 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 8cc76cc8b3fe..2ba829988de2 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,39 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_CPC "ppc405-cpc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
+
+enum {
+ PPC405EP_CPU_CLK = 0,
+ PPC405EP_PLB_CLK = 1,
+ PPC405EP_OPB_CLK = 2,
+ PPC405EP_EBC_CLK = 3,
+ PPC405EP_MAL_CLK = 4,
+ PPC405EP_PCI_CLK = 5,
+ PPC405EP_UART0_CLK = 6,
+ PPC405EP_UART1_CLK = 7,
+ PPC405EP_CLK_NB = 8,
+};
+
+struct Ppc405CpcState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t sysclk;
+ clk_setup_t clk_setup[PPC405EP_CLK_NB];
+ uint32_t boot;
+ uint32_t epctl;
+ uint32_t pllmr[2];
+ uint32_t ucr;
+ uint32_t srr;
+ uint32_t jtagid;
+ uint32_t pci;
+ /* Clock and power management */
+ uint32_t er;
+ uint32_t fr;
+ uint32_t sr;
+};
+
#define TYPE_PPC405_SOC "ppc405-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
@@ -78,9 +111,9 @@ struct Ppc405SoCState {
MemoryRegion *dram_mr;
hwaddr ram_size;
- uint32_t sysclk;
PowerPCCPU cpu;
DeviceState *uic;
+ Ppc405CpcState cpc;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index fa3853df2233..e45535b8e52a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1178,36 +1178,7 @@ enum {
#endif
};
-enum {
- PPC405EP_CPU_CLK = 0,
- PPC405EP_PLB_CLK = 1,
- PPC405EP_OPB_CLK = 2,
- PPC405EP_EBC_CLK = 3,
- PPC405EP_MAL_CLK = 4,
- PPC405EP_PCI_CLK = 5,
- PPC405EP_UART0_CLK = 6,
- PPC405EP_UART1_CLK = 7,
- PPC405EP_CLK_NB = 8,
-};
-
-typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
-struct ppc405ep_cpc_t {
- uint32_t sysclk;
- clk_setup_t clk_setup[PPC405EP_CLK_NB];
- uint32_t boot;
- uint32_t epctl;
- uint32_t pllmr[2];
- uint32_t ucr;
- uint32_t srr;
- uint32_t jtagid;
- uint32_t pci;
- /* Clock and power management */
- uint32_t er;
- uint32_t fr;
- uint32_t sr;
-};
-
-static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
+static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
{
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
uint32_t UART0_clk, UART1_clk;
@@ -1302,10 +1273,9 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = PPC405_CPC(opaque);
uint32_t ret;
- cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
ret = cpc->boot;
@@ -1342,9 +1312,8 @@ static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = PPC405_CPC(opaque);
- cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
/* Read-only register */
@@ -1377,9 +1346,9 @@ static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc405ep_cpc_reset (void *opaque)
+static void ppc405_cpc_reset(DeviceState *opaque)
{
- ppc405ep_cpc_t *cpc = opaque;
+ Ppc405CpcState *cpc = PPC405_CPC(opaque);
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
cpc->epctl = 0x00000000;
@@ -1391,45 +1360,56 @@ static void ppc405ep_cpc_reset (void *opaque)
cpc->er = 0x00000000;
cpc->fr = 0x00000000;
cpc->sr = 0x00000000;
+ cpc->jtagid = 0x20267049;
ppc405ep_compute_clocks(cpc);
}
/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
- uint32_t sysclk)
+static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = PPC405_CPC(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+ CPUPPCState *env;
- cpc = g_new0(ppc405ep_cpc_t, 1);
- memcpy(cpc->clk_setup, clk_setup,
- PPC405EP_CLK_NB * sizeof(clk_setup_t));
- cpc->jtagid = 0x20267049;
- cpc->sysclk = sysclk;
- qemu_register_reset(&ppc405ep_cpc_reset, cpc);
- ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
+ assert(dcr->cpu);
+
+ env = &dcr->cpu->env;
+
+ cpc->clk_setup[PPC405EP_CPU_CLK].cb =
+ ppc_40x_timers_init(env, cpc->sysclk, PPC_INTERRUPT_PIT);
+ cpc->clk_setup[PPC405EP_CPU_CLK].opaque = env;
+
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT,
&dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL,
&dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0,
&dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1,
&dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR,
&dcr_read_epcpc, &dcr_write_epcpc);
-#if 0
- ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR,
&dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID,
&dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI,
&dcr_read_epcpc, &dcr_write_epcpc);
-#endif
+}
+
+static Property ppc405_cpc_properties[] = {
+ DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_cpc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_cpc_realize;
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc405_cpc_properties);
+ dc->reset = ppc405_cpc_reset;
}
static void ppc405_soc_instance_init(Object *obj)
@@ -1438,17 +1418,17 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpu", &s->cpu,
POWERPC_CPU_TYPE_NAME("405ep"));
+
+ object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
+ object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- clk_setup_t clk_setup[PPC405EP_CLK_NB];
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUPPCState *env;
- memset(clk_setup, 0, sizeof(clk_setup));
-
/* init CPUs */
if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
return;
@@ -1457,14 +1437,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
env = &s->cpu.env;
- clk_setup[PPC405EP_CPU_CLK].cb =
- ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
- clk_setup[PPC405EP_CPU_CLK].opaque = env;
-
ppc_dcr_init(env, NULL, NULL);
/* CPU control */
- ppc405ep_cpc_init(env, clk_setup, s->sysclk);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) {
+ return;
+ }
/* PLB arbitrer */
ppc4xx_plb_init(env);
@@ -1556,7 +1534,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
@@ -1573,6 +1550,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_CPC,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405CpcState),
+ .class_init = ppc405_cpc_class_init,
+ }, {
.name = TYPE_PPC405_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405SoCState),
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 09/22] ppc/ppc405: QOM'ify CPC
2022-08-08 10:27 ` [PATCH v3 09/22] ppc/ppc405: QOM'ify CPC Cédric Le Goater
@ 2022-08-08 14:12 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:12 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 10636 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> The OCM controller is currently modeled as a DCR device.
What's OCM? Did you mean CPC?
> Now that all clock settings are handled at the CPC level, change the
> SoC "sys-clk" property to be an alias on the same property in the CPC
> model.
>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 35 ++++++++++++-
> hw/ppc/ppc405_uc.c | 122 +++++++++++++++++++--------------------------
> 2 files changed, 86 insertions(+), 71 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 8cc76cc8b3fe..2ba829988de2 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -63,6 +63,39 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> +#define TYPE_PPC405_CPC "ppc405-cpc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
> +
> +enum {
> + PPC405EP_CPU_CLK = 0,
> + PPC405EP_PLB_CLK = 1,
> + PPC405EP_OPB_CLK = 2,
> + PPC405EP_EBC_CLK = 3,
> + PPC405EP_MAL_CLK = 4,
> + PPC405EP_PCI_CLK = 5,
> + PPC405EP_UART0_CLK = 6,
> + PPC405EP_UART1_CLK = 7,
> + PPC405EP_CLK_NB = 8,
> +};
> +
> +struct Ppc405CpcState {
> + Ppc4xxDcrDeviceState parent_obj;
> +
> + uint32_t sysclk;
> + clk_setup_t clk_setup[PPC405EP_CLK_NB];
> + uint32_t boot;
> + uint32_t epctl;
> + uint32_t pllmr[2];
> + uint32_t ucr;
> + uint32_t srr;
> + uint32_t jtagid;
> + uint32_t pci;
> + /* Clock and power management */
> + uint32_t er;
> + uint32_t fr;
> + uint32_t sr;
> +};
> +
> #define TYPE_PPC405_SOC "ppc405-soc"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
>
> @@ -78,9 +111,9 @@ struct Ppc405SoCState {
> MemoryRegion *dram_mr;
> hwaddr ram_size;
>
> - uint32_t sysclk;
> PowerPCCPU cpu;
> DeviceState *uic;
> + Ppc405CpcState cpc;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index fa3853df2233..e45535b8e52a 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1178,36 +1178,7 @@ enum {
> #endif
> };
>
> -enum {
> - PPC405EP_CPU_CLK = 0,
> - PPC405EP_PLB_CLK = 1,
> - PPC405EP_OPB_CLK = 2,
> - PPC405EP_EBC_CLK = 3,
> - PPC405EP_MAL_CLK = 4,
> - PPC405EP_PCI_CLK = 5,
> - PPC405EP_UART0_CLK = 6,
> - PPC405EP_UART1_CLK = 7,
> - PPC405EP_CLK_NB = 8,
> -};
> -
> -typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
> -struct ppc405ep_cpc_t {
> - uint32_t sysclk;
> - clk_setup_t clk_setup[PPC405EP_CLK_NB];
> - uint32_t boot;
> - uint32_t epctl;
> - uint32_t pllmr[2];
> - uint32_t ucr;
> - uint32_t srr;
> - uint32_t jtagid;
> - uint32_t pci;
> - /* Clock and power management */
> - uint32_t er;
> - uint32_t fr;
> - uint32_t sr;
> -};
> -
> -static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
> +static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
> {
> uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
> uint32_t UART0_clk, UART1_clk;
> @@ -1302,10 +1273,9 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
>
> static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
> {
> - ppc405ep_cpc_t *cpc;
> + Ppc405CpcState *cpc = PPC405_CPC(opaque);
I still think that these callbacks that are registered by the realize
method with an already checked opaque pointer don't need to check it again
here so I'd drop the QOM casts from all these callbacks and assign opaque
directly. Only cast where needed (you're passed a DeviceState, wtc.). But
now that you've introduced ppc4xx_dcr_register it is passed a DcrDevice as
it registers the callbacks with itself. That's wrong, the scr callbacks
could have any opaque data so ppc4xx_dcr_register() should have an opaque
argument (where you pass cpc uin this patch) then drop these casts. Same
for all later patches.
> uint32_t ret;
>
> - cpc = opaque;
> switch (dcrn) {
> case PPC405EP_CPC0_BOOT:
> ret = cpc->boot;
> @@ -1342,9 +1312,8 @@ static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
>
> static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
> {
> - ppc405ep_cpc_t *cpc;
> + Ppc405CpcState *cpc = PPC405_CPC(opaque);
>
> - cpc = opaque;
> switch (dcrn) {
> case PPC405EP_CPC0_BOOT:
> /* Read-only register */
> @@ -1377,9 +1346,9 @@ static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -static void ppc405ep_cpc_reset (void *opaque)
> +static void ppc405_cpc_reset(DeviceState *opaque)
> {
> - ppc405ep_cpc_t *cpc = opaque;
> + Ppc405CpcState *cpc = PPC405_CPC(opaque);
>
> cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
> cpc->epctl = 0x00000000;
> @@ -1391,45 +1360,56 @@ static void ppc405ep_cpc_reset (void *opaque)
> cpc->er = 0x00000000;
> cpc->fr = 0x00000000;
> cpc->sr = 0x00000000;
> + cpc->jtagid = 0x20267049;
> ppc405ep_compute_clocks(cpc);
> }
>
> /* XXX: sysclk should be between 25 and 100 MHz */
> -static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
> - uint32_t sysclk)
> +static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
> {
> - ppc405ep_cpc_t *cpc;
> + Ppc405CpcState *cpc = PPC405_CPC(dev);
> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
Only these casts are enough to check the object as it's only passed on
from this point.
> + CPUPPCState *env;
>
> - cpc = g_new0(ppc405ep_cpc_t, 1);
> - memcpy(cpc->clk_setup, clk_setup,
> - PPC405EP_CLK_NB * sizeof(clk_setup_t));
> - cpc->jtagid = 0x20267049;
> - cpc->sysclk = sysclk;
> - qemu_register_reset(&ppc405ep_cpc_reset, cpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
> - &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
> - &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
> - &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
> + assert(dcr->cpu);
So if you move this to the end you can drop this assert. Also env may not
be needed any more now that it only apears twice.
Regards,
BALATON Zoltan
> +
> + env = &dcr->cpu->env;
> +
> + cpc->clk_setup[PPC405EP_CPU_CLK].cb =
> + ppc_40x_timers_init(env, cpc->sysclk, PPC_INTERRUPT_PIT);
> + cpc->clk_setup[PPC405EP_CPU_CLK].opaque = env;
> +
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT,
> &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL,
> &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0,
> &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1,
> &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR,
> &dcr_read_epcpc, &dcr_write_epcpc);
> -#if 0
> - ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR,
> &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID,
> &dcr_read_epcpc, &dcr_write_epcpc);
> - ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
> + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI,
> &dcr_read_epcpc, &dcr_write_epcpc);
> -#endif
> +}
> +
> +static Property ppc405_cpc_properties[] = {
> + DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_cpc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_cpc_realize;
> + dc->user_creatable = false;
> + device_class_set_props(dc, ppc405_cpc_properties);
> + dc->reset = ppc405_cpc_reset;
> }
>
> static void ppc405_soc_instance_init(Object *obj)
> @@ -1438,17 +1418,17 @@ static void ppc405_soc_instance_init(Object *obj)
>
> object_initialize_child(obj, "cpu", &s->cpu,
> POWERPC_CPU_TYPE_NAME("405ep"));
> +
> + object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
> + object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - clk_setup_t clk_setup[PPC405EP_CLK_NB];
> qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> CPUPPCState *env;
>
> - memset(clk_setup, 0, sizeof(clk_setup));
> -
> /* init CPUs */
> if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
> return;
> @@ -1457,14 +1437,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> env = &s->cpu.env;
>
> - clk_setup[PPC405EP_CPU_CLK].cb =
> - ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
> - clk_setup[PPC405EP_CPU_CLK].opaque = env;
> -
> ppc_dcr_init(env, NULL, NULL);
>
> /* CPU control */
> - ppc405ep_cpc_init(env, clk_setup, s->sysclk);
> + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) {
> + return;
> + }
>
> /* PLB arbitrer */
> ppc4xx_plb_init(env);
> @@ -1556,7 +1534,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> static Property ppc405_soc_properties[] = {
> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> MemoryRegion *),
> - DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
> DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> DEFINE_PROP_END_OF_LIST(),
> @@ -1573,6 +1550,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_CPC,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc405CpcState),
> + .class_init = ppc405_cpc_class_init,
> + }, {
> .name = TYPE_PPC405_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(Ppc405SoCState),
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 10/22] ppc/ppc405: QOM'ify GPT
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (8 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 09/22] ppc/ppc405: QOM'ify CPC Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 14:25 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 11/22] ppc/ppc405: QOM'ify OCM Cédric Le Goater
` (12 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The GPT controller is currently modeled as a SysBus device with a
unique memory region, a couple of IRQs and a timer.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 22 ++++++++++++
hw/ppc/ppc405_uc.c | 90 +++++++++++++++++++++++-----------------------
2 files changed, 67 insertions(+), 45 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 2ba829988de2..bcf55e4f6b2e 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,27 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* General purpose timers */
+#define TYPE_PPC405_GPT "ppc405-gpt"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
+struct Ppc405GptState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ int64_t tb_offset;
+ uint32_t tb_freq;
+ QEMUTimer *timer;
+ qemu_irq irqs[5];
+ uint32_t oe;
+ uint32_t ol;
+ uint32_t im;
+ uint32_t is;
+ uint32_t ie;
+ uint32_t comp[5];
+ uint32_t mask[5];
+};
+
#define TYPE_PPC405_CPC "ppc405-cpc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
@@ -114,6 +135,7 @@ struct Ppc405SoCState {
PowerPCCPU cpu;
DeviceState *uic;
Ppc405CpcState cpc;
+ Ppc405GptState gpt;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e45535b8e52a..f64e661eef6c 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env)
/*****************************************************************************/
/* General purpose timers */
-typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
-struct ppc4xx_gpt_t {
- MemoryRegion iomem;
- int64_t tb_offset;
- uint32_t tb_freq;
- QEMUTimer *timer;
- qemu_irq irqs[5];
- uint32_t oe;
- uint32_t ol;
- uint32_t im;
- uint32_t is;
- uint32_t ie;
- uint32_t comp[5];
- uint32_t mask[5];
-};
-
-static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
+static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
{
/* XXX: TODO */
return 0;
}
-static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
+static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
{
/* XXX: TODO */
}
-static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
{
/* XXX: TODO */
}
static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_gpt_t *gpt = opaque;
+ Ppc405GptState *gpt = PPC405_GPT(opaque);
uint32_t ret;
int idx;
@@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_gpt_t *gpt = opaque;
+ Ppc405GptState *gpt = PPC405_GPT(opaque);
int idx;
trace_ppc4xx_gpt_write(addr, size, value);
@@ -1116,20 +1100,18 @@ static const MemoryRegionOps gpt_ops = {
static void ppc4xx_gpt_cb (void *opaque)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *gpt = PPC405_GPT(opaque);
- gpt = opaque;
ppc4xx_gpt_set_irqs(gpt);
ppc4xx_gpt_set_outputs(gpt);
ppc4xx_gpt_compute_timer(gpt);
}
-static void ppc4xx_gpt_reset (void *opaque)
+static void ppc405_gpt_reset(DeviceState *dev)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *gpt = PPC405_GPT(dev);
int i;
- gpt = opaque;
timer_del(gpt->timer);
gpt->oe = 0x00000000;
gpt->ol = 0x00000000;
@@ -1142,21 +1124,28 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
-static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
+static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *s = PPC405_GPT(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
- trace_ppc4xx_gpt_init(base);
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
+ memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0x0d4);
+ sysbus_init_mmio(sbd, &s->iomem);
- gpt = g_new0(ppc4xx_gpt_t, 1);
- for (i = 0; i < 5; i++) {
- gpt->irqs[i] = irqs[i];
+ for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
+ sysbus_init_irq(sbd, &s->irqs[i]);
}
- gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
- memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
- memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
- qemu_register_reset(ppc4xx_gpt_reset, gpt);
+}
+
+static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_gpt_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_gpt_reset;
}
/*****************************************************************************/
@@ -1421,13 +1410,16 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
+
+ object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
+ qemu_irq dma_irqs[4], mal_irqs[4];
CPUPPCState *env;
+ int i;
/* init CPUs */
if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
@@ -1513,12 +1505,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc405_ocm_init(env);
/* GPT */
- gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
- gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
- gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
- gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
- gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
- ppc4xx_gpt_init(0xef600000, gpt_irqs);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, 0xef600000);
+
+ for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
+ qdev_get_gpio_in(s->uic, 19 + i));
+ }
/* MAL */
mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
@@ -1550,6 +1545,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_GPT,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405GptState),
+ .class_init = ppc405_gpt_class_init,
+ }, {
.name = TYPE_PPC405_CPC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405CpcState),
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 10/22] ppc/ppc405: QOM'ify GPT
2022-08-08 10:27 ` [PATCH v3 10/22] ppc/ppc405: QOM'ify GPT Cédric Le Goater
@ 2022-08-08 14:25 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:25 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 7959 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> The GPT controller is currently modeled as a SysBus device with a
> unique memory region, a couple of IRQs and a timer.
>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 22 ++++++++++++
> hw/ppc/ppc405_uc.c | 90 +++++++++++++++++++++++-----------------------
> 2 files changed, 67 insertions(+), 45 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 2ba829988de2..bcf55e4f6b2e 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -63,6 +63,27 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> +/* General purpose timers */
> +#define TYPE_PPC405_GPT "ppc405-gpt"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
> +struct Ppc405GptState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +
> + int64_t tb_offset;
> + uint32_t tb_freq;
> + QEMUTimer *timer;
> + qemu_irq irqs[5];
> + uint32_t oe;
> + uint32_t ol;
> + uint32_t im;
> + uint32_t is;
> + uint32_t ie;
> + uint32_t comp[5];
> + uint32_t mask[5];
> +};
> +
> #define TYPE_PPC405_CPC "ppc405-cpc"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
>
> @@ -114,6 +135,7 @@ struct Ppc405SoCState {
> PowerPCCPU cpu;
> DeviceState *uic;
> Ppc405CpcState cpc;
> + Ppc405GptState gpt;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index e45535b8e52a..f64e661eef6c 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env)
>
> /*****************************************************************************/
> /* General purpose timers */
> -typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
> -struct ppc4xx_gpt_t {
> - MemoryRegion iomem;
> - int64_t tb_offset;
> - uint32_t tb_freq;
> - QEMUTimer *timer;
> - qemu_irq irqs[5];
> - uint32_t oe;
> - uint32_t ol;
> - uint32_t im;
> - uint32_t is;
> - uint32_t ie;
> - uint32_t comp[5];
> - uint32_t mask[5];
> -};
> -
> -static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
> +static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
> {
> /* XXX: TODO */
> return 0;
> }
>
> -static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
> +static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
> {
> /* XXX: TODO */
> }
>
> -static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
> +static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
> {
> uint32_t mask;
> int i;
> @@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
> }
> }
>
> -static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
> +static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
> {
> uint32_t mask;
> int i;
> @@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
> }
> }
>
> -static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
> +static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
> {
> /* XXX: TODO */
> }
>
> static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
> {
> - ppc4xx_gpt_t *gpt = opaque;
> + Ppc405GptState *gpt = PPC405_GPT(opaque);
> uint32_t ret;
> int idx;
>
> @@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
> static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
> unsigned size)
> {
> - ppc4xx_gpt_t *gpt = opaque;
> + Ppc405GptState *gpt = PPC405_GPT(opaque);
> int idx;
>
> trace_ppc4xx_gpt_write(addr, size, value);
> @@ -1116,20 +1100,18 @@ static const MemoryRegionOps gpt_ops = {
>
> static void ppc4xx_gpt_cb (void *opaque)
> {
> - ppc4xx_gpt_t *gpt;
> + Ppc405GptState *gpt = PPC405_GPT(opaque);
>
> - gpt = opaque;
> ppc4xx_gpt_set_irqs(gpt);
> ppc4xx_gpt_set_outputs(gpt);
> ppc4xx_gpt_compute_timer(gpt);
> }
>
> -static void ppc4xx_gpt_reset (void *opaque)
> +static void ppc405_gpt_reset(DeviceState *dev)
> {
> - ppc4xx_gpt_t *gpt;
> + Ppc405GptState *gpt = PPC405_GPT(dev);
> int i;
>
> - gpt = opaque;
> timer_del(gpt->timer);
> gpt->oe = 0x00000000;
> gpt->ol = 0x00000000;
> @@ -1142,21 +1124,28 @@ static void ppc4xx_gpt_reset (void *opaque)
> }
> }
>
> -static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
> +static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_gpt_t *gpt;
> + Ppc405GptState *s = PPC405_GPT(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> int i;
>
> - trace_ppc4xx_gpt_init(base);
Where has this trace gone? If you've dropped it then you should also drop
it from trace-events.
> + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
> + memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0x0d4);
> + sysbus_init_mmio(sbd, &s->iomem);
>
> - gpt = g_new0(ppc4xx_gpt_t, 1);
> - for (i = 0; i < 5; i++) {
> - gpt->irqs[i] = irqs[i];
> + for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
> + sysbus_init_irq(sbd, &s->irqs[i]);
> }
> - gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
> - memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
> - memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
> - qemu_register_reset(ppc4xx_gpt_reset, gpt);
> +}
> +
> +static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_gpt_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_gpt_reset;
> }
>
> /*****************************************************************************/
> @@ -1421,13 +1410,16 @@ static void ppc405_soc_instance_init(Object *obj)
>
> object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
> object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
> +
> + object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
> + qemu_irq dma_irqs[4], mal_irqs[4];
> CPUPPCState *env;
> + int i;
>
> /* init CPUs */
> if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
> @@ -1513,12 +1505,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> ppc405_ocm_init(env);
>
> /* GPT */
> - gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
> - gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
> - gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
> - gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
> - gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
> - ppc4xx_gpt_init(0xef600000, gpt_irqs);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, 0xef600000);
> +
> + for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
> + qdev_get_gpio_in(s->uic, 19 + i));
Maybe you should have a SysBusDevice *sbd local here and cast only once if
you need it several times. It's also more readable that way.
Regards,
BALATON Zoltan
> + }
>
> /* MAL */
> mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
> @@ -1550,6 +1545,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_GPT,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405GptState),
> + .class_init = ppc405_gpt_class_init,
> + }, {
> .name = TYPE_PPC405_CPC,
> .parent = TYPE_PPC4xx_DCR_DEVICE,
> .instance_size = sizeof(Ppc405CpcState),
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 11/22] ppc/ppc405: QOM'ify OCM
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (9 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 10/22] ppc/ppc405: QOM'ify GPT Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
` (11 subsequent siblings)
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 16 +++++++++++
hw/ppc/ppc405_uc.c | 72 +++++++++++++++++++++++-----------------------
2 files changed, 52 insertions(+), 36 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index bcf55e4f6b2e..a5b493d3e7bf 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* On Chip Memory */
+#define TYPE_PPC405_OCM "ppc405-ocm"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
+struct Ppc405OcmState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion ram;
+ MemoryRegion isarc_ram;
+ MemoryRegion dsarc_ram;
+ uint32_t isarc;
+ uint32_t isacntl;
+ uint32_t dsarc;
+ uint32_t dsacntl;
+};
+
/* General purpose timers */
#define TYPE_PPC405_GPT "ppc405-gpt"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
@@ -136,6 +151,7 @@ struct Ppc405SoCState {
DeviceState *uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
+ Ppc405OcmState ocm;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index f64e661eef6c..961a7c851d4a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -773,20 +773,9 @@ enum {
OCM0_DSACNTL = 0x01B,
};
-typedef struct ppc405_ocm_t ppc405_ocm_t;
-struct ppc405_ocm_t {
- MemoryRegion ram;
- MemoryRegion isarc_ram;
- MemoryRegion dsarc_ram;
- uint32_t isarc;
- uint32_t isacntl;
- uint32_t dsarc;
- uint32_t dsacntl;
-};
-
-static void ocm_update_mappings (ppc405_ocm_t *ocm,
- uint32_t isarc, uint32_t isacntl,
- uint32_t dsarc, uint32_t dsacntl)
+static void ocm_update_mappings(Ppc405OcmState *ocm,
+ uint32_t isarc, uint32_t isacntl,
+ uint32_t dsarc, uint32_t dsacntl)
{
trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
ocm->isacntl, ocm->dsarc, ocm->dsacntl);
@@ -830,10 +819,9 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
static uint32_t dcr_read_ocm (void *opaque, int dcrn)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(opaque);
uint32_t ret;
- ocm = opaque;
switch (dcrn) {
case OCM0_ISARC:
ret = ocm->isarc;
@@ -857,10 +845,9 @@ static uint32_t dcr_read_ocm (void *opaque, int dcrn)
static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(opaque);
uint32_t isarc, dsarc, isacntl, dsacntl;
- ocm = opaque;
isarc = ocm->isarc;
dsarc = ocm->dsarc;
isacntl = ocm->isacntl;
@@ -886,12 +873,11 @@ static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
ocm->dsacntl = dsacntl;
}
-static void ocm_reset (void *opaque)
+static void ppc405_ocm_reset(DeviceState *dev)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(dev);
uint32_t isarc, dsarc, isacntl, dsacntl;
- ocm = opaque;
isarc = 0x00000000;
isacntl = 0x00000000;
dsarc = 0x00000000;
@@ -903,25 +889,30 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
-static void ppc405_ocm_init(CPUPPCState *env)
+static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- ocm = g_new0(ppc405_ocm_t, 1);
/* XXX: Size is 4096 or 0x04000000 */
- memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
+ memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
&error_fatal);
- memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
+ memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
&ocm->isarc_ram, 0, 4 * KiB);
- qemu_register_reset(&ocm_reset, ocm);
- ppc_dcr_register(env, OCM0_ISARC,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc_dcr_register(env, OCM0_ISACNTL,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc_dcr_register(env, OCM0_DSARC,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc_dcr_register(env, OCM0_DSACNTL,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
+
+ ppc4xx_dcr_register(dcr, OCM0_ISARC, &dcr_read_ocm, &dcr_write_ocm);
+ ppc4xx_dcr_register(dcr, OCM0_ISACNTL, &dcr_read_ocm, &dcr_write_ocm);
+ ppc4xx_dcr_register(dcr, OCM0_DSARC, &dcr_read_ocm, &dcr_write_ocm);
+ ppc4xx_dcr_register(dcr, OCM0_DSACNTL, &dcr_read_ocm, &dcr_write_ocm);
+}
+
+static void ppc405_ocm_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_ocm_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_ocm_reset;
}
/*****************************************************************************/
@@ -1412,6 +1403,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
+
+ object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1502,7 +1495,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* OCM */
- ppc405_ocm_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) {
+ return;
+ }
/* GPT */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
@@ -1545,6 +1540,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_OCM,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405OcmState),
+ .class_init = ppc405_ocm_class_init,
+ }, {
.name = TYPE_PPC405_GPT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GptState),
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (10 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 11/22] ppc/ppc405: QOM'ify OCM Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 14:32 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 13/22] ppc/ppc405: QOM'ify DMA Cédric Le Goater
` (10 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 21 +++++++++++++++++++
hw/ppc/ppc405_uc.c | 50 +++++++++++++++++++++-------------------------
2 files changed, 44 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index a5b493d3e7bf..21f6cb358501 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* GPIO */
+#define TYPE_PPC405_GPIO "ppc405-gpio"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
+struct Ppc405GpioState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion io;
+ uint32_t or;
+ uint32_t tcr;
+ uint32_t osrh;
+ uint32_t osrl;
+ uint32_t tsrh;
+ uint32_t tsrl;
+ uint32_t odr;
+ uint32_t ir;
+ uint32_t rr1;
+ uint32_t isr1h;
+ uint32_t isr1l;
+};
+
/* On Chip Memory */
#define TYPE_PPC405_OCM "ppc405-ocm"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
@@ -152,6 +172,7 @@ struct Ppc405SoCState {
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
+ Ppc405GpioState gpio;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 961a7c851d4a..768e6909a831 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -713,23 +713,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
}
/*****************************************************************************/
-/* GPIO */
-typedef struct ppc405_gpio_t ppc405_gpio_t;
-struct ppc405_gpio_t {
- MemoryRegion io;
- uint32_t or;
- uint32_t tcr;
- uint32_t osrh;
- uint32_t osrl;
- uint32_t tsrh;
- uint32_t tsrl;
- uint32_t odr;
- uint32_t ir;
- uint32_t rr1;
- uint32_t isr1h;
- uint32_t isr1l;
-};
-
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
trace_ppc405_gpio_read(addr, size);
@@ -748,20 +731,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc405_gpio_reset (void *opaque)
+static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
{
+ Ppc405GpioState *s = PPC405_GPIO(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
+ 0x038);
+ sysbus_init_mmio(sbd, &s->io);
}
-static void ppc405_gpio_init(hwaddr base)
+static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
{
- ppc405_gpio_t *gpio;
-
- trace_ppc405_gpio_init(base);
+ DeviceClass *dc = DEVICE_CLASS(oc);
- gpio = g_new0(ppc405_gpio_t, 1);
- memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
- memory_region_add_subregion(get_system_memory(), base, &gpio->io);
- qemu_register_reset(&ppc405_gpio_reset, gpio);
+ dc->realize = ppc405_gpio_realize;
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1405,6 +1390,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
+
+ object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1477,8 +1464,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
qdev_get_gpio_in(s->uic, 2));
+
/* GPIO */
- ppc405_gpio_init(0xef600700);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, 0xef600700);
/* Serial ports */
if (serial_hd(0) != NULL) {
@@ -1540,6 +1531,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405GpioState),
+ .class_init = ppc405_gpio_class_init,
+ }, {
.name = TYPE_PPC405_OCM,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405OcmState),
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO
2022-08-08 10:27 ` [PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
@ 2022-08-08 14:32 ` BALATON Zoltan
2022-08-08 14:50 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:32 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 4784 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> The GPIO controller is currently modeled as a simple SysBus device
> with a unique memory region.
>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 21 +++++++++++++++++++
> hw/ppc/ppc405_uc.c | 50 +++++++++++++++++++++-------------------------
> 2 files changed, 44 insertions(+), 27 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index a5b493d3e7bf..21f6cb358501 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> +/* GPIO */
> +#define TYPE_PPC405_GPIO "ppc405-gpio"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
> +struct Ppc405GpioState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion io;
> + uint32_t or;
> + uint32_t tcr;
> + uint32_t osrh;
> + uint32_t osrl;
> + uint32_t tsrh;
> + uint32_t tsrl;
> + uint32_t odr;
> + uint32_t ir;
> + uint32_t rr1;
> + uint32_t isr1h;
> + uint32_t isr1l;
> +};
> +
> /* On Chip Memory */
> #define TYPE_PPC405_OCM "ppc405-ocm"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
> @@ -152,6 +172,7 @@ struct Ppc405SoCState {
> Ppc405CpcState cpc;
> Ppc405GptState gpt;
> Ppc405OcmState ocm;
> + Ppc405GpioState gpio;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 961a7c851d4a..768e6909a831 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -713,23 +713,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
> }
>
> /*****************************************************************************/
> -/* GPIO */
> -typedef struct ppc405_gpio_t ppc405_gpio_t;
> -struct ppc405_gpio_t {
> - MemoryRegion io;
> - uint32_t or;
> - uint32_t tcr;
> - uint32_t osrh;
> - uint32_t osrl;
> - uint32_t tsrh;
> - uint32_t tsrl;
> - uint32_t odr;
> - uint32_t ir;
> - uint32_t rr1;
> - uint32_t isr1h;
> - uint32_t isr1l;
> -};
> -
> static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
> {
> trace_ppc405_gpio_read(addr, size);
> @@ -748,20 +731,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -static void ppc405_gpio_reset (void *opaque)
> +static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
> {
> + Ppc405GpioState *s = PPC405_GPIO(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
> + 0x038);
> + sysbus_init_mmio(sbd, &s->io);
> }
>
> -static void ppc405_gpio_init(hwaddr base)
> +static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
> {
> - ppc405_gpio_t *gpio;
> -
> - trace_ppc405_gpio_init(base);
Trace gone, update trace-events too.
> + DeviceClass *dc = DEVICE_CLASS(oc);
>
> - gpio = g_new0(ppc405_gpio_t, 1);
> - memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
> - memory_region_add_subregion(get_system_memory(), base, &gpio->io);
> - qemu_register_reset(&ppc405_gpio_reset, gpio);
> + dc->realize = ppc405_gpio_realize;
> + dc->user_creatable = false;
> }
>
> /*****************************************************************************/
> @@ -1405,6 +1390,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
>
> object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
> +
> + object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1477,8 +1464,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> qdev_get_gpio_in(s->uic, 2));
> +
> /* GPIO */
> - ppc405_gpio_init(0xef600700);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, 0xef600700);
>
> /* Serial ports */
> if (serial_hd(0) != NULL) {
> @@ -1540,6 +1531,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_GPIO,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405GpioState),
> + .class_init = ppc405_gpio_class_init,
> + }, {
> .name = TYPE_PPC405_OCM,
> .parent = TYPE_PPC4xx_DCR_DEVICE,
> .instance_size = sizeof(Ppc405OcmState),
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO
2022-08-08 14:32 ` BALATON Zoltan
@ 2022-08-08 14:50 ` Cédric Le Goater
0 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 14:50 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 16:32, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> The GPIO controller is currently modeled as a simple SysBus device
>> with a unique memory region.
>>
>> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h | 21 +++++++++++++++++++
>> hw/ppc/ppc405_uc.c | 50 +++++++++++++++++++++-------------------------
>> 2 files changed, 44 insertions(+), 27 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index a5b493d3e7bf..21f6cb358501 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t {
>> uint32_t bi_iic_fast[2];
>> };
>>
>> +/* GPIO */
>> +#define TYPE_PPC405_GPIO "ppc405-gpio"
>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
>> +struct Ppc405GpioState {
>> + SysBusDevice parent_obj;
>> +
>> + MemoryRegion io;
>> + uint32_t or;
>> + uint32_t tcr;
>> + uint32_t osrh;
>> + uint32_t osrl;
>> + uint32_t tsrh;
>> + uint32_t tsrl;
>> + uint32_t odr;
>> + uint32_t ir;
>> + uint32_t rr1;
>> + uint32_t isr1h;
>> + uint32_t isr1l;
>> +};
>> +
>> /* On Chip Memory */
>> #define TYPE_PPC405_OCM "ppc405-ocm"
>> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
>> @@ -152,6 +172,7 @@ struct Ppc405SoCState {
>> Ppc405CpcState cpc;
>> Ppc405GptState gpt;
>> Ppc405OcmState ocm;
>> + Ppc405GpioState gpio;
>> };
>>
>> /* PowerPC 405 core */
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index 961a7c851d4a..768e6909a831 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -713,23 +713,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
>> }
>>
>> /*****************************************************************************/
>> -/* GPIO */
>> -typedef struct ppc405_gpio_t ppc405_gpio_t;
>> -struct ppc405_gpio_t {
>> - MemoryRegion io;
>> - uint32_t or;
>> - uint32_t tcr;
>> - uint32_t osrh;
>> - uint32_t osrl;
>> - uint32_t tsrh;
>> - uint32_t tsrl;
>> - uint32_t odr;
>> - uint32_t ir;
>> - uint32_t rr1;
>> - uint32_t isr1h;
>> - uint32_t isr1l;
>> -};
>> -
>> static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
>> {
>> trace_ppc405_gpio_read(addr, size);
>> @@ -748,20 +731,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
>> .endianness = DEVICE_NATIVE_ENDIAN,
>> };
>>
>> -static void ppc405_gpio_reset (void *opaque)
>> +static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
>> {
>> + Ppc405GpioState *s = PPC405_GPIO(dev);
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
>> +
>> + memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
>> + 0x038);
>> + sysbus_init_mmio(sbd, &s->io);
>> }
>>
>> -static void ppc405_gpio_init(hwaddr base)
>> +static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
>> {
>> - ppc405_gpio_t *gpio;
>> -
>> - trace_ppc405_gpio_init(base);
>
> Trace gone, update trace-events too.
Yes. I have checked the others.
Thanks,
C.
>
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>>
>> - gpio = g_new0(ppc405_gpio_t, 1);
>> - memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
>> - memory_region_add_subregion(get_system_memory(), base, &gpio->io);
>> - qemu_register_reset(&ppc405_gpio_reset, gpio);
>> + dc->realize = ppc405_gpio_realize;
>> + dc->user_creatable = false;
>> }
>>
>> /*****************************************************************************/
>> @@ -1405,6 +1390,8 @@ static void ppc405_soc_instance_init(Object *obj)
>> object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
>>
>> object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
>> +
>> + object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
>> }
>>
>> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> @@ -1477,8 +1464,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>> /* I2C controller */
>> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
>> qdev_get_gpio_in(s->uic, 2));
>> +
>> /* GPIO */
>> - ppc405_gpio_init(0xef600700);
>> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
>> + return;
>> + }
>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, 0xef600700);
>>
>> /* Serial ports */
>> if (serial_hd(0) != NULL) {
>> @@ -1540,6 +1531,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>>
>> static const TypeInfo ppc405_types[] = {
>> {
>> + .name = TYPE_PPC405_GPIO,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(Ppc405GpioState),
>> + .class_init = ppc405_gpio_class_init,
>> + }, {
>> .name = TYPE_PPC405_OCM,
>> .parent = TYPE_PPC4xx_DCR_DEVICE,
>> .instance_size = sizeof(Ppc405OcmState),
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 13/22] ppc/ppc405: QOM'ify DMA
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (11 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 14:35 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 14/22] ppc/ppc405: QOM'ify EBC Cédric Le Goater
` (9 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The GPIO controller is currently modeled as a DCR device with a couple
of IRQs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 19 ++++++
hw/ppc/ppc405_uc.c | 141 ++++++++++++++++++++-------------------------
2 files changed, 81 insertions(+), 79 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 21f6cb358501..c75e4c7cb50a 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,24 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* DMA controller */
+#define TYPE_PPC405_DMA "ppc405-dma"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
+struct Ppc405DmaState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ qemu_irq irqs[4];
+ uint32_t cr[4];
+ uint32_t ct[4];
+ uint32_t da[4];
+ uint32_t sa[4];
+ uint32_t sg[4];
+ uint32_t sr;
+ uint32_t sgc;
+ uint32_t slp;
+ uint32_t pol;
+};
+
/* GPIO */
#define TYPE_PPC405_GPIO "ppc405-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
@@ -173,6 +191,7 @@ struct Ppc405SoCState {
Ppc405GptState gpt;
Ppc405OcmState ocm;
Ppc405GpioState gpio;
+ Ppc405DmaState dma;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 768e6909a831..49405e610dc1 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -613,35 +613,20 @@ enum {
DMA0_POL = 0x126,
};
-typedef struct ppc405_dma_t ppc405_dma_t;
-struct ppc405_dma_t {
- qemu_irq irqs[4];
- uint32_t cr[4];
- uint32_t ct[4];
- uint32_t da[4];
- uint32_t sa[4];
- uint32_t sg[4];
- uint32_t sr;
- uint32_t sgc;
- uint32_t slp;
- uint32_t pol;
-};
-
-static uint32_t dcr_read_dma (void *opaque, int dcrn)
+static uint32_t dcr_read_dma(void *opaque, int dcrn)
{
return 0;
}
-static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
{
}
-static void ppc405_dma_reset (void *opaque)
+static void ppc405_dma_reset(DeviceState *dev)
{
- ppc405_dma_t *dma;
+ Ppc405DmaState *dma = PPC405_DMA(dev);
int i;
- dma = opaque;
for (i = 0; i < 4; i++) {
dma->cr[i] = 0x00000000;
dma->ct[i] = 0x00000000;
@@ -655,61 +640,49 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
-static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
+static void ppc405_dma_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405DmaState *dma = PPC405_DMA(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]);
+ }
+
+ ppc4xx_dcr_register(dcr, DMA0_CR0, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT0, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA0, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA0, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG0, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CR1, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT1, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA1, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA1, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG1, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CR2, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT2, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA2, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA2, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG2, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CR3, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT3, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA3, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA3, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG3, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SR, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SGC, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SLP, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_POL, &dcr_read_dma, &dcr_write_dma);
+}
+
+static void ppc405_dma_class_init(ObjectClass *oc, void *data)
{
- ppc405_dma_t *dma;
-
- dma = g_new0(ppc405_dma_t, 1);
- memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
- qemu_register_reset(&ppc405_dma_reset, dma);
- ppc_dcr_register(env, DMA0_CR0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CR1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CR2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CR3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SR,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SGC,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SLP,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_POL,
- dma, &dcr_read_dma, &dcr_write_dma);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_dma_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_dma_reset;
}
/*****************************************************************************/
@@ -1392,12 +1365,14 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
+
+ object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq dma_irqs[4], mal_irqs[4];
+ qemu_irq mal_irqs[4];
CPUPPCState *env;
int i;
@@ -1455,11 +1430,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc405_ebc_init(env);
/* DMA controller */
- dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
- dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
- dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
- dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
- ppc405_dma_init(env, dma_irqs);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+ qdev_get_gpio_in(s->uic, 5 + i));
+ }
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
@@ -1531,6 +1509,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_DMA,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405DmaState),
+ .class_init = ppc405_dma_class_init,
+ }, {
.name = TYPE_PPC405_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GpioState),
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 13/22] ppc/ppc405: QOM'ify DMA
2022-08-08 10:27 ` [PATCH v3 13/22] ppc/ppc405: QOM'ify DMA Cédric Le Goater
@ 2022-08-08 14:35 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:35 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 9497 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> The GPIO controller is currently modeled as a DCR device with a couple
It's the DMA already not the GPIU.
Regards,
BALATON Zoltan
> of IRQs.
>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 19 ++++++
> hw/ppc/ppc405_uc.c | 141 ++++++++++++++++++++-------------------------
> 2 files changed, 81 insertions(+), 79 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 21f6cb358501..c75e4c7cb50a 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -63,6 +63,24 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> +/* DMA controller */
> +#define TYPE_PPC405_DMA "ppc405-dma"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
> +struct Ppc405DmaState {
> + Ppc4xxDcrDeviceState parent_obj;
> +
> + qemu_irq irqs[4];
> + uint32_t cr[4];
> + uint32_t ct[4];
> + uint32_t da[4];
> + uint32_t sa[4];
> + uint32_t sg[4];
> + uint32_t sr;
> + uint32_t sgc;
> + uint32_t slp;
> + uint32_t pol;
> +};
> +
> /* GPIO */
> #define TYPE_PPC405_GPIO "ppc405-gpio"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
> @@ -173,6 +191,7 @@ struct Ppc405SoCState {
> Ppc405GptState gpt;
> Ppc405OcmState ocm;
> Ppc405GpioState gpio;
> + Ppc405DmaState dma;
> };
>
> /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 768e6909a831..49405e610dc1 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -613,35 +613,20 @@ enum {
> DMA0_POL = 0x126,
> };
>
> -typedef struct ppc405_dma_t ppc405_dma_t;
> -struct ppc405_dma_t {
> - qemu_irq irqs[4];
> - uint32_t cr[4];
> - uint32_t ct[4];
> - uint32_t da[4];
> - uint32_t sa[4];
> - uint32_t sg[4];
> - uint32_t sr;
> - uint32_t sgc;
> - uint32_t slp;
> - uint32_t pol;
> -};
> -
> -static uint32_t dcr_read_dma (void *opaque, int dcrn)
> +static uint32_t dcr_read_dma(void *opaque, int dcrn)
> {
> return 0;
> }
>
> -static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
> +static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
> {
> }
>
> -static void ppc405_dma_reset (void *opaque)
> +static void ppc405_dma_reset(DeviceState *dev)
> {
> - ppc405_dma_t *dma;
> + Ppc405DmaState *dma = PPC405_DMA(dev);
> int i;
>
> - dma = opaque;
> for (i = 0; i < 4; i++) {
> dma->cr[i] = 0x00000000;
> dma->ct[i] = 0x00000000;
> @@ -655,61 +640,49 @@ static void ppc405_dma_reset (void *opaque)
> dma->pol = 0x00000000;
> }
>
> -static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
> +static void ppc405_dma_realize(DeviceState *dev, Error **errp)
> +{
> + Ppc405DmaState *dma = PPC405_DMA(dev);
> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]);
> + }
> +
> + ppc4xx_dcr_register(dcr, DMA0_CR0, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_CT0, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_DA0, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SA0, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SG0, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_CR1, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_CT1, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_DA1, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SA1, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SG1, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_CR2, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_CT2, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_DA2, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SA2, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SG2, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_CR3, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_CT3, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_DA3, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SA3, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SG3, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SR, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SGC, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_SLP, &dcr_read_dma, &dcr_write_dma);
> + ppc4xx_dcr_register(dcr, DMA0_POL, &dcr_read_dma, &dcr_write_dma);
> +}
> +
> +static void ppc405_dma_class_init(ObjectClass *oc, void *data)
> {
> - ppc405_dma_t *dma;
> -
> - dma = g_new0(ppc405_dma_t, 1);
> - memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
> - qemu_register_reset(&ppc405_dma_reset, dma);
> - ppc_dcr_register(env, DMA0_CR0,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_CT0,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_DA0,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SA0,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SG0,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_CR1,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_CT1,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_DA1,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SA1,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SG1,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_CR2,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_CT2,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_DA2,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SA2,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SG2,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_CR3,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_CT3,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_DA3,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SA3,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SG3,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SR,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SGC,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_SLP,
> - dma, &dcr_read_dma, &dcr_write_dma);
> - ppc_dcr_register(env, DMA0_POL,
> - dma, &dcr_read_dma, &dcr_write_dma);
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_dma_realize;
> + dc->user_creatable = false;
> + dc->reset = ppc405_dma_reset;
> }
>
> /*****************************************************************************/
> @@ -1392,12 +1365,14 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
>
> object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
> +
> + object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
> }
>
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - qemu_irq dma_irqs[4], mal_irqs[4];
> + qemu_irq mal_irqs[4];
> CPUPPCState *env;
> int i;
>
> @@ -1455,11 +1430,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> ppc405_ebc_init(env);
>
> /* DMA controller */
> - dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
> - dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
> - dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
> - dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
> - ppc405_dma_init(env, dma_irqs);
> + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
> + return;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> + qdev_get_gpio_in(s->uic, 5 + i));
> + }
>
> /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> @@ -1531,6 +1509,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> + .name = TYPE_PPC405_DMA,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc405DmaState),
> + .class_init = ppc405_dma_class_init,
> + }, {
> .name = TYPE_PPC405_GPIO,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc405GpioState),
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 14/22] ppc/ppc405: QOM'ify EBC
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (12 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 13/22] ppc/ppc405: QOM'ify DMA Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 15/22] ppc/ppc405: QOM'ify OPBA Cédric Le Goater
` (8 subsequent siblings)
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 17 +++++++++++++-
hw/ppc/ppc405_uc.c | 56 +++++++++++++++++++++++-----------------------
hw/ppc/sam460ex.c | 4 +++-
3 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c75e4c7cb50a..82bf8dae931f 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* Peripheral controller */
+#define TYPE_PPC405_EBC "ppc405-ebc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
+struct Ppc405EbcState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t addr;
+ uint32_t bcr[8];
+ uint32_t bap[8];
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+ uint32_t cfg;
+};
+
/* DMA controller */
#define TYPE_PPC405_DMA "ppc405-dma"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
@@ -192,12 +207,12 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+ Ppc405EbcState ebc;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
-void ppc405_ebc_init(CPUPPCState *env);
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 49405e610dc1..732b05156715 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -393,17 +393,6 @@ static void ppc4xx_opba_init(hwaddr base)
/*****************************************************************************/
/* Peripheral controller */
-typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
-struct ppc4xx_ebc_t {
- uint32_t addr;
- uint32_t bcr[8];
- uint32_t bap[8];
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
- uint32_t cfg;
-};
-
enum {
EBC0_CFGADDR = 0x012,
EBC0_CFGDATA = 0x013,
@@ -411,10 +400,9 @@ enum {
static uint32_t dcr_read_ebc (void *opaque, int dcrn)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(opaque);
uint32_t ret;
- ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ret = ebc->addr;
@@ -496,9 +484,8 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn)
static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(opaque);
- ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ebc->addr = val;
@@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
}
}
-static void ebc_reset (void *opaque)
+static void ppc405_ebc_reset(DeviceState *opaque)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(opaque);
int i;
- ebc = opaque;
ebc->addr = 0x00000000;
ebc->bap[0] = 0x7F8FFE80;
ebc->bcr[0] = 0xFFE28000;
@@ -572,16 +558,21 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
-void ppc405_ebc_init(CPUPPCState *env)
+static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
+{
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, EBC0_CFGADDR, &dcr_read_ebc, &dcr_write_ebc);
+ ppc4xx_dcr_register(dcr, EBC0_CFGDATA, &dcr_read_ebc, &dcr_write_ebc);
+}
+
+static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
{
- ppc4xx_ebc_t *ebc;
-
- ebc = g_new0(ppc4xx_ebc_t, 1);
- qemu_register_reset(&ebc_reset, ebc);
- ppc_dcr_register(env, EBC0_CFGADDR,
- ebc, &dcr_read_ebc, &dcr_write_ebc);
- ppc_dcr_register(env, EBC0_CFGDATA,
- ebc, &dcr_read_ebc, &dcr_write_ebc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_ebc_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_ebc_reset;
}
/*****************************************************************************/
@@ -1367,6 +1358,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
+
+ object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1427,7 +1420,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->do_dram_init);
/* External bus controller */
- ppc405_ebc_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
+ return;
+ }
/* DMA controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
@@ -1509,6 +1504,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_EBC,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405EbcState),
+ .class_init = ppc405_ebc_class_init,
+ }, {
.name = TYPE_PPC405_DMA,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405DmaState),
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 0357ee077f0c..320c61a7f36c 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -371,7 +371,9 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 3));
/* External bus controller */
- ppc405_ebc_init(env);
+ dev = qdev_new(TYPE_PPC405_EBC);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* CPR */
ppc4xx_cpr_init(env);
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 15/22] ppc/ppc405: QOM'ify OPBA
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (13 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 14/22] ppc/ppc405: QOM'ify EBC Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 16/22] ppc/ppc405: QOM'ify POB Cédric Le Goater
` (7 subsequent siblings)
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 12 ++++++++++++
hw/ppc/ppc405_uc.c | 47 +++++++++++++++++++++++++++-------------------
2 files changed, 40 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 82bf8dae931f..d63c2acdc7b5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* OPB arbitrer */
+#define TYPE_PPC405_OPBA "ppc405-opba"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
+struct Ppc405OpbaState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion io;
+ uint8_t cr;
+ uint8_t pr;
+};
+
/* Peripheral controller */
#define TYPE_PPC405_EBC "ppc405-ebc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
@@ -208,6 +219,7 @@ struct Ppc405SoCState {
Ppc405GpioState gpio;
Ppc405DmaState dma;
Ppc405EbcState ebc;
+ Ppc405OpbaState opba;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 732b05156715..d66db9b9c14a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -310,16 +310,10 @@ static void ppc4xx_pob_init(CPUPPCState *env)
/*****************************************************************************/
/* OPB arbitrer */
-typedef struct ppc4xx_opba_t ppc4xx_opba_t;
-struct ppc4xx_opba_t {
- MemoryRegion io;
- uint8_t cr;
- uint8_t pr;
-};
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_opba_t *opba = opaque;
+ Ppc405OpbaState *opba = PPC405_OPBA(opaque);
uint32_t ret;
switch (addr) {
@@ -341,7 +335,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_opba_t *opba = opaque;
+ Ppc405OpbaState *opba = PPC405_OPBA(opaque);
trace_opba_writeb(addr, value);
@@ -366,25 +360,30 @@ static const MemoryRegionOps opba_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ppc4xx_opba_reset (void *opaque)
+static void ppc405_opba_reset(DeviceState *dev)
{
- ppc4xx_opba_t *opba;
+ Ppc405OpbaState *opba = PPC405_OPBA(dev);
- opba = opaque;
opba->cr = 0x00; /* No dynamic priorities - park disabled */
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(hwaddr base)
+static void ppc405_opba_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_opba_t *opba;
+ Ppc405OpbaState *s = PPC405_OPBA(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- trace_opba_init(base);
+ memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 0x002);
+ sysbus_init_mmio(sbd, &s->io);
+}
+
+static void ppc405_opba_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
- opba = g_new0(ppc4xx_opba_t, 1);
- memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
- memory_region_add_subregion(get_system_memory(), base, &opba->io);
- qemu_register_reset(ppc4xx_opba_reset, opba);
+ dc->realize = ppc405_opba_realize;
+ dc->reset = ppc405_opba_reset;
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1360,6 +1359,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
+
+ object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1391,7 +1392,10 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_pob_init(env);
/* OBP arbitrer */
- ppc4xx_opba_init(0xef600600);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
@@ -1504,6 +1508,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_OPBA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405OpbaState),
+ .class_init = ppc405_opba_class_init,
+ }, {
.name = TYPE_PPC405_EBC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405EbcState),
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 16/22] ppc/ppc405: QOM'ify POB
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (14 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 15/22] ppc/ppc405: QOM'ify OPBA Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 17/22] ppc/ppc405: QOM'ify PLB Cédric Le Goater
` (6 subsequent siblings)
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
POB is currently modeled as a simple DCR device.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 12 +++++++++++
hw/ppc/ppc405_uc.c | 50 ++++++++++++++++++++++++++--------------------
2 files changed, 40 insertions(+), 22 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d63c2acdc7b5..4140e811d5ec 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* PLB to OPB bridge */
+#define TYPE_PPC405_POB "ppc405-pob"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
+struct Ppc405PobState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+};
+
/* OPB arbitrer */
#define TYPE_PPC405_OPBA "ppc405-opba"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
@@ -220,6 +231,7 @@ struct Ppc405SoCState {
Ppc405DmaState dma;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
+ Ppc405PobState pob;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d66db9b9c14a..1e731f69932c 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -234,19 +234,11 @@ enum {
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob_t ppc4xx_pob_t;
-struct ppc4xx_pob_t {
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
-};
-
static uint32_t dcr_read_pob (void *opaque, int dcrn)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(opaque);
uint32_t ret;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
ret = pob->bear;
@@ -268,9 +260,8 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(opaque);
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
/* Read only */
@@ -286,26 +277,32 @@ static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc4xx_pob_reset (void *opaque)
+static void ppc405_pob_reset(DeviceState *opaque)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(opaque);
- pob = opaque;
/* No error */
pob->bear = 0x00000000;
pob->besr0 = 0x0000000;
pob->besr1 = 0x0000000;
}
-static void ppc4xx_pob_init(CPUPPCState *env)
+static void ppc405_pob_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_pob_t *pob;
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- pob = g_new0(ppc4xx_pob_t, 1);
- ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
- qemu_register_reset(ppc4xx_pob_reset, pob);
+ ppc4xx_dcr_register(dcr, POB0_BEAR, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR0, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR1, &dcr_read_pob, &dcr_write_pob);
+}
+
+static void ppc405_pob_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_pob_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_pob_reset;
}
/*****************************************************************************/
@@ -1361,6 +1358,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
+
+ object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1389,7 +1388,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
- ppc4xx_pob_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
+ return;
+ }
/* OBP arbitrer */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
@@ -1508,6 +1509,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_POB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PobState),
+ .class_init = ppc405_pob_class_init,
+ }, {
.name = TYPE_PPC405_OPBA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 17/22] ppc/ppc405: QOM'ify PLB
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (15 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 16/22] ppc/ppc405: QOM'ify POB Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 18/22] ppc/ppc405: QOM'ify MAL Cédric Le Goater
` (5 subsequent siblings)
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 14 +++++++++--
hw/ppc/ppc405_uc.c | 58 +++++++++++++++++++++++++---------------------
hw/ppc/sam460ex.c | 4 +++-
3 files changed, 47 insertions(+), 29 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4140e811d5ec..cb34792daf6b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* Peripheral local bus arbitrer */
+#define TYPE_PPC405_PLB "ppc405-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
+struct Ppc405PlbState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t acr;
+ uint32_t bear;
+ uint32_t besr;
+};
+
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -232,11 +243,10 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
+ Ppc405PlbState plb;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
-void ppc4xx_plb_init(CPUPPCState *env);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 1e731f69932c..12d25cfbf38b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -148,19 +148,11 @@ enum {
PLB4A1_ACR = 0x089,
};
-typedef struct ppc4xx_plb_t ppc4xx_plb_t;
-struct ppc4xx_plb_t {
- uint32_t acr;
- uint32_t bear;
- uint32_t besr;
-};
-
static uint32_t dcr_read_plb (void *opaque, int dcrn)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
uint32_t ret;
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
ret = plb->acr;
@@ -182,9 +174,8 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
/* We don't care about the actual parameters written as
@@ -202,28 +193,34 @@ static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc4xx_plb_reset (void *opaque)
+static void ppc405_plb_reset(DeviceState *opaque)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
- plb = opaque;
plb->acr = 0x00000000;
plb->bear = 0x00000000;
plb->besr = 0x00000000;
}
-void ppc4xx_plb_init(CPUPPCState *env)
+static void ppc405_plb_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_plb_t *plb;
-
- plb = g_new0(ppc4xx_plb_t, 1);
- ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- qemu_register_reset(ppc4xx_plb_reset, plb);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, PLB3A0_ACR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A0_ACR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_ACR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BEAR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BESR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A1_ACR, &dcr_read_plb, &dcr_write_plb);
+}
+
+static void ppc405_plb_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_plb_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_plb_reset;
}
/*****************************************************************************/
@@ -1360,6 +1357,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
+
+ object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1385,7 +1384,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) {
+ return;
+ }
/* PLB to OPB bridge */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
@@ -1509,6 +1510,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_PLB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PlbState),
+ .class_init = ppc405_plb_class_init,
+ }, {
.name = TYPE_PPC405_POB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PobState),
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 320c61a7f36c..31139c1554de 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -309,7 +309,9 @@ static void sam460ex_init(MachineState *machine)
ppc_dcr_init(env, NULL, NULL);
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ dev = qdev_new(TYPE_PPC405_PLB);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* interrupt controllers */
for (i = 0; i < ARRAY_SIZE(uic); i++) {
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 18/22] ppc/ppc405: QOM'ify MAL
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (16 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 17/22] ppc/ppc405: QOM'ify PLB Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
` (4 subsequent siblings)
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 1 +
include/hw/ppc/ppc4xx.h | 32 +++++++++-
hw/ppc/ppc405_uc.c | 18 ++++--
hw/ppc/ppc4xx_devs.c | 134 ++++++++++++++++++----------------------
hw/ppc/sam460ex.c | 16 +++--
5 files changed, 115 insertions(+), 86 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index cb34792daf6b..31c94e474209 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -244,6 +244,7 @@ struct Ppc405SoCState {
Ppc405OpbaState opba;
Ppc405PobState pob;
Ppc405PlbState plb;
+ Ppc4xxMalState mal;
};
/* PowerPC 405 core */
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index bb373db0ba10..b8426bbc353d 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -26,6 +26,7 @@
#define PPC4XX_H
#include "hw/ppc/ppc.h"
+#include "hw/sysbus.h"
#include "exec/memory.h"
#include "hw/sysbus.h"
@@ -46,9 +47,6 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
hwaddr *ram_sizes,
int do_init);
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4]);
-
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/*
@@ -67,4 +65,32 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
Error **errp);
+/* Memory Access Layer (MAL) */
+#define TYPE_PPC4xx_MAL "ppc4xx-mal"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
+struct Ppc4xxMalState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ qemu_irq irqs[4];
+ uint32_t cfg;
+ uint32_t esr;
+ uint32_t ier;
+ uint32_t txcasr;
+ uint32_t txcarr;
+ uint32_t txeobisr;
+ uint32_t txdeir;
+ uint32_t rxcasr;
+ uint32_t rxcarr;
+ uint32_t rxeobisr;
+ uint32_t rxdeir;
+ uint32_t *txctpr;
+ uint32_t *rxctpr;
+ uint32_t *rcbs;
+ uint8_t txcnum;
+ uint8_t rxcnum;
+};
+
+void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
+ qemu_irq irqs[4]);
+
#endif /* PPC4XX_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 12d25cfbf38b..73b9e60881fd 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1359,12 +1359,13 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
+
+ object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq mal_irqs[4];
CPUPPCState *env;
int i;
@@ -1481,11 +1482,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* MAL */
- mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
- mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
- mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
- mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
- ppc4xx_mal_init(env, 4, 2, mal_irqs);
+ object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
+ object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
+ qdev_get_gpio_in(s->uic, 11 + i));
+ }
/* Ethernet */
/* Uses UIC IRQs 9, 15, 17 */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index e07bdba0f912..3cb6d0e66eff 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -491,32 +491,10 @@ enum {
MAL0_RCBS1 = 0x1E1,
};
-typedef struct ppc4xx_mal_t ppc4xx_mal_t;
-struct ppc4xx_mal_t {
- qemu_irq irqs[4];
- uint32_t cfg;
- uint32_t esr;
- uint32_t ier;
- uint32_t txcasr;
- uint32_t txcarr;
- uint32_t txeobisr;
- uint32_t txdeir;
- uint32_t rxcasr;
- uint32_t rxcarr;
- uint32_t rxeobisr;
- uint32_t rxdeir;
- uint32_t *txctpr;
- uint32_t *rxctpr;
- uint32_t *rcbs;
- uint8_t txcnum;
- uint8_t rxcnum;
-};
-
-static void ppc4xx_mal_reset(void *opaque)
+static void ppc4xx_mal_reset(DeviceState *dev)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
- mal = opaque;
mal->cfg = 0x0007C000;
mal->esr = 0x00000000;
mal->ier = 0x00000000;
@@ -530,10 +508,9 @@ static void ppc4xx_mal_reset(void *opaque)
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
uint32_t ret;
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
ret = mal->cfg;
@@ -587,13 +564,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x80000000) {
- ppc4xx_mal_reset(mal);
+ ppc4xx_mal_reset(DEVICE(mal));
}
mal->cfg = val & 0x00FFC087;
break;
@@ -644,59 +620,66 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
}
}
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4])
+static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
int i;
- assert(txcnum <= 32 && rxcnum <= 32);
- mal = g_malloc0(sizeof(*mal));
- mal->txcnum = txcnum;
- mal->rxcnum = rxcnum;
- mal->txctpr = g_new0(uint32_t, txcnum);
- mal->rxctpr = g_new0(uint32_t, rxcnum);
- mal->rcbs = g_new0(uint32_t, rxcnum);
- for (i = 0; i < 4; i++) {
- mal->irqs[i] = irqs[i];
+ if (mal->txcnum > 32 || mal->rxcnum > 32) {
+ error_setg(errp, "invalid TXC/RXC number");
+ return;
+ }
+
+ mal->txctpr = g_new0(uint32_t, mal->txcnum);
+ mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
+ mal->rcbs = g_new0(uint32_t, mal->rxcnum);
+
+ for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]);
}
- qemu_register_reset(&ppc4xx_mal_reset, mal);
- ppc_dcr_register(env, MAL0_CFG,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_ESR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_IER,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- for (i = 0; i < txcnum; i++) {
- ppc_dcr_register(env, MAL0_TXCTP0R + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+
+ ppc4xx_dcr_register(dcr, MAL0_CFG, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_ESR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_IER, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXCASR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXCARR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXDEIR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXCASR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXCARR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXDEIR, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->txcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i,
+ &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
- ppc_dcr_register(env, MAL0_RXCTP0R + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->rxcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i,
+ &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
- ppc_dcr_register(env, MAL0_RCBS0 + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->rxcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i,
+ &dcr_read_mal, &dcr_write_mal);
}
}
+static Property ppc4xx_mal_properties[] = {
+ DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
+ DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_mal_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc4xx_mal_reset;
+ device_class_set_props(dc, ppc4xx_mal_properties);
+}
+
void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
dcr_read_cb dcr_read, dcr_write_cb dcr_write)
{
@@ -733,6 +716,11 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
+ .name = TYPE_PPC4xx_MAL,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxMalState),
+ .class_init = ppc4xx_mal_class_init,
+ }, {
.name = TYPE_PPC4xx_DCR_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc4xxDcrDeviceState),
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 31139c1554de..5f0e0ccaf485 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -280,7 +280,7 @@ static void sam460ex_init(MachineState *machine)
hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
- qemu_irq mal_irqs[4];
+ Ppc4xxMalState *mal;
int i;
PCIBus *pci_bus;
PowerPCCPU *cpu;
@@ -387,10 +387,18 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdr_init(env);
/* MAL */
- for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) {
- mal_irqs[i] = qdev_get_gpio_in(uic[2], 3 + i);
+ dev = qdev_new(TYPE_PPC4xx_MAL);
+ mal = PPC4xx_MAL(dev);
+
+ qdev_prop_set_uint32(dev, "txc-num", 4);
+ qdev_prop_set_uint32(dev, "rxc-num", 16);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(mal), cpu, &error_fatal);
+ object_unref(OBJECT(mal));
+
+ for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
+ qdev_get_gpio_in(uic[2], 3 + i));
}
- ppc4xx_mal_init(env, 4, 16, mal_irqs);
/* DMA */
ppc4xx_dma_init(env, 0x200);
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (17 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 18/22] ppc/ppc405: QOM'ify MAL Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 14:55 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 20/22] ppc/ppc405: Use an explicit PPCUIC object Cédric Le Goater
` (3 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 55 +++++++++++++++++++++++++++++-------------
1 file changed, 38 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 5ba12d60bc00..195aa58c35ad 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -71,18 +71,23 @@ struct Ppc405MachineState {
* - NVRAM (0xF0000000)
* - FPGA (0xF0300000)
*/
-typedef struct ref405ep_fpga_t ref405ep_fpga_t;
-struct ref405ep_fpga_t {
+
+#define TYPE_PPC405_FPGA "ppc405-fpga"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA);
+struct Ppc405FpgaState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
uint8_t reg0;
uint8_t reg1;
};
static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
- ref405ep_fpga_t *fpga;
+ Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
uint32_t ret;
- fpga = opaque;
switch (addr) {
case 0x0:
ret = fpga->reg0;
@@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ref405ep_fpga_t *fpga;
+ Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
- fpga = opaque;
switch (addr) {
case 0x0:
/* Read only */
@@ -126,27 +130,39 @@ static const MemoryRegionOps ref405ep_fpga_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ref405ep_fpga_reset (void *opaque)
+static void ref405ep_fpga_reset(DeviceState *dev)
{
- ref405ep_fpga_t *fpga;
+ Ppc405FpgaState *fpga = PPC405_FPGA(dev);
- fpga = opaque;
fpga->reg0 = 0x00;
fpga->reg1 = 0x0F;
}
-static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
+static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
{
- ref405ep_fpga_t *fpga;
- MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
+ Ppc405FpgaState *s = PPC405_FPGA(dev);
- fpga = g_new0(ref405ep_fpga_t, 1);
- memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
+ memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
"fpga", 0x00000100);
- memory_region_add_subregion(sysmem, base, fpga_memory);
- qemu_register_reset(&ref405ep_fpga_reset, fpga);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ref405ep_fpga_realize;
+ dc->user_creatable = false;
+ dc->reset = ref405ep_fpga_reset;
}
+static const TypeInfo ref405ep_fpga_type = {
+ .name = TYPE_PPC405_FPGA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405FpgaState),
+ .class_init = ref405ep_fpga_class_init,
+};
+
/*
* CPU reset handler when booting directly from a loaded kernel
*/
@@ -332,7 +348,11 @@ static void ref405ep_init(MachineState *machine)
memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
/* Register FPGA */
- ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
+ dev = qdev_new(TYPE_PPC405_FPGA);
+ object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
+
/* Register NVRAM */
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
@@ -377,6 +397,7 @@ static void ppc405_machine_init(void)
{
type_register_static(&ppc405_machine_type);
type_register_static(&ref405ep_type);
+ type_register_static(&ref405ep_fpga_type);
}
type_init(ppc405_machine_init)
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA
2022-08-08 10:27 ` [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
@ 2022-08-08 14:55 ` BALATON Zoltan
2022-08-08 15:58 ` Cédric Le Goater
0 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:55 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 4162 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405_boards.c | 55 +++++++++++++++++++++++++++++-------------
> 1 file changed, 38 insertions(+), 17 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 5ba12d60bc00..195aa58c35ad 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -71,18 +71,23 @@ struct Ppc405MachineState {
> * - NVRAM (0xF0000000)
> * - FPGA (0xF0300000)
> */
> -typedef struct ref405ep_fpga_t ref405ep_fpga_t;
> -struct ref405ep_fpga_t {
> +
> +#define TYPE_PPC405_FPGA "ppc405-fpga"
If this is specific to ref405ep maybe it should be named accordingly.
Regards,
BALATON Zoltan
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA);
> +struct Ppc405FpgaState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +
> uint8_t reg0;
> uint8_t reg1;
> };
>
> static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> {
> - ref405ep_fpga_t *fpga;
> + Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
> uint32_t ret;
>
> - fpga = opaque;
> switch (addr) {
> case 0x0:
> ret = fpga->reg0;
> @@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
> unsigned size)
> {
> - ref405ep_fpga_t *fpga;
> + Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
>
> - fpga = opaque;
> switch (addr) {
> case 0x0:
> /* Read only */
> @@ -126,27 +130,39 @@ static const MemoryRegionOps ref405ep_fpga_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> -static void ref405ep_fpga_reset (void *opaque)
> +static void ref405ep_fpga_reset(DeviceState *dev)
> {
> - ref405ep_fpga_t *fpga;
> + Ppc405FpgaState *fpga = PPC405_FPGA(dev);
>
> - fpga = opaque;
> fpga->reg0 = 0x00;
> fpga->reg1 = 0x0F;
> }
>
> -static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
> +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
> {
> - ref405ep_fpga_t *fpga;
> - MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
> + Ppc405FpgaState *s = PPC405_FPGA(dev);
>
> - fpga = g_new0(ref405ep_fpga_t, 1);
> - memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
> + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
> "fpga", 0x00000100);
> - memory_region_add_subregion(sysmem, base, fpga_memory);
> - qemu_register_reset(&ref405ep_fpga_reset, fpga);
> + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
> +}
> +
> +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ref405ep_fpga_realize;
> + dc->user_creatable = false;
> + dc->reset = ref405ep_fpga_reset;
> }
>
> +static const TypeInfo ref405ep_fpga_type = {
> + .name = TYPE_PPC405_FPGA,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc405FpgaState),
> + .class_init = ref405ep_fpga_class_init,
> +};
> +
> /*
> * CPU reset handler when booting directly from a loaded kernel
> */
> @@ -332,7 +348,11 @@ static void ref405ep_init(MachineState *machine)
> memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
>
> /* Register FPGA */
> - ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
> + dev = qdev_new(TYPE_PPC405_FPGA);
> + object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
> +
> /* Register NVRAM */
> dev = qdev_new("sysbus-m48t08");
> qdev_prop_set_int32(dev, "base-year", 1968);
> @@ -377,6 +397,7 @@ static void ppc405_machine_init(void)
> {
> type_register_static(&ppc405_machine_type);
> type_register_static(&ref405ep_type);
> + type_register_static(&ref405ep_fpga_type);
> }
>
> type_init(ppc405_machine_init)
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA
2022-08-08 14:55 ` BALATON Zoltan
@ 2022-08-08 15:58 ` Cédric Le Goater
0 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 15:58 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 16:55, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405_boards.c | 55 +++++++++++++++++++++++++++++-------------
>> 1 file changed, 38 insertions(+), 17 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 5ba12d60bc00..195aa58c35ad 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -71,18 +71,23 @@ struct Ppc405MachineState {
>> * - NVRAM (0xF0000000)
>> * - FPGA (0xF0300000)
>> */
>> -typedef struct ref405ep_fpga_t ref405ep_fpga_t;
>> -struct ref405ep_fpga_t {
>> +
>> +#define TYPE_PPC405_FPGA "ppc405-fpga"
>
> If this is specific to ref405ep maybe it should be named accordingly.
done.
Thanks,
C.
>
> Regards,
> BALATON Zoltan
>
>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA);
>> +struct Ppc405FpgaState {
>> + SysBusDevice parent_obj;
>> +
>> + MemoryRegion iomem;
>> +
>> uint8_t reg0;
>> uint8_t reg1;
>> };
>>
>> static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
>> {
>> - ref405ep_fpga_t *fpga;
>> + Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
>> uint32_t ret;
>>
>> - fpga = opaque;
>> switch (addr) {
>> case 0x0:
>> ret = fpga->reg0;
>> @@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
>> static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
>> unsigned size)
>> {
>> - ref405ep_fpga_t *fpga;
>> + Ppc405FpgaState *fpga = PPC405_FPGA(opaque);
>>
>> - fpga = opaque;
>> switch (addr) {
>> case 0x0:
>> /* Read only */
>> @@ -126,27 +130,39 @@ static const MemoryRegionOps ref405ep_fpga_ops = {
>> .endianness = DEVICE_BIG_ENDIAN,
>> };
>>
>> -static void ref405ep_fpga_reset (void *opaque)
>> +static void ref405ep_fpga_reset(DeviceState *dev)
>> {
>> - ref405ep_fpga_t *fpga;
>> + Ppc405FpgaState *fpga = PPC405_FPGA(dev);
>>
>> - fpga = opaque;
>> fpga->reg0 = 0x00;
>> fpga->reg1 = 0x0F;
>> }
>>
>> -static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
>> +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
>> {
>> - ref405ep_fpga_t *fpga;
>> - MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
>> + Ppc405FpgaState *s = PPC405_FPGA(dev);
>>
>> - fpga = g_new0(ref405ep_fpga_t, 1);
>> - memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
>> + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
>> "fpga", 0x00000100);
>> - memory_region_add_subregion(sysmem, base, fpga_memory);
>> - qemu_register_reset(&ref405ep_fpga_reset, fpga);
>> + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
>> +}
>> +
>> +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + dc->realize = ref405ep_fpga_realize;
>> + dc->user_creatable = false;
>> + dc->reset = ref405ep_fpga_reset;
>> }
>>
>> +static const TypeInfo ref405ep_fpga_type = {
>> + .name = TYPE_PPC405_FPGA,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(Ppc405FpgaState),
>> + .class_init = ref405ep_fpga_class_init,
>> +};
>> +
>> /*
>> * CPU reset handler when booting directly from a loaded kernel
>> */
>> @@ -332,7 +348,11 @@ static void ref405ep_init(MachineState *machine)
>> memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
>>
>> /* Register FPGA */
>> - ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
>> + dev = qdev_new(TYPE_PPC405_FPGA);
>> + object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
>> + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
>> +
>> /* Register NVRAM */
>> dev = qdev_new("sysbus-m48t08");
>> qdev_prop_set_int32(dev, "base-year", 1968);
>> @@ -377,6 +397,7 @@ static void ppc405_machine_init(void)
>> {
>> type_register_static(&ppc405_machine_type);
>> type_register_static(&ref405ep_type);
>> + type_register_static(&ref405ep_fpga_type);
>> }
>>
>> type_init(ppc405_machine_init)
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 20/22] ppc/ppc405: Use an explicit PPCUIC object
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (18 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 14:58 ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 21/22] ppc/ppc405: Use an explicit I2C object Cédric Le Goater
` (2 subsequent siblings)
22 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 3 ++-
hw/ppc/ppc405_uc.c | 26 +++++++++++++-------------
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 31c94e474209..8e67ad0b72c3 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
+#include "hw/intc/ppc-uic.h"
#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000
@@ -234,7 +235,7 @@ struct Ppc405SoCState {
hwaddr ram_size;
PowerPCCPU cpu;
- DeviceState *uic;
+ PPCUIC uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 73b9e60881fd..d80e22d265c8 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1341,6 +1341,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpu", &s->cpu,
POWERPC_CPU_TYPE_NAME("405ep"));
+ object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
+
object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
@@ -1401,17 +1403,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
/* Universal interrupt controller */
- s->uic = qdev_new(TYPE_PPC_UIC);
-
- object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
+ object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
&error_fatal);
- if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->uic), errp)) {
return;
}
- sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
- sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_CINT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
@@ -1422,7 +1422,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
"ppc405.sdram0", s->dram_mr,
s->ram_bases[0], s->ram_sizes[0]);
- ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1,
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
s->ram_banks, s->ram_bases, s->ram_sizes,
s->do_dram_init);
@@ -1438,12 +1438,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
- qdev_get_gpio_in(s->uic, 5 + i));
+ qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
}
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(s->uic, 2));
+ qdev_get_gpio_in(DEVICE(&s->uic), 2));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
@@ -1454,13 +1454,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Serial ports */
if (serial_hd(0) != NULL) {
serial_mm_init(get_system_memory(), 0xef600300, 0,
- qdev_get_gpio_in(s->uic, 0),
+ qdev_get_gpio_in(DEVICE(&s->uic), 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
serial_mm_init(get_system_memory(), 0xef600400, 0,
- qdev_get_gpio_in(s->uic, 1),
+ qdev_get_gpio_in(DEVICE(&s->uic), 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
@@ -1478,7 +1478,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
- qdev_get_gpio_in(s->uic, 19 + i));
+ qdev_get_gpio_in(DEVICE(&s->uic), 19 + i));
}
/* MAL */
@@ -1490,7 +1490,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
- qdev_get_gpio_in(s->uic, 11 + i));
+ qdev_get_gpio_in(DEVICE(&s->uic), 11 + i));
}
/* Ethernet */
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 20/22] ppc/ppc405: Use an explicit PPCUIC object
2022-08-08 10:27 ` [PATCH v3 20/22] ppc/ppc405: Use an explicit PPCUIC object Cédric Le Goater
@ 2022-08-08 14:58 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:58 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 5281 bytes --]
It's not that it's now explicitly typed as PPCUIC but more that it's now
embedded in soc state instead of dynamically allocated. So Embed UIC in
soc state may be a better patch title.
Regards,
BALATON Zoltan
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 3 ++-
> hw/ppc/ppc405_uc.c | 26 +++++++++++++-------------
> 2 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 31c94e474209..8e67ad0b72c3 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -27,6 +27,7 @@
>
> #include "qom/object.h"
> #include "hw/ppc/ppc4xx.h"
> +#include "hw/intc/ppc-uic.h"
>
> #define PPC405EP_SDRAM_BASE 0x00000000
> #define PPC405EP_NVRAM_BASE 0xF0000000
> @@ -234,7 +235,7 @@ struct Ppc405SoCState {
> hwaddr ram_size;
>
> PowerPCCPU cpu;
> - DeviceState *uic;
> + PPCUIC uic;
> Ppc405CpcState cpc;
> Ppc405GptState gpt;
> Ppc405OcmState ocm;
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 73b9e60881fd..d80e22d265c8 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1341,6 +1341,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "cpu", &s->cpu,
> POWERPC_CPU_TYPE_NAME("405ep"));
>
> + object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
> +
> object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
> object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
>
> @@ -1401,17 +1403,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
>
> /* Universal interrupt controller */
> - s->uic = qdev_new(TYPE_PPC_UIC);
> -
> - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
> + object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
> &error_fatal);
> - if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uic), errp)) {
> return;
> }
>
> - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
> - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uic), PPCUIC_OUTPUT_CINT,
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> @@ -1422,7 +1422,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> "ppc405.sdram0", s->dram_mr,
> s->ram_bases[0], s->ram_sizes[0]);
>
> - ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1,
> + ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
> s->ram_banks, s->ram_bases, s->ram_sizes,
> s->do_dram_init);
>
> @@ -1438,12 +1438,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> - qdev_get_gpio_in(s->uic, 5 + i));
> + qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
> }
>
> /* I2C controller */
> sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
> - qdev_get_gpio_in(s->uic, 2));
> + qdev_get_gpio_in(DEVICE(&s->uic), 2));
>
> /* GPIO */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> @@ -1454,13 +1454,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* Serial ports */
> if (serial_hd(0) != NULL) {
> serial_mm_init(get_system_memory(), 0xef600300, 0,
> - qdev_get_gpio_in(s->uic, 0),
> + qdev_get_gpio_in(DEVICE(&s->uic), 0),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
> DEVICE_BIG_ENDIAN);
> }
> if (serial_hd(1) != NULL) {
> serial_mm_init(get_system_memory(), 0xef600400, 0,
> - qdev_get_gpio_in(s->uic, 1),
> + qdev_get_gpio_in(DEVICE(&s->uic), 1),
> PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
> DEVICE_BIG_ENDIAN);
> }
> @@ -1478,7 +1478,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i,
> - qdev_get_gpio_in(s->uic, 19 + i));
> + qdev_get_gpio_in(DEVICE(&s->uic), 19 + i));
> }
>
> /* MAL */
> @@ -1490,7 +1490,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
> - qdev_get_gpio_in(s->uic, 11 + i));
> + qdev_get_gpio_in(DEVICE(&s->uic), 11 + i));
> }
>
> /* Ethernet */
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 21/22] ppc/ppc405: Use an explicit I2C object
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (19 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 20/22] ppc/ppc405: Use an explicit PPCUIC object Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 22/22] ppc/ppc4xx: Fix sdram trace events Cédric Le Goater
2022-08-08 12:16 ` [PATCH v3 00/22] ppc: QOM'ify 405 board BALATON Zoltan
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus from the machine init routine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 2 ++
hw/ppc/ppc405_uc.c | 10 ++++++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 8e67ad0b72c3..56881b181ba1 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -28,6 +28,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/intc/ppc-uic.h"
+#include "hw/i2c/ppc4xx_i2c.h"
#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000
@@ -241,6 +242,7 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+ PPC4xxI2CState i2c;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d80e22d265c8..111ebbdb7865 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1354,6 +1354,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
+ object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C);
+
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
@@ -1442,8 +1444,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* I2C controller */
- sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(DEVICE(&s->uic), 2));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, 0xef600500);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
+ qdev_get_gpio_in(DEVICE(&s->uic), 2));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v3 22/22] ppc/ppc4xx: Fix sdram trace events
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (20 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 21/22] ppc/ppc405: Use an explicit I2C object Cédric Le Goater
@ 2022-08-08 10:27 ` Cédric Le Goater
2022-08-08 12:16 ` [PATCH v3 00/22] ppc: QOM'ify 405 board BALATON Zoltan
22 siblings, 0 replies; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 10:27 UTC (permalink / raw)
To: qemu-ppc
Cc: Daniel Henrique Barboza, qemu-devel, BALATON Zoltan,
Peter Maydell, Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 3cb6d0e66eff..5d5626c0506d 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -175,7 +175,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
sdram->bcr[i] = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
- trace_ppc4xx_sdram_unmap(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
sdram_size(bcr));
memory_region_add_subregion(&sdram->containers[i], 0,
--
2.37.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v3 00/22] ppc: QOM'ify 405 board
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
` (21 preceding siblings ...)
2022-08-08 10:27 ` [PATCH v3 22/22] ppc/ppc4xx: Fix sdram trace events Cédric Le Goater
@ 2022-08-08 12:16 ` BALATON Zoltan
2022-08-08 13:10 ` Cédric Le Goater
22 siblings, 1 reply; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 12:16 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 3382 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> Hello,
>
> Here is large series QOM'ifying the PPC405 board. It introduces a new
> generic machine and SoC models, converts the current device models to
> QOM and populates the SoC. The process is quite mechanical without too
> much issues to handle. The noisy part is the initial patch introducing
> the SoC realize routine.
>
> What's left ?
>
> * the SDRAM mappings are very baroque and certainly could be simplified.
> I think we should QOMify the ppc440 machines before addressing this
> part.
The issue with SDRAM controller and the likely reason why its model looks
so complex is that it can't handle any RAM size because of how the bank
sizes are encoded in the registers so it only really supports real RAM
modules which are predefined sizes. Also the firmware discovers RAM by
looking at SPD data and may only check the slots that the real hardware
has which may not be the first one. Previously I had code to round down
the memory size specified on the command line to an acceptable size and
issue a warning to let the user know but this was dropped because of some
changes in code elsewhere which now allocates memory before the machine
could check and ajust it so we can only adjust it by wasting some. Take
this into account and check the ppc4xx_sdram_banks() function and 440
machines before changing this.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
> Changes in v3 :
>
> - New device model Ppc4xxDcrDeviceState
> - Removal of ppc4xx_mal_init(), ppc4xx_plb_init() and ppc405_ebc_init()
> - Fixes for some reset issues
> - Kept 2 RAM banks at the Soc level but only one is initialized.
> - Moved SRAM under the machine. It's not part of the SoC according
> to the 405 specs
>
> Changes in v2 :
>
> - docs/about/removed-features.rst update
> - Fix compile breakage (uic)
> - Fix CPU reset, which breaking u-boot boot
> - Changed prefix of memory regions to "ppc405"
> - Reduced the number of RAM banks to 1. Second was a dummy one to
> please ppc405ep_init()
>
> Cédric Le Goater (22):
> ppc/ppc405: Remove taihu machine
> ppc/ppc405: Introduce a PPC405 generic machine
> ppc/ppc405: Move devices under the ref405ep machine
> ppc/ppc405: Move SRAM under the ref405ep machine
> ppc/ppc405: Introduce a PPC405 SoC
> ppc/ppc405: Start QOMification of the SoC
> ppc/ppc405: QOM'ify CPU
> ppc/ppc4xx: Introduce a DCR device model
> ppc/ppc405: QOM'ify CPC
> ppc/ppc405: QOM'ify GPT
> ppc/ppc405: QOM'ify OCM
> ppc/ppc405: QOM'ify GPIO
> ppc/ppc405: QOM'ify DMA
> ppc/ppc405: QOM'ify EBC
> ppc/ppc405: QOM'ify OPBA
> ppc/ppc405: QOM'ify POB
> ppc/ppc405: QOM'ify PLB
> ppc/ppc405: QOM'ify MAL
> ppc/ppc405: QOM'ify FPGA
> ppc/ppc405: Use an explicit PPCUIC object
> ppc/ppc405: Use an explicit I2C object
> ppc/ppc4xx: Fix sdram trace events
>
> docs/about/deprecated.rst | 9 -
> docs/about/removed-features.rst | 6 +
> docs/system/ppc/embedded.rst | 1 -
> hw/ppc/ppc405.h | 198 +++++++-
> include/hw/ppc/ppc4xx.h | 48 +-
> hw/ppc/ppc405_boards.c | 375 ++++-----------
> hw/ppc/ppc405_uc.c | 828 +++++++++++++++++---------------
> hw/ppc/ppc4xx_devs.c | 184 ++++---
> hw/ppc/sam460ex.c | 24 +-
> MAINTAINERS | 2 +-
> 10 files changed, 903 insertions(+), 772 deletions(-)
>
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v3 00/22] ppc: QOM'ify 405 board
2022-08-08 12:16 ` [PATCH v3 00/22] ppc: QOM'ify 405 board BALATON Zoltan
@ 2022-08-08 13:10 ` Cédric Le Goater
2022-08-08 14:08 ` BALATON Zoltan
0 siblings, 1 reply; 51+ messages in thread
From: Cédric Le Goater @ 2022-08-08 13:10 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
On 8/8/22 14:16, BALATON Zoltan wrote:
> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>> Hello,
>>
>> Here is large series QOM'ifying the PPC405 board. It introduces a new
>> generic machine and SoC models, converts the current device models to
>> QOM and populates the SoC. The process is quite mechanical without too
>> much issues to handle. The noisy part is the initial patch introducing
>> the SoC realize routine.
>>
>> What's left ?
>>
>> * the SDRAM mappings are very baroque and certainly could be simplified.
>> I think we should QOMify the ppc440 machines before addressing this
>> part.
>
> The issue with SDRAM controller and the likely reason why its model looks so complex is that it can't handle any RAM size because of how the bank sizes are encoded in the registers so it only really supports real RAM modules which are predefined sizes. Also the firmware discovers RAM by looking at SPD data and may only check the slots that the real hardware has which may not be the first one.
>
> Previously I had code to round down the memory size specified on the command line to an acceptable size and issue a warning to let the user know but this was dropped because of some changes in code elsewhere which now allocates memory before the machine could check and ajust it so we can only adjust it by wasting some.
I don't think we should care adjusting the values. the machine init
routine should check that the RAM size is valid or fail. The machine
should also have a sane RAM size value by default.
See how the aspeed machine deals with similar constraints of its SDRAM
controller in aspeed_machine_init(). If the sdram controller does not
validate the RAM size, aspeed_sdmc_set_ram_size() fails with an error.
C.
> Take this into account and check the ppc4xx_sdram_banks() function and 440 machines before changing this.
>
> Regards,
> BALATON Zoltan
>
>
>> Thanks,
>>
>> C.
>>
>> Changes in v3 :
>>
>> - New device model Ppc4xxDcrDeviceState
>> - Removal of ppc4xx_mal_init(), ppc4xx_plb_init() and ppc405_ebc_init()
>> - Fixes for some reset issues
>> - Kept 2 RAM banks at the Soc level but only one is initialized.
>> - Moved SRAM under the machine. It's not part of the SoC according
>> to the 405 specs
>>
>> Changes in v2 :
>>
>> - docs/about/removed-features.rst update
>> - Fix compile breakage (uic)
>> - Fix CPU reset, which breaking u-boot boot
>> - Changed prefix of memory regions to "ppc405"
>> - Reduced the number of RAM banks to 1. Second was a dummy one to
>> please ppc405ep_init()
>>
>> Cédric Le Goater (22):
>> ppc/ppc405: Remove taihu machine
>> ppc/ppc405: Introduce a PPC405 generic machine
>> ppc/ppc405: Move devices under the ref405ep machine
>> ppc/ppc405: Move SRAM under the ref405ep machine
>> ppc/ppc405: Introduce a PPC405 SoC
>> ppc/ppc405: Start QOMification of the SoC
>> ppc/ppc405: QOM'ify CPU
>> ppc/ppc4xx: Introduce a DCR device model
>> ppc/ppc405: QOM'ify CPC
>> ppc/ppc405: QOM'ify GPT
>> ppc/ppc405: QOM'ify OCM
>> ppc/ppc405: QOM'ify GPIO
>> ppc/ppc405: QOM'ify DMA
>> ppc/ppc405: QOM'ify EBC
>> ppc/ppc405: QOM'ify OPBA
>> ppc/ppc405: QOM'ify POB
>> ppc/ppc405: QOM'ify PLB
>> ppc/ppc405: QOM'ify MAL
>> ppc/ppc405: QOM'ify FPGA
>> ppc/ppc405: Use an explicit PPCUIC object
>> ppc/ppc405: Use an explicit I2C object
>> ppc/ppc4xx: Fix sdram trace events
>>
>> docs/about/deprecated.rst | 9 -
>> docs/about/removed-features.rst | 6 +
>> docs/system/ppc/embedded.rst | 1 -
>> hw/ppc/ppc405.h | 198 +++++++-
>> include/hw/ppc/ppc4xx.h | 48 +-
>> hw/ppc/ppc405_boards.c | 375 ++++-----------
>> hw/ppc/ppc405_uc.c | 828 +++++++++++++++++---------------
>> hw/ppc/ppc4xx_devs.c | 184 ++++---
>> hw/ppc/sam460ex.c | 24 +-
>> MAINTAINERS | 2 +-
>> 10 files changed, 903 insertions(+), 772 deletions(-)
>>
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 00/22] ppc: QOM'ify 405 board
2022-08-08 13:10 ` Cédric Le Goater
@ 2022-08-08 14:08 ` BALATON Zoltan
0 siblings, 0 replies; 51+ messages in thread
From: BALATON Zoltan @ 2022-08-08 14:08 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-ppc, Daniel Henrique Barboza, qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 2349 bytes --]
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
> On 8/8/22 14:16, BALATON Zoltan wrote:
>> On Mon, 8 Aug 2022, Cédric Le Goater wrote:
>>> Hello,
>>>
>>> Here is large series QOM'ifying the PPC405 board. It introduces a new
>>> generic machine and SoC models, converts the current device models to
>>> QOM and populates the SoC. The process is quite mechanical without too
>>> much issues to handle. The noisy part is the initial patch introducing
>>> the SoC realize routine.
>>>
>>> What's left ?
>>>
>>> * the SDRAM mappings are very baroque and certainly could be simplified.
>>> I think we should QOMify the ppc440 machines before addressing this
>>> part.
>>
>> The issue with SDRAM controller and the likely reason why its model looks
>> so complex is that it can't handle any RAM size because of how the bank
>> sizes are encoded in the registers so it only really supports real RAM
>> modules which are predefined sizes. Also the firmware discovers RAM by
>> looking at SPD data and may only check the slots that the real hardware has
>> which may not be the first one.
>> Previously I had code to round down the memory size specified on the
>> command line to an acceptable size and issue a warning to let the user know
>> but this was dropped because of some changes in code elsewhere which now
>> allocates memory before the machine could check and ajust it so we can only
>> adjust it by wasting some.
>
> I don't think we should care adjusting the values. the machine init
> routine should check that the RAM size is valid or fail. The machine
> should also have a sane RAM size value by default.
>
> See how the aspeed machine deals with similar constraints of its SDRAM
> controller in aspeed_machine_init(). If the sdram controller does not
> validate the RAM size, aspeed_sdmc_set_ram_size() fails with an error.
Even then we need to check if the specified memory matches one of the
allowed sized and distribute it to the allowed banks by the soc. This code
is more complex than the 405ep has currently and should not be reprated in
each board. That's why we have the ppc4xx_memory_banks and sdram_init
functions so while it may be possible to simmplify it a bit maybe not
much. I've spent quite some time with it so if you change it check that
at least sam360ex -m 2G still works.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 51+ messages in thread