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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id b25-20020aa7dc19000000b0043d668dec21sm1384083edu.38.2022.08.12.07.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Aug 2022 07:01:04 -0700 (PDT) Date: Fri, 12 Aug 2022 16:01:03 +0200 From: Andrew Jones To: Philipp Tomsich Cc: qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: Re: [PATCH 1/2] target/riscv: fence.i: update decode pattern Message-ID: <20220812140103.3lbh45oidiw2fhsf@kamzik> References: <20220812131304.1674484-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220812131304.1674484-1-philipp.tomsich@vrull.eu> Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Please use a cover-letter for multi-patch patch series. On Fri, Aug 12, 2022 at 03:13:03PM +0200, Philipp Tomsich wrote: > The RISC-V specification specifies imm12, rs1 and rd to be all-zeros, > so we can't ignore these bits when decoding into fence.i. > > Update the decode pattern to reflect the specification. I got hung-up on this for a bit since there isn't any "must-be-0" fields, only ignored fields, but the next patch gives a clue which helped me make sense of this. The encoding of these instructions with ignored fields set to anything except zero gets into reserved instruction territory, and QEMU may legally raise an illegal-instruction in that case, which this patch will start doing. It'd be nice to have a bit more text in this commit message to make that clear. > > Signed-off-by: Philipp Tomsich > --- > > target/riscv/insn32.decode | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 014127d066..089128c3dc 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -151,7 +151,7 @@ sra 0100000 ..... ..... 101 ..... 0110011 @r > or 0000000 ..... ..... 110 ..... 0110011 @r > and 0000000 ..... ..... 111 ..... 0110011 @r > fence ---- pred:4 succ:4 ----- 000 ----- 0001111 > -fence_i ---- ---- ---- ----- 001 ----- 0001111 > +fence_i 000000000000 00000 001 00000 0001111 ^ need two more spaces here to line up with fence. > csrrw ............ ..... 001 ..... 1110011 @csr > csrrs ............ ..... 010 ..... 1110011 @csr > csrrc ............ ..... 011 ..... 1110011 @csr > -- > 2.34.1 > > Thanks, drew