[PATCH] hw/arm/nvic: implement "num-prio-bits" property

[Anton Kochkov <anton.kochkov@proton.me>]

Cortex-M NVIC can be configured with different amount of
the maximum available priority bits. FreeRTOS has asserts
that checks if the all unavailable priority bits are unset
after writing into this register in real hardware.
To allow setting this number depending on the machine or
configuration expose priority bits as QDev property
which is by default is set to 8 as it was hardcoded in the past.
Thus, existing code doesn't require any additional changes,
and it doesn't change the default behavior of NVIC.

Signed-off-by: Anton Kochkov <anton.kochkov@proton.me>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
---
 hw/intc/armv7m_nvic.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 1f7763964c..b8959d645d 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2580,6 +2580,8 @@ static const VMStateDescription vmstate_nvic = {
 static Property props_nvic[] = {
     /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
     DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
+    /* Number of the maximum priority bits that can be used */
+    DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 8),
     DEFINE_PROP_END_OF_LIST()
 };

@@ -2690,7 +2692,9 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
     /* include space for internal exception vectors */
     s->num_irq += NVIC_FIRST_IRQ;

-    s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+    if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) {
+        s->num_prio_bits = 2;
+    }

     /*
      * This device provides a single memory region which covers the
--
2.37.1