[PATCH] hw/riscv: Setting address of vector reset is improved

[PATCH] hw/riscv: Setting address of vector reset is improved

[Maksim Perov]

Previously address is set by default value 0x1000 which is hardcoded in target/riscv/cpu_bits.h
If add to new RISC-V Machine in which ROM area is based on 0x1000 address than there is problem of running simulation

Signed-off-by: Maksim Perov <coder@frtk.ru>
---
 hw/riscv/boot.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 06b4fc5ac3..5e2438d39a 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -327,6 +327,10 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
     riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
                                  kernel_entry);
 
+    /* change reset vector address */
+    for (i = 0; i < harts->num_harts; i++) {
+        harts->harts[i].env.resetvec = rom_base;
+    }
     return;
 }
 
-- 
2.17.1

[PATCH] hw/riscv: Setting address of vector reset is improved

[Maksim Perov]

Previously address is set by default value 0x1000 which is hardcoded in target/riscv/cpu_bits.h
If add to new RISC-V Machine in which ROM area is not based on 0x1000 address than there is problem of running simulation

Signed-off-by: Maksim Perov <coder@frtk.ru>
---
 hw/riscv/boot.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 06b4fc5ac3..5e2438d39a 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -327,6 +327,10 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
     riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
                                  kernel_entry);
 
+    /* change reset vector address */
+    for (i = 0; i < harts->num_harts; i++) {
+        harts->harts[i].env.resetvec = rom_base;
+    }
     return;
 }
 
-- 
2.17.1

Re: [PATCH] hw/riscv: Setting address of vector reset is improved

[Alistair Francis]

On Tue, Aug 16, 2022 at 6:15 AM Maksim Perov <coder@frtk.ru> wrote:
>
> Previously address is set by default value 0x1000 which is hardcoded in target/riscv/cpu_bits.h
> If add to new RISC-V Machine in which ROM area is not based on 0x1000 address than there is problem of running simulation
>
> Signed-off-by: Maksim Perov <coder@frtk.ru>
> ---
>  hw/riscv/boot.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 06b4fc5ac3..5e2438d39a 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -327,6 +327,10 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
>      riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
>                                   kernel_entry);
>
> +    /* change reset vector address */
> +    for (i = 0; i < harts->num_harts; i++) {
> +        harts->harts[i].env.resetvec = rom_base;
> +    }

Thanks for the patch!

We don't want to do this though. The reset vector is part of the
hardware design, we don't want to change the reset vector based on the
software that is loaded.

The reset vector is exposed as a property (resetvec) and can be
configured from a board. You could also configure it from the command
line if you wanted to (although it might be overridden, I haven't
checked).

Alistair

>      return;
>  }
>
> --
> 2.17.1
>
>