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[31.208.27.151]) by smtp.gmail.com with ESMTPSA id k6-20020a05651c10a600b0025d620892cdsm2089625ljn.107.2022.08.17.02.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 02:50:55 -0700 (PDT) Date: Wed, 17 Aug 2022 11:50:54 +0200 From: Francisco Iglesias To: Anton Kochkov Cc: qemu-devel@nongnu.org, Pavel Pisa , Vikram Garhwal , Francisco Iglesias , Jason Wang Subject: Re: [PATCH] can: fix Xilinx ZynqMP CAN RX FIFO logic Message-ID: <20220817095053.GA4571@fralle-msi> References: <20220812172420.1946484-1-anton.kochkov@proton.me> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220812172420.1946484-1-anton.kochkov@proton.me> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x12f.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On [2022 Aug 12] Fri 17:25:28, Anton Kochkov wrote: > Function "update_rx_fifo()" should operate on the RX FIFO > registers, not the TX FIFO ones. Hi Anton, Should we update the git commit message to say this is done for readability / keeping it consistent? (the defines have the same values) Otherwise: Reviewed-by: Francisco Iglesias Best regards, Francisco Iglesias > > Signed-off-by: Anton Kochkov > Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123 > --- > hw/net/can/xlnx-zynqmp-can.c | 32 ++++++++++++++++---------------- > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c > index 82ac48cee2..e93e6c5e19 100644 > --- a/hw/net/can/xlnx-zynqmp-can.c > +++ b/hw/net/can/xlnx-zynqmp-can.c > @@ -696,30 +696,30 @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame) > timestamp)); > > /* First 32 bit of the data. */ > - fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT, > - R_TXFIFO_DATA1_DB3_LENGTH, > + fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT, > + R_RXFIFO_DATA1_DB3_LENGTH, > frame->data[0]) | > - deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT, > - R_TXFIFO_DATA1_DB2_LENGTH, > + deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT, > + R_RXFIFO_DATA1_DB2_LENGTH, > frame->data[1]) | > - deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT, > - R_TXFIFO_DATA1_DB1_LENGTH, > + deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT, > + R_RXFIFO_DATA1_DB1_LENGTH, > frame->data[2]) | > - deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT, > - R_TXFIFO_DATA1_DB0_LENGTH, > + deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT, > + R_RXFIFO_DATA1_DB0_LENGTH, > frame->data[3])); > /* Last 32 bit of the data. */ > - fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT, > - R_TXFIFO_DATA2_DB7_LENGTH, > + fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT, > + R_RXFIFO_DATA2_DB7_LENGTH, > frame->data[4]) | > - deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT, > - R_TXFIFO_DATA2_DB6_LENGTH, > + deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT, > + R_RXFIFO_DATA2_DB6_LENGTH, > frame->data[5]) | > - deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT, > - R_TXFIFO_DATA2_DB5_LENGTH, > + deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT, > + R_RXFIFO_DATA2_DB5_LENGTH, > frame->data[6]) | > - deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT, > - R_TXFIFO_DATA2_DB4_LENGTH, > + deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT, > + R_RXFIFO_DATA2_DB4_LENGTH, > frame->data[7])); > > ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); > -- > 2.37.1 > > >