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From: Wilfred Mallawa <wilfred.mallawa@opensource.wdc.com>
To: Alistair.Francis@wdc.com, qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org, Wilfred Mallawa <wilfred.mallawa@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v3 4/4] hw/ssi: ibex_spi: update reg addr
Date: Mon, 22 Aug 2022 09:42:01 +1000	[thread overview]
Message-ID: <20220821234200.34052-5-wilfred.mallawa@opensource.wdc.com> (raw)
In-Reply-To: <20220821234200.34052-1-wilfred.mallawa@opensource.wdc.com>

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].

[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/ssi/ibex_spi_host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index 3809febb0c..bafff8ca1f 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -93,7 +93,7 @@ REG32(ERROR_STATUS, 0x30)
     FIELD(ERROR_STATUS, CMDINVAL, 3, 1)
     FIELD(ERROR_STATUS, CSIDINVAL, 4, 1)
     FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1)
-REG32(EVENT_ENABLE, 0x30)
+REG32(EVENT_ENABLE, 0x34)
     FIELD(EVENT_ENABLE, RXFULL, 0, 1)
     FIELD(EVENT_ENABLE, TXEMPTY, 1, 1)
     FIELD(EVENT_ENABLE, RXWM, 2, 1)
-- 
2.37.2



      parent reply	other threads:[~2022-08-21 23:52 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-21 23:41 [PATCH v3 0/4] hw/ssi: ibex_spi: cleanup and fixup bugs Wilfred Mallawa
2022-08-21 23:41 ` [PATCH v3 1/4] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Wilfred Mallawa
2022-08-21 23:41 ` [PATCH v3 2/4] hw/ssi: ibex_spi: fixup coverity issue Wilfred Mallawa
2022-08-22  3:42   ` Alistair Francis
2022-08-22  3:53     ` Wilfred Mallawa
2022-08-21 23:42 ` [PATCH v3 3/4] hw/ssi: ibex_spi: fixup/add rw1c functionality Wilfred Mallawa
2022-08-21 23:42 ` Wilfred Mallawa [this message]

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