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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 04/10] target/arm: Ignore PMCR.D when PMCR.LC is set
Date: Mon, 22 Aug 2022 14:23:52 +0100	[thread overview]
Message-ID: <20220822132358.3524971-5-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org>

The architecture requires that if PMCR.LC is set (for a 64-bit cycle
counter) then PMCR.D (which enables the clock divider so the counter
ticks every 64 cycles rather than every cycle) should be ignored.  We
were always honouring PMCR.D; fix the bug so we correctly ignore it
in this situation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 59e1280a9cd..f2bf1c52eb2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1172,6 +1172,17 @@ static void pmu_update_irq(CPUARMState *env)
             (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
 }
 
+static bool pmccntr_clockdiv_enabled(CPUARMState *env)
+{
+    /*
+     * Return true if the clock divider is enabled and the cycle counter
+     * is supposed to tick only once every 64 clock cycles. This is
+     * controlled by PMCR.D, but if PMCR.LC is set to enable the long
+     * (64-bit) cycle counter PMCR.D has no effect.
+     */
+    return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD;
+}
+
 /*
  * Ensure c15_ccnt is the guest-visible count so that operations such as
  * enabling/disabling the counter or filtering, modifying the count itself,
@@ -1184,8 +1195,7 @@ static void pmccntr_op_start(CPUARMState *env)
 
     if (pmu_counter_enabled(env, 31)) {
         uint64_t eff_cycles = cycles;
-        if (env->cp15.c9_pmcr & PMCRD) {
-            /* Increment once every 64 processor clock cycles */
+        if (pmccntr_clockdiv_enabled(env)) {
             eff_cycles /= 64;
         }
 
@@ -1228,8 +1238,7 @@ static void pmccntr_op_finish(CPUARMState *env)
 #endif
 
         uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
-        if (env->cp15.c9_pmcr & PMCRD) {
-            /* Increment once every 64 processor clock cycles */
+        if (pmccntr_clockdiv_enabled(env)) {
             prev_cycles /= 64;
         }
         env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;
-- 
2.25.1



  parent reply	other threads:[~2022-08-22 13:33 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-22 13:23 [PATCH v2 00/10] target/arm: Implement FEAT_PMUv3p5 Peter Maydell
2022-08-22 13:23 ` [PATCH v2 01/10] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows Peter Maydell
2022-08-22 13:23 ` [PATCH v2 02/10] target/arm: Correct value returned by pmu_counter_mask() Peter Maydell
2022-08-22 13:23 ` [PATCH v2 03/10] target/arm: Don't mishandle count when enabling or disabling PMU counters Peter Maydell
2022-10-03  8:54   ` Alex Bennée
2022-10-03  9:32     ` Peter Maydell
2022-08-22 13:23 ` Peter Maydell [this message]
2022-08-22 13:23 ` [PATCH v2 05/10] target/arm: Honour MDCR_EL2.HPMD in Secure EL2 Peter Maydell
2022-08-22 13:23 ` [PATCH v2 06/10] target/arm: Detect overflow when calculating next PMU interrupt Peter Maydell
2022-08-22 13:23 ` [PATCH v2 07/10] target/arm: Rename pmu_8_n feature test functions Peter Maydell
2022-08-22 13:23 ` [PATCH v2 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits Peter Maydell
2022-08-22 16:15   ` Richard Henderson
2022-08-22 13:23 ` [PATCH v2 09/10] target/arm: Support 64-bit event counters for FEAT_PMUv3p5 Peter Maydell
2022-08-22 13:23 ` [PATCH v2 10/10] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max' Peter Maydell
2022-08-23 21:53 ` [PATCH v2 00/10] target/arm: Implement FEAT_PMUv3p5 Richard Henderson

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