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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, paul@nowt.org
Subject: [PATCH 06/17] target/i386: add 08-0F, 18-1F opcodes
Date: Wed, 24 Aug 2022 19:31:12 +0200	[thread overview]
Message-ID: <20220824173123.232018-7-pbonzini@redhat.com> (raw)
In-Reply-To: <20220824173123.232018-1-pbonzini@redhat.com>

Using operands named "0-7" for fixed registers wasn't a great idea
in retrospect...  It only makes sense for 1-byte INC/DEC, and those
could even use LoBits instead.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/decode-new.c.inc | 17 ++++++++++++++++-
 target/i386/tcg/decode-old.c.inc |  2 +-
 target/i386/tcg/emit.c.inc       | 10 ++++++++++
 3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 6d0d6a683c..b1e849b332 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -515,9 +515,24 @@ static X86OpEntry A2_00_F7[16][8] = {
 
 static X86OpEntry A2_08_FF[16][8] = {
     {
-        [7] = { .decode = decode_twobyte, .is_decode = true, }
+        X86_OP_ENTRY2(OR, E,b, G,b),
+        X86_OP_ENTRY2(OR, E,v, G,v),
+        X86_OP_ENTRY2(OR, G,b, E,b),
+        X86_OP_ENTRY2(OR, G,v, E,v),
+        X86_OP_ENTRY2(OR, 0,b, I,b),   /* AL, Ib */
+        X86_OP_ENTRY2(OR, 0,v, I,z),   /* rAX, Iz */
+        X86_OP_ENTRYr(PUSH, CS, w, i64),
+        { .decode = decode_twobyte, .is_decode = true, }
     },
     {
+        X86_OP_ENTRY2(SBB, E,b, G,b),
+        X86_OP_ENTRY2(SBB, E,v, G,v),
+        X86_OP_ENTRY2(SBB, G,b, E,b),
+        X86_OP_ENTRY2(SBB, G,v, E,v),
+        X86_OP_ENTRY2(SBB, 0,b, I,b),   /* AL, Ib */
+        X86_OP_ENTRY2(SBB, 0,v, I,z),   /* rAX, Iz */
+        X86_OP_ENTRYr(PUSH, DS, w, i64),
+        X86_OP_ENTRYw(POP, DS, w, i64)
     },
     {
     },
diff --git a/target/i386/tcg/decode-old.c.inc b/target/i386/tcg/decode-old.c.inc
index fb86855501..937975f69a 100644
--- a/target/i386/tcg/decode-old.c.inc
+++ b/target/i386/tcg/decode-old.c.inc
@@ -1821,7 +1821,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
 #else
         use_new &= b <= limit;
 #endif
-        if (use_new && 0) {
+        if (use_new && b <= 0x1f) {
             return disas_insn_new(s, cpu, b);
         }
     case 0x0f:
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 758e468a25..1f799d1f18 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -135,6 +135,11 @@ static void gen_ADD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
     gen_alu_op(s, OP_ADDL, decode->op[0].ot);
 }
 
+static void gen_OR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+    gen_alu_op(s, OP_ORL, decode->op[0].ot);
+}
+
 static void gen_PUSH(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
 {
     gen_push_v(s, decode->op[2].v);
@@ -147,6 +152,11 @@ static void gen_POP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
     gen_pop_update(s, ot);
 }
 
+static void gen_SBB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+    gen_alu_op(s, OP_SBBL, decode->op[0].ot);
+}
+
 static void gen_writeback(DisasContext *s, X86DecodedOp *op)
 {
     switch (op->alu_op_type) {
-- 
2.37.1




  parent reply	other threads:[~2022-08-24 17:42 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-24 17:31 [RFC PATCH 00/17] (The beginning of) a new i386 decoder Paolo Bonzini
2022-08-24 17:31 ` [PATCH 01/17] target/i386: extract old decoder to a separate file Paolo Bonzini
2022-08-24 17:31 ` [PATCH 02/17] target/i386: introduce insn_get_addr Paolo Bonzini
2022-08-25  0:45   ` Richard Henderson
2022-08-24 17:31 ` [PATCH 03/17] target/i386: add core of new i386 decoder Paolo Bonzini
2022-08-25  0:12   ` Richard Henderson
2022-08-25  6:37     ` Paolo Bonzini
2022-08-25  1:47   ` Richard Henderson
2022-08-25  6:44     ` Paolo Bonzini
2022-08-24 17:31 ` [PATCH 04/17] target/i386: add ALU load/writeback core Paolo Bonzini
2022-08-25  0:23   ` Richard Henderson
2022-08-25  6:48     ` Paolo Bonzini
2022-08-25 15:36       ` Richard Henderson
2022-08-24 17:31 ` [PATCH 05/17] target/i386: add 00-07, 10-17 opcodes Paolo Bonzini
2022-08-25  0:27   ` Richard Henderson
2022-08-25  6:49     ` Paolo Bonzini
2022-08-24 17:31 ` Paolo Bonzini [this message]
2022-08-24 17:32 ` [PATCH 07/17] target/i386: add 20-27, 30-37 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 08/17] target/i386: add 28-2f, 38-3f opcodes Paolo Bonzini
2022-08-25  0:28   ` Richard Henderson
2022-08-24 17:32 ` [PATCH 09/17] target/i386: add 40-47, 50-57 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 10/17] target/i386: add 48-4f, 58-5f opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 11/17] target/i386: add 60-67, 70-77 opcodes Paolo Bonzini
2022-08-25  0:33   ` Richard Henderson
2022-08-25  6:58     ` Paolo Bonzini
2022-08-24 17:32 ` [PATCH 12/17] target/i386: add 68-6f, 78-7f opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 13/17] target/i386: add 80-87, 90-97 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 14/17] target/i386: add a0-a7, b0-b7 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 15/17] target/i386: do not clobber A0 in POP translation Paolo Bonzini
2022-08-24 17:32 ` [PATCH 16/17] target/i386: add 88-8f, 98-9f opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 17/17] target/i386: add a8-af, b8-bf opcodes Paolo Bonzini
2022-08-25  0:44   ` Richard Henderson
2022-08-24 23:01 ` [RFC PATCH 00/17] (The beginning of) a new i386 decoder Richard Henderson
2022-08-25  6:36   ` Paolo Bonzini

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