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Wed, 24 Aug 2022 17:32:52 +0000 (UTC) Received: from avogadro.redhat.com (unknown [10.39.192.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9F1C2492C3B; Wed, 24 Aug 2022 17:32:51 +0000 (UTC) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, paul@nowt.org Subject: [PATCH 07/17] target/i386: add 20-27, 30-37 opcodes Date: Wed, 24 Aug 2022 19:32:40 +0200 Message-Id: <20220824173250.232491-1-pbonzini@redhat.com> In-Reply-To: <20220824173123.232018-1-pbonzini@redhat.com> References: <20220824173123.232018-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 16 ++++++++++++++++ target/i386/tcg/emit.c.inc | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index b1e849b332..de0364ac87 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -484,8 +484,24 @@ static X86OpEntry A2_00_F7[16][8] = { X86_OP_ENTRYw(POP, SS, w, i64) }, { + X86_OP_ENTRY2(AND, E,b, G,b), + X86_OP_ENTRY2(AND, E,v, G,v), + X86_OP_ENTRY2(AND, G,b, E,b), + X86_OP_ENTRY2(AND, G,v, E,v), + X86_OP_ENTRY2(AND, 0,b, I,b), /* AL, Ib */ + X86_OP_ENTRY2(AND, 0,v, I,z), /* rAX, Iz */ + {}, + X86_OP_ENTRY0(DAA, i64), }, { + X86_OP_ENTRY2(XOR, E,b, G,b), + X86_OP_ENTRY2(XOR, E,v, G,v), + X86_OP_ENTRY2(XOR, G,b, E,b), + X86_OP_ENTRY2(XOR, G,v, E,v), + X86_OP_ENTRY2(XOR, 0,b, I,b), /* AL, Ib */ + X86_OP_ENTRY2(XOR, 0,v, I,z), /* rAX, Iz */ + {}, + X86_OP_ENTRY0(AAA, i64), }, { }, diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 1f799d1f18..33469098c2 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -125,6 +125,13 @@ static void gen_alu_op(DisasContext *s1, int op, MemOp ot) } } +static void gen_AAA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_update_cc_op(s); + gen_helper_aaa(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); +} + static void gen_ADC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { gen_alu_op(s, OP_ADCL, decode->op[0].ot); @@ -135,6 +142,18 @@ static void gen_ADD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) gen_alu_op(s, OP_ADDL, decode->op[0].ot); } +static void gen_AND(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_alu_op(s, OP_ANDL, decode->op[0].ot); +} + +static void gen_DAA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_update_cc_op(s); + gen_helper_daa(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); +} + static void gen_OR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { gen_alu_op(s, OP_ORL, decode->op[0].ot); @@ -157,6 +176,20 @@ static void gen_SBB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) gen_alu_op(s, OP_SBBL, decode->op[0].ot); } +static void gen_XOR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + /* special case XOR reg, reg */ + if (decode->op[1].alu_op_type == X86_ALU_GPR && + decode->op[2].alu_op_type == X86_ALU_GPR && + decode->op[1].n == decode->op[2].n) { + tcg_gen_movi_tl(s->T0, 0); + gen_op_update1_cc(s); + set_cc_op(s, CC_OP_LOGICB + decode->op[0].ot); + } else { + gen_alu_op(s, OP_XORL, decode->op[0].ot); + } +} + static void gen_writeback(DisasContext *s, X86DecodedOp *op) { switch (op->alu_op_type) { -- 2.37.1