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Wed, 24 Aug 2022 17:32:53 +0000 (UTC) Received: from avogadro.redhat.com (unknown [10.39.192.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id B677F492CA6; Wed, 24 Aug 2022 17:32:52 +0000 (UTC) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, paul@nowt.org Subject: [PATCH 08/17] target/i386: add 28-2f, 38-3f opcodes Date: Wed, 24 Aug 2022 19:32:41 +0200 Message-Id: <20220824173250.232491-2-pbonzini@redhat.com> In-Reply-To: <20220824173123.232018-1-pbonzini@redhat.com> References: <20220824173123.232018-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 16 ++++++++++++++++ target/i386/tcg/decode-old.c.inc | 2 +- target/i386/tcg/emit.c.inc | 22 ++++++++++++++++++++-- 3 files changed, 37 insertions(+), 3 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index de0364ac87..c94cd7ac61 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -551,8 +551,24 @@ static X86OpEntry A2_08_FF[16][8] = { X86_OP_ENTRYw(POP, DS, w, i64) }, { + X86_OP_ENTRY2(SUB, E,b, G,b), + X86_OP_ENTRY2(SUB, E,v, G,v), + X86_OP_ENTRY2(SUB, G,b, E,b), + X86_OP_ENTRY2(SUB, G,v, E,v), + X86_OP_ENTRY2(SUB, 0,b, I,b), /* AL, Ib */ + X86_OP_ENTRY2(SUB, 0,v, I,z), /* rAX, Iz */ + {}, + X86_OP_ENTRY0(DAS, i64), }, { + X86_OP_ENTRY2(SUB, E,b, G,b, nowb), + X86_OP_ENTRY2(SUB, E,v, G,v, nowb), + X86_OP_ENTRY2(SUB, G,b, E,b, nowb), + X86_OP_ENTRY2(SUB, G,v, E,v, nowb), + X86_OP_ENTRY2(SUB, 0,b, I,b, nowb), /* AL, Ib */ + X86_OP_ENTRY2(SUB, 0,v, I,z, nowb), /* rAX, Iz */ + {}, + X86_OP_ENTRY0(AAS, i64), }, { }, diff --git a/target/i386/tcg/decode-old.c.inc b/target/i386/tcg/decode-old.c.inc index 937975f69a..28edb62b5b 100644 --- a/target/i386/tcg/decode-old.c.inc +++ b/target/i386/tcg/decode-old.c.inc @@ -1821,7 +1821,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #else use_new &= b <= limit; #endif - if (use_new && b <= 0x1f) { + if (use_new && b <= 0x3f) { return disas_insn_new(s, cpu, b); } case 0x0f: diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 33469098c2..e247b542ed 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -132,6 +132,13 @@ static void gen_AAA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) set_cc_op(s, CC_OP_EFLAGS); } +static void gen_AAS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_update_cc_op(s); + gen_helper_aas(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); +} + static void gen_ADC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { gen_alu_op(s, OP_ADCL, decode->op[0].ot); @@ -154,6 +161,13 @@ static void gen_DAA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) set_cc_op(s, CC_OP_EFLAGS); } +static void gen_DAS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_update_cc_op(s); + gen_helper_das(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); +} + static void gen_OR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { gen_alu_op(s, OP_ORL, decode->op[0].ot); @@ -176,6 +190,11 @@ static void gen_SBB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) gen_alu_op(s, OP_SBBL, decode->op[0].ot); } +static void gen_SUB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_alu_op(s, OP_SUBL, decode->op[0].ot); +} + static void gen_XOR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { /* special case XOR reg, reg */ @@ -183,8 +202,7 @@ static void gen_XOR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) decode->op[2].alu_op_type == X86_ALU_GPR && decode->op[1].n == decode->op[2].n) { tcg_gen_movi_tl(s->T0, 0); - gen_op_update1_cc(s); - set_cc_op(s, CC_OP_LOGICB + decode->op[0].ot); + set_cc_op(s, CC_OP_CLR); } else { gen_alu_op(s, OP_XORL, decode->op[0].ot); } -- 2.37.1