[PATCH 09/17] target/i386: add 40-47, 50-57 opcodes

[Paolo Bonzini <pbonzini@redhat.com>]

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/decode-new.c.inc | 16 ++++++++++++++++
 target/i386/tcg/emit.c.inc       | 30 +++++++++++++++++++++++++++++-
 target/i386/tcg/translate.c      |  2 ++
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index c94cd7ac61..bbd6ef07a1 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -504,8 +504,24 @@ static X86OpEntry A2_00_F7[16][8] = {
         X86_OP_ENTRY0(AAA, i64),
     },
     {
+        X86_OP_ENTRY1(INC, 0,v, i64),
+        X86_OP_ENTRY1(INC, 1,v, i64),
+        X86_OP_ENTRY1(INC, 2,v, i64),
+        X86_OP_ENTRY1(INC, 3,v, i64),
+        X86_OP_ENTRY1(INC, 4,v, i64),
+        X86_OP_ENTRY1(INC, 5,v, i64),
+        X86_OP_ENTRY1(INC, 6,v, i64),
+        X86_OP_ENTRY1(INC, 7,v, i64),
     },
     {
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
+        X86_OP_ENTRYr(PUSH, LoBits,d64),
     },
     {
     },
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index e247b542ed..d3d0f893fb 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -91,7 +91,30 @@ static void gen_alu_op(DisasContext *s1, int op, MemOp ot)
         gen_op_update2_cc(s1);
         set_cc_op(s1, CC_OP_SUBB + ot);
         break;
-    default:
+    case OP_DECL:
+        tcg_gen_movi_tl(s1->T1, -1);
+        if (s1->prefix & PREFIX_LOCK) {
+            tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T1,
+                                        s1->mem_index, ot | MO_LE);
+        } else {
+            tcg_gen_add_tl(s1->T0, s1->T0, s1->T1);
+        }
+        gen_compute_eflags_c(s1, cpu_cc_src);
+        tcg_gen_mov_tl(cpu_cc_dst, s1->T0);
+        set_cc_op(s1, CC_OP_DECB + ot);
+        break;
+    case OP_INCL:
+        tcg_gen_movi_tl(s1->T1, 1);
+        if (s1->prefix & PREFIX_LOCK) {
+            tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T1,
+                                        s1->mem_index, ot | MO_LE);
+        } else {
+            tcg_gen_add_tl(s1->T0, s1->T0, s1->T1);
+        }
+        gen_compute_eflags_c(s1, cpu_cc_src);
+        tcg_gen_mov_tl(cpu_cc_dst, s1->T0);
+        set_cc_op(s1, CC_OP_INCB + ot);
+        break;
     case OP_ANDL:
         if (s1->prefix & PREFIX_LOCK) {
             tcg_gen_atomic_and_fetch_tl(s1->T0, s1->A0, s1->T1,
@@ -168,6 +191,11 @@ static void gen_DAS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
     set_cc_op(s, CC_OP_EFLAGS);
 }
 
+static void gen_INC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+    gen_alu_op(s, OP_INCL, decode->op[0].ot);
+}
+
 static void gen_OR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
 {
     gen_alu_op(s, OP_ORL, decode->op[0].ot);
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9b925c7ec8..d0a8c0becb 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -223,6 +223,8 @@ enum {
     OP_SUBL,
     OP_XORL,
     OP_CMPL,
+    OP_INCL,
+    OP_DECL,
 };
 
 /* i386 shift ops */
-- 
2.37.1