From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, paul@nowt.org
Subject: [PATCH 11/17] target/i386: add 60-67, 70-77 opcodes
Date: Wed, 24 Aug 2022 19:32:44 +0200 [thread overview]
Message-ID: <20220824173250.232491-5-pbonzini@redhat.com> (raw)
In-Reply-To: <20220824173123.232018-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 30 +++++++++++++
target/i386/tcg/emit.c.inc | 77 ++++++++++++++++++++++++++++++++
2 files changed, 107 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 586894e4ee..161a3b1554 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -462,6 +462,20 @@ static void decode_twobyte(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
}
}
+static void decode_group_0x63(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
+{
+ static X86OpEntry arpl = X86_OP_ENTRY2(ARPL, E,w, G,w, .special = X86_SPECIAL_ProtMode);
+ static X86OpEntry mov = X86_OP_ENTRY3(MOV, G,v, E,v, None, None);
+ static X86OpEntry movsxd = X86_OP_ENTRY3(MOVSXD, G,v, E,d, None, None);
+ if (!CODE64(s)) {
+ *entry = arpl;
+ } else if (REX_W(s)) {
+ *entry = movsxd;
+ } else {
+ *entry = mov;
+ }
+}
+
static X86OpEntry A2_00_F7[16][8] = {
{
X86_OP_ENTRY2(ADD, E,b, G,b),
@@ -524,8 +538,24 @@ static X86OpEntry A2_00_F7[16][8] = {
X86_OP_ENTRYr(PUSH, LoBits,d64),
},
{
+ X86_OP_ENTRY0(PUSHA, i64),
+ X86_OP_ENTRY0(POPA, i64),
+ X86_OP_ENTRY2(BOUND, G,v, M,a, i64),
+ X86_OP_GROUP0(0x63),
+ {},
+ {},
+ {},
+ {},
},
{
+ X86_OP_ENTRYr(Jcc, J,b),
+ X86_OP_ENTRYr(Jcc, J,b),
+ X86_OP_ENTRYr(Jcc, J,b),
+ X86_OP_ENTRYr(Jcc, J,b),
+ X86_OP_ENTRYr(Jcc, J,b),
+ X86_OP_ENTRYr(Jcc, J,b),
+ X86_OP_ENTRYr(Jcc, J,b),
+ X86_OP_ENTRYr(Jcc, J,b),
},
{
},
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index a76d6820e1..cf606e74c7 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -177,6 +177,56 @@ static void gen_AND(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_alu_op(s, OP_ANDL, decode->op[0].ot);
}
+static void gen_ARPL(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ TCGLabel *label1;
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
+ TCGv a0;
+
+ if (decode->op[0].alu_op_type == X86_ALU_MEM) {
+ a0 = tcg_temp_local_new();
+ tcg_gen_mov_tl(a0, s->A0);
+ decode->op[0].v = a0;
+ } else {
+ a0 = NULL;
+ }
+
+ gen_compute_eflags(s);
+ tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
+
+ tcg_gen_mov_tl(t0, s->T0);
+ tcg_gen_andi_tl(s->T0, s->T0, 3);
+ tcg_gen_andi_tl(t1, s->T1, 3);
+ label1 = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_GE, s->T0, t1, label1);
+ tcg_gen_andi_tl(t0, t0, ~3);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_Z);
+ gen_set_label(label1);
+
+ /* Do writeback here due to temp locals. */
+ decode->op[0].alu_op_type = X86_ALU_SKIP;
+ if (a0) {
+ gen_op_st_v(s, MO_16, t0, a0);
+ tcg_temp_free(a0);
+ } else {
+ gen_op_mov_reg_v(s, MO_16, decode->op[0].n, t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void gen_BOUND(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
+ if (decode->op[1].ot == MO_16) {
+ gen_helper_boundw(cpu_env, s->A0, s->tmp2_i32);
+ } else {
+ gen_helper_boundl(cpu_env, s->A0, s->tmp2_i32);
+ }
+}
+
static void gen_DAA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_update_cc_op(s);
@@ -201,6 +251,23 @@ static void gen_INC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_alu_op(s, OP_INCL, decode->op[0].ot);
}
+static void gen_Jcc(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ target_ulong next_eip = s->pc - s->cs_base;
+ gen_bnd_jmp(s);
+ gen_jcc(s, decode->b & 0xf, decode->immediate, next_eip);
+}
+
+static void gen_MOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ /* nothing to do! */
+}
+
+static void gen_MOVSXD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ tcg_gen_ext32s_tl(s->T0, s->T0);
+}
+
static void gen_OR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_alu_op(s, OP_ORL, decode->op[0].ot);
@@ -211,6 +278,11 @@ static void gen_PUSH(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_push_v(s, decode->op[2].v);
}
+static void gen_PUSHA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_pusha(s);
+}
+
static void gen_POP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = gen_pop_T0(s);
@@ -218,6 +290,11 @@ static void gen_POP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_pop_update(s, ot);
}
+static void gen_POPA(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_popa(s);
+}
+
static void gen_SBB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_alu_op(s, OP_SBBL, decode->op[0].ot);
--
2.37.1
next prev parent reply other threads:[~2022-08-24 17:56 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 17:31 [RFC PATCH 00/17] (The beginning of) a new i386 decoder Paolo Bonzini
2022-08-24 17:31 ` [PATCH 01/17] target/i386: extract old decoder to a separate file Paolo Bonzini
2022-08-24 17:31 ` [PATCH 02/17] target/i386: introduce insn_get_addr Paolo Bonzini
2022-08-25 0:45 ` Richard Henderson
2022-08-24 17:31 ` [PATCH 03/17] target/i386: add core of new i386 decoder Paolo Bonzini
2022-08-25 0:12 ` Richard Henderson
2022-08-25 6:37 ` Paolo Bonzini
2022-08-25 1:47 ` Richard Henderson
2022-08-25 6:44 ` Paolo Bonzini
2022-08-24 17:31 ` [PATCH 04/17] target/i386: add ALU load/writeback core Paolo Bonzini
2022-08-25 0:23 ` Richard Henderson
2022-08-25 6:48 ` Paolo Bonzini
2022-08-25 15:36 ` Richard Henderson
2022-08-24 17:31 ` [PATCH 05/17] target/i386: add 00-07, 10-17 opcodes Paolo Bonzini
2022-08-25 0:27 ` Richard Henderson
2022-08-25 6:49 ` Paolo Bonzini
2022-08-24 17:31 ` [PATCH 06/17] target/i386: add 08-0F, 18-1F opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 07/17] target/i386: add 20-27, 30-37 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 08/17] target/i386: add 28-2f, 38-3f opcodes Paolo Bonzini
2022-08-25 0:28 ` Richard Henderson
2022-08-24 17:32 ` [PATCH 09/17] target/i386: add 40-47, 50-57 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 10/17] target/i386: add 48-4f, 58-5f opcodes Paolo Bonzini
2022-08-24 17:32 ` Paolo Bonzini [this message]
2022-08-25 0:33 ` [PATCH 11/17] target/i386: add 60-67, 70-77 opcodes Richard Henderson
2022-08-25 6:58 ` Paolo Bonzini
2022-08-24 17:32 ` [PATCH 12/17] target/i386: add 68-6f, 78-7f opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 13/17] target/i386: add 80-87, 90-97 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 14/17] target/i386: add a0-a7, b0-b7 opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 15/17] target/i386: do not clobber A0 in POP translation Paolo Bonzini
2022-08-24 17:32 ` [PATCH 16/17] target/i386: add 88-8f, 98-9f opcodes Paolo Bonzini
2022-08-24 17:32 ` [PATCH 17/17] target/i386: add a8-af, b8-bf opcodes Paolo Bonzini
2022-08-25 0:44 ` Richard Henderson
2022-08-24 23:01 ` [RFC PATCH 00/17] (The beginning of) a new i386 decoder Richard Henderson
2022-08-25 6:36 ` Paolo Bonzini
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