From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
Atish Patra <atishp@rivosinc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v14 2/5] target/riscv: Simplify counter predicate function
Date: Wed, 24 Aug 2022 15:16:58 -0700 [thread overview]
Message-ID: <20220824221701.41932-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20220824221701.41932-1-atishp@rivosinc.com>
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/csr.c | 110 ++++-----------------------------------------
1 file changed, 9 insertions(+), 101 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 888ddfc4dd4b..2151e280a868 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -75,6 +75,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
+ target_ulong ctr_mask;
int base_csrno = CSR_CYCLE;
bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
@@ -83,122 +84,29 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
+ ctr_mask = BIT(ctr_index);
if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
(csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
goto skip_ext_pmu_check;
}
- if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) {
+ if (!(cpu->pmu_avail_ctrs & ctr_mask)) {
/* No counter is enabled in PMU or the counter is out of range */
return RISCV_EXCP_ILLEGAL_INST;
}
skip_ext_pmu_check:
- if (env->priv == PRV_S) {
- switch (csrno) {
- case CSR_CYCLE:
- if (!get_field(env->mcounteren, COUNTEREN_CY)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- case CSR_TIME:
- if (!get_field(env->mcounteren, COUNTEREN_TM)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- case CSR_INSTRET:
- if (!get_field(env->mcounteren, COUNTEREN_IR)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
- if (!get_field(env->mcounteren, 1 << ctr_index)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- }
- if (rv32) {
- switch (csrno) {
- case CSR_CYCLEH:
- if (!get_field(env->mcounteren, COUNTEREN_CY)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- case CSR_TIMEH:
- if (!get_field(env->mcounteren, COUNTEREN_TM)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- case CSR_INSTRETH:
- if (!get_field(env->mcounteren, COUNTEREN_IR)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
- if (!get_field(env->mcounteren, 1 << ctr_index)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- break;
- }
- }
+ if (((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) ||
+ ((env->priv == PRV_U) && (!get_field(env->scounteren, ctr_mask)))) {
+ return RISCV_EXCP_ILLEGAL_INST;
}
if (riscv_cpu_virt_enabled(env)) {
- switch (csrno) {
- case CSR_CYCLE:
- if (!get_field(env->hcounteren, COUNTEREN_CY) &&
- get_field(env->mcounteren, COUNTEREN_CY)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- case CSR_TIME:
- if (!get_field(env->hcounteren, COUNTEREN_TM) &&
- get_field(env->mcounteren, COUNTEREN_TM)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- case CSR_INSTRET:
- if (!get_field(env->hcounteren, COUNTEREN_IR) &&
- get_field(env->mcounteren, COUNTEREN_IR)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
- if (!get_field(env->hcounteren, 1 << ctr_index) &&
- get_field(env->mcounteren, 1 << ctr_index)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- }
- if (rv32) {
- switch (csrno) {
- case CSR_CYCLEH:
- if (!get_field(env->hcounteren, COUNTEREN_CY) &&
- get_field(env->mcounteren, COUNTEREN_CY)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- case CSR_TIMEH:
- if (!get_field(env->hcounteren, COUNTEREN_TM) &&
- get_field(env->mcounteren, COUNTEREN_TM)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- case CSR_INSTRETH:
- if (!get_field(env->hcounteren, COUNTEREN_IR) &&
- get_field(env->mcounteren, COUNTEREN_IR)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
- if (!get_field(env->hcounteren, 1 << ctr_index) &&
- get_field(env->mcounteren, 1 << ctr_index)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- break;
- }
+ if (!get_field(env->hcounteren, ctr_mask) &&
+ get_field(env->mcounteren, ctr_mask)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
#endif
--
2.25.1
next prev parent reply other threads:[~2022-08-24 22:32 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 22:16 [PATCH v14 0/5] Improve PMU support Atish Patra
2022-08-24 22:16 ` [PATCH v14 1/5] target/riscv: Add sscofpmf extension support Atish Patra
2022-08-24 22:16 ` Atish Patra [this message]
2022-08-24 22:16 ` [PATCH v14 3/5] target/riscv: Add few cache related PMU events Atish Patra
2022-08-24 22:17 ` [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-11-24 13:16 ` Conor Dooley
2022-11-28 20:16 ` Atish Kumar Patra
2022-11-28 20:38 ` Conor.Dooley
2022-11-28 20:41 ` Atish Kumar Patra
2022-11-28 21:10 ` Conor.Dooley
2022-11-29 7:08 ` Andrew Jones
2022-11-29 7:32 ` Conor.Dooley
2022-11-29 9:27 ` Atish Kumar Patra
2022-11-29 9:42 ` Conor.Dooley
2022-11-29 23:54 ` Conor.Dooley
2022-11-30 8:13 ` Atish Kumar Patra
2022-11-30 8:31 ` Conor.Dooley
2022-08-24 22:17 ` [PATCH v14 5/5] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-09-19 22:08 ` [PATCH v14 0/5] Improve PMU support Alistair Francis
2022-09-20 8:36 ` Atish Kumar Patra
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