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From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>
Cc: Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>
Subject: [RFC PATCH 0/3] CXL Performance Monitoring Unit QEMU emulation.
Date: Wed, 31 Aug 2022 16:33:33 +0100	[thread overview]
Message-ID: <20220831153336.16165-1-Jonathan.Cameron@huawei.com> (raw)

CXL 3.0 introduces a CXL Performance Monitoring Unit.
(13.2 Performance Monitoring)
These unit may be present in any CXL component but for now the kernel
code only supports them in Type 3 Memory devices.

Add basic emulation of such units and instantiate 2 in each CXL Type 3 device.

Kernel driver was developed against this fairly minimal emulation.
https://lore.kernel.org/linux-cxl/20220824103617.21781-1-Jonathan.Cameron@huawei.com/T/#t

For now, this RFC is both to seek general feedback on the approach used and to
provide a platform for testing the kernel driver against.

Note that the CPMU definition is extremely flexible and configuring the
available options via the QEMU command line may be impractical.
To avoid that complexity, this configuration is currently fixed.
This code provides a pair of identical CPMU instances on each CXL type 3
device which were constructed to hit some of the corner cases in the
enumeration code.

The counters themselves just get bigger in a fashion designed to overflow
fairly quickly. Actual values are meaningless.  For now there is no
control over the existence of CPMU instances.  Likely we will add at least
an option to enable them or not.

Precursor patch to add MSI/MSIX support may well merge as part of a
different series, but is needed to apply this to 7.1.

Jonathan Cameron (3):
  hw/mem/cxl-type3: Add MSI/MSIX support
  hw/cxl: Switch to using an array for CXLRegisterLocator base
    addresses.
  hw/cxl: CXL Performance Monitoring Unit (CPMU) Emulation

 hw/cxl/cxl-cpmu.c              | 295 +++++++++++++++++++++++++++++++++
 hw/cxl/meson.build             |   1 +
 hw/mem/cxl_type3.c             |  31 +++-
 hw/pci-bridge/cxl_downstream.c |   4 +-
 hw/pci-bridge/cxl_root_port.c  |   4 +-
 hw/pci-bridge/cxl_upstream.c   |   4 +-
 include/hw/cxl/cxl.h           |   1 +
 include/hw/cxl/cxl_cpmu.h      |  99 +++++++++++
 include/hw/cxl/cxl_device.h    |  31 +++-
 include/hw/cxl/cxl_pci.h       |  15 +-
 10 files changed, 463 insertions(+), 22 deletions(-)
 create mode 100644 hw/cxl/cxl-cpmu.c
 create mode 100644 include/hw/cxl/cxl_cpmu.h

-- 
2.32.0



             reply	other threads:[~2022-08-31 15:36 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-31 15:33 Jonathan Cameron via [this message]
2022-08-31 15:33 ` [RFC PATCH 1/3] hw/mem/cxl-type3: Add MSI/MSIX support Jonathan Cameron via
2022-08-31 15:33 ` [RFC PATCH 2/3] hw/cxl: Switch to using an array for CXLRegisterLocator base addresses Jonathan Cameron via
2022-08-31 15:33 ` [RFC PATCH 3/3] hw/cxl: CXL Performance Monitoring Unit (CPMU) Emulation Jonathan Cameron via

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