[PATCH 19/37] target/i386: Introduce 256-bit vector helpers

qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed

From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PATCH 19/37] target/i386: Introduce 256-bit vector helpers
Date: Mon, 12 Sep 2022 01:03:59 +0200	[thread overview]
Message-ID: <20220911230418.340941-20-pbonzini@redhat.com> (raw)
In-Reply-To: <20220911230418.340941-1-pbonzini@redhat.com>

The new implementation of SSE will cover AVX from the get go, because
all the work for the helper functions is already done.  We just need to
build them.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/helper.h         | 2 ++
 target/i386/ops_sse.h        | 5 +++++
 target/i386/ops_sse_header.h | 4 ++++
 target/i386/tcg/fpu_helper.c | 3 +++
 4 files changed, 14 insertions(+)

diff --git a/target/i386/helper.h b/target/i386/helper.h
index ac3b4d1ee3..3da5df98b9 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -218,6 +218,8 @@ DEF_HELPER_3(movq, void, env, ptr, ptr)
 #include "ops_sse_header.h"
 #define SHIFT 1
 #include "ops_sse_header.h"
+#define SHIFT 2
+#include "ops_sse_header.h"
 
 DEF_HELPER_3(rclb, tl, env, tl, tl)
 DEF_HELPER_3(rclw, tl, env, tl, tl)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 93cee330d2..4f72164c0f 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -35,7 +35,11 @@
 #define W(n) ZMM_W(n)
 #define L(n) ZMM_L(n)
 #define Q(n) ZMM_Q(n)
+#if SHIFT == 1
 #define SUFFIX _xmm
+#else
+#define SUFFIX _ymm
+#endif
 #endif
 
 #define LANE_WIDTH (SHIFT ? 16 : 8)
@@ -2379,6 +2383,7 @@ void glue(helper_aeskeygenassist, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
 
 #undef SSE_HELPER_S
 
+#undef LANE_WIDTH
 #undef SHIFT
 #undef XMM_ONLY
 #undef Reg
diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 4bef536edb..4041816945 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -21,7 +21,11 @@
 #define SUFFIX _mmx
 #else
 #define Reg ZMMReg
+#if SHIFT == 1
 #define SUFFIX _xmm
+#else
+#define SUFFIX _ymm
+#endif
 #endif
 
 #define dh_alias_Reg ptr
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 48bf0c5cf8..819e920ec6 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -3053,3 +3053,6 @@ void helper_movq(CPUX86State *env, void *d, void *s)
 
 #define SHIFT 1
 #include "ops_sse.h"
+
+#define SHIFT 2
+#include "ops_sse.h"
-- 
2.37.2

next prev parent reply	other threads:[~2022-09-11 23:22 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
2022-09-11 23:03 ` [PATCH 01/37] target/i386: Define XMMReg and access macros, align ZMM registers Paolo Bonzini
2022-09-11 23:03 ` [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
2022-09-12  8:33   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive Paolo Bonzini
2022-09-12  8:37   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 04/37] target/i386: introduce insn_get_addr Paolo Bonzini
2022-09-12  8:39   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 05/37] target/i386: add core of new i386 decoder Paolo Bonzini
2022-09-12  9:27   ` Richard Henderson
2022-09-12 10:54   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 06/37] target/i386: add ALU load/writeback core Paolo Bonzini
2022-09-12 10:02   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext Paolo Bonzini
2022-09-12 10:02   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 08/37] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
2022-09-12 10:05   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 09/37] target/i386: add AVX_EN hflag Paolo Bonzini
2022-09-12 10:06   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
2022-09-12 10:39   ` Richard Henderson
2022-09-12 10:42   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 11/37] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
2022-09-12 10:51   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
2022-09-12 11:04   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 13/37] target/i386: remove scalar VEX instructions from old decoder Paolo Bonzini
2022-09-12 11:06   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 14/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
2022-09-12 11:09   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 15/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
2022-09-12 11:11   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 16/37] target/i386: support operand merging in binary scalar helpers Paolo Bonzini
2022-09-12 11:11   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 17/37] target/i386: provide 3-operand versions of unary " Paolo Bonzini
2022-09-12 11:14   ` Richard Henderson
2022-09-11 23:03 ` [PATCH 18/37] target/i386: implement additional AVX comparison operators Paolo Bonzini
2022-09-12 11:19   ` Richard Henderson
2022-09-11 23:03 ` Paolo Bonzini [this message]
2022-09-12 11:19   ` [PATCH 19/37] target/i386: Introduce 256-bit vector helpers Richard Henderson
2022-09-11 23:04 ` [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
2022-09-12 11:41   ` Richard Henderson
2022-09-13 10:56     ` Paolo Bonzini
2022-09-13 11:35       ` Richard Henderson
2022-09-12 13:01   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 21/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
2022-09-12 13:19   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 22/37] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
2022-09-12 13:46   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
2022-09-12 13:56   ` Richard Henderson
2022-09-14 16:17     ` Paolo Bonzini
2022-09-11 23:04 ` [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
2022-09-12 14:29   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
2022-09-12 15:06   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, " Paolo Bonzini
2022-09-12 15:33   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
2022-09-13  8:16   ` Richard Henderson
2022-09-14 22:59     ` Paolo Bonzini
2022-09-15  6:48       ` Richard Henderson
2022-09-11 23:04 ` [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
2022-09-13  9:31   ` Richard Henderson
2022-09-14 17:04     ` Paolo Bonzini
2022-09-15  6:50       ` Richard Henderson
2022-09-11 23:04 ` [PATCH 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, " Paolo Bonzini
2022-09-13  9:44   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
2022-09-13 10:14   ` Richard Henderson
2022-09-14 22:45     ` Paolo Bonzini
2022-09-15  6:51       ` Richard Henderson
2022-09-13 10:38   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
2022-09-13 10:24   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers Paolo Bonzini
2022-09-13 10:27   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
2022-09-13 10:28   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
2022-09-13 10:32   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 35/37] tests/tcg: extend SSE tests to AVX Paolo Bonzini
2022-09-13 10:33   ` Richard Henderson
2022-09-11 23:04 ` [PATCH 36/37] target/i386: move 3DNow completely out of gen_sse Paolo Bonzini
2022-09-13 10:34   ` Richard Henderson
2022-09-13 10:39 ` [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Richard Henderson

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:ac3b4d1ee dfblob:3da5df98b dfblob:93cee330d dfblob:4f72164c0
dfblob:4bef536ed dfblob:404181694 dfblob:48bf0c5cf dfblob:819e920ec )
 OR (
bs:"[PATCH 19/37] target/i386: Introduce 256-bit vector helpers" )
	(help)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220911230418.340941-20-pbonzini@redhat.com \
    --to=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Be sure your reply has a Subject: header at the top and a blank line before the message body.

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).