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[93.44.39.154]) by smtp.gmail.com with ESMTPSA id r12-20020aa7da0c000000b004511957d075sm4660022eds.80.2022.09.11.16.05.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 16:05:53 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, add AVX Date: Mon, 12 Sep 2022 01:04:11 +0200 Message-Id: <20220911230418.340941-32-pbonzini@redhat.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220911230418.340941-1-pbonzini@redhat.com> References: <20220911230418.340941-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Here the code is a bit uglier due to the truncation and extension of registers to and from 32-bit. Otherwise there is nothing special going on. Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 54 ++++++++++++++ target/i386/tcg/emit.c.inc | 120 +++++++++++++++++++++++++++++++ target/i386/tcg/translate.c | 1 + 3 files changed, 175 insertions(+) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index 268ccb886f..383a425ccd 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -620,6 +620,51 @@ static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui } } +static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) +{ + static const X86OpEntry opcodes_0F2A[4] = { + X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q, vex4), + X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q, vex4), + X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3), + X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3), + }; + *entry = *decode_by_prefix(s, opcodes_0F2A); +} + +static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) +{ + static const X86OpEntry opcodes_0F2B[4] = { + X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS */ + X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD */ + X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4), + X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */ + }; + + *entry = *decode_by_prefix(s, opcodes_0F2B); +} + +static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) +{ + static const X86OpEntry opcodes_0F2C[4] = { + X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,x, vex4), + X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,x, vex4), + X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,x, vex3), + X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,x, vex3), + }; + *entry = *decode_by_prefix(s, opcodes_0F2C); +} + +static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) +{ + static const X86OpEntry opcodes_0F2D[4] = { + X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,x, vex4), + X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,x, vex4), + X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,x, vex3), + X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,x, vex3), + }; + *entry = *decode_by_prefix(s, opcodes_0F2D); +} + static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) { if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) { @@ -672,6 +717,15 @@ static const X86OpEntry opcodes_0F[256] = { [0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), [0x77] = X86_OP_ENTRY0(EMMS_VZERO, vex8), + [0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */ + [0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */ + [0x2A] = X86_OP_GROUP0(0F2A), + [0x2B] = X86_OP_GROUP0(0F2B), + [0x2C] = X86_OP_GROUP0(0F2C), + [0x2D] = X86_OP_GROUP0(0F2D), + [0x2E] = X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex4 p_00_66), + [0x2F] = X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex4 p_00_66), + [0x38] = X86_OP_GROUP0(0F38), [0x3a] = X86_OP_GROUP0(0F3A), diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 2319368cb5..d61b43f21c 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -921,6 +921,36 @@ static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_const_i32(8 << ot)); } +static void gen_CVTPI2Px(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_helper_enter_mmx(cpu_env); + if (s->prefix & PREFIX_DATA) { + gen_helper_cvtpi2pd(cpu_env, s->ptr0, s->ptr2); + } else { + gen_helper_cvtpi2ps(cpu_env, s->ptr0, s->ptr2); + } +} + +static void gen_CVTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_helper_enter_mmx(cpu_env); + if (s->prefix & PREFIX_DATA) { + gen_helper_cvtpd2pi(cpu_env, s->ptr0, s->ptr2); + } else { + gen_helper_cvtps2pi(cpu_env, s->ptr0, s->ptr2); + } +} + +static void gen_CVTTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_helper_enter_mmx(cpu_env); + if (s->prefix & PREFIX_DATA) { + gen_helper_cvttpd2pi(cpu_env, s->ptr0, s->ptr2); + } else { + gen_helper_cvttps2pi(cpu_env, s->ptr0, s->ptr2); + } +} + static void gen_EMMS_VZERO(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { if (!(s->prefix & PREFIX_VEX)) { @@ -1863,6 +1893,14 @@ static inline void gen_VCMP(DisasContext *s, CPUX86State *env, X86DecodedInsn *d gen_helper_cmp_funcs[index][b](cpu_env, s->ptr0, s->ptr1, s->ptr2); } +static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + SSEFunc_0_epp fn; + fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss; + fn(cpu_env, s->ptr1, s->ptr2); + set_cc_op(s, CC_OP_EFLAGS); +} + static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { gen_unary_fp_sse(s, env, decode, @@ -1871,6 +1909,80 @@ static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec gen_helper_cvtsd2ss, gen_helper_cvtss2sd); } +static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + int vec_len = sse_vec_len(s, decode); + MemOp ot = decode->op[2].ot; + TCGv_i32 in; + + tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); +#ifdef TARGET_X86_64 + if (ot == MO_64) { + if (s->prefix & PREFIX_REPNZ) { + gen_helper_cvtsq2sd(cpu_env, s->ptr0, s->T1); + } else { + gen_helper_cvtsq2ss(cpu_env, s->ptr0, s->T1); + } + return; + } + in = s->tmp2_i32; + tcg_gen_trunc_tl_i32(in, s->T1); +#else + in = s->T1; +#endif + + if (s->prefix & PREFIX_REPNZ) { + gen_helper_cvtsi2sd(cpu_env, s->ptr0, in); + } else { + gen_helper_cvtsi2ss(cpu_env, s->ptr0, in); + } +} + +static inline void gen_VCVTtSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode, + SSEFunc_i_ep ss2si, SSEFunc_l_ep ss2sq, + SSEFunc_i_ep sd2si, SSEFunc_l_ep sd2sq) +{ + MemOp ot = decode->op[0].ot; + TCGv_i32 out; + +#ifdef TARGET_X86_64 + if (ot == MO_64) { + if (s->prefix & PREFIX_REPNZ) { + sd2sq(s->T0, cpu_env, s->ptr2); + } else { + ss2sq(s->T0, cpu_env, s->ptr2); + } + return; + } + + out = s->tmp2_i32; +#else + out = s->T0; +#endif + if (s->prefix & PREFIX_REPNZ) { + sd2si(out, cpu_env, s->ptr2); + } else { + ss2si(out, cpu_env, s->ptr2); + } +#ifdef TARGET_X86_64 + tcg_gen_extu_i32_tl(s->T0, out); +#endif +} + +static void gen_VCVTSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_VCVTtSx2SI(s, env, decode, + gen_helper_cvtss2si, gen_helper_cvtss2sq, + gen_helper_cvtsd2si, gen_helper_cvtsd2sq); +} + +static void gen_VCVTTSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_VCVTtSx2SI(s, env, decode, + gen_helper_cvttss2si, gen_helper_cvttss2sq, + gen_helper_cvttsd2si, gen_helper_cvttsd2sq); +} + static void gen_VCVTpd_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { SSEFunc_0_epp fn = NULL; @@ -2162,4 +2274,12 @@ static inline void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn * tcg_temp_free_i32(imm); } +static void gen_VUCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + SSEFunc_0_epp fn; + fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss; + fn(cpu_env, s->ptr1, s->ptr2); + set_cc_op(s, CC_OP_EFLAGS); +} + #define gen_VXOR gen_PXOR diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index bb5f74140c..f312663110 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -4669,6 +4669,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (use_new && (b == 0x138 || b == 0x13a || (b >= 0x110 && b <= 0x117) || + (b >= 0x128 && b <= 0x12f) || (b >= 0x150 && b <= 0x17f) || b == 0x1c2 || (b >= 0x1c4 && b <= 0x1c6) || (b >= 0x1d0 && b <= 0x1ff))) { -- 2.37.2