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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: laurent@vivier.eu, mark.cave-ayland@ilande.co.uk
Subject: [PATCH 2/2] target/m68k: Perform writback before modifying SR
Date: Tue, 13 Sep 2022 15:28:18 +0100	[thread overview]
Message-ID: <20220913142818.7802-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220913142818.7802-1-richard.henderson@linaro.org>

Writes to SR may change security state, which may involve
a swap of %ssp with %usp as reflected in %a7.  Finish the
writeback of %sp@+ before swapping stack pointers.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1206
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/m68k/translate.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 87044382c3..8506da0a0b 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2285,9 +2285,9 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
         tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
         tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
     } else {
-        TCGv sr = tcg_const_i32(val);
-        gen_helper_set_sr(cpu_env, sr);
-        tcg_temp_free(sr);
+        /* Must writeback before changing security state. */
+        do_writebacks(s);
+        gen_helper_set_sr(cpu_env, tcg_constant_i32(val));
     }
     set_cc_op(s, CC_OP_FLAGS);
 }
@@ -2297,6 +2297,8 @@ static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
     if (ccr_only) {
         gen_helper_set_ccr(cpu_env, val);
     } else {
+        /* Must writeback before changing security state. */
+        do_writebacks(s);
         gen_helper_set_sr(cpu_env, val);
     }
     set_cc_op(s, CC_OP_FLAGS);
-- 
2.34.1



  parent reply	other threads:[~2022-09-13 14:31 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 14:28 [PATCH 0/2] target/m68k: fix two writes to %sr Richard Henderson
2022-09-13 14:28 ` [PATCH 1/2] target/m68k: Fix MACSR to CCR Richard Henderson
2022-09-13 14:59   ` Laurent Vivier
2022-09-21 13:01   ` Laurent Vivier
2022-09-13 14:28 ` Richard Henderson [this message]
2022-09-13 14:47   ` [PATCH 2/2] target/m68k: Perform writback before modifying SR Laurent Vivier
2022-09-13 16:24   ` Mark Cave-Ayland
2022-09-21 13:02   ` Laurent Vivier
2022-09-13 16:29 ` [PATCH 0/2] target/m68k: fix two writes to %sr Mark Cave-Ayland
2022-09-13 16:35   ` Laurent Vivier
2022-09-13 17:15   ` Richard Henderson
2022-09-14 16:48   ` Howard Spoelstra
2022-09-14 17:08     ` Howard Spoelstra

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