From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: [PULL 18/20] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'
Date: Wed, 14 Sep 2022 12:52:15 +0100 [thread overview]
Message-ID: <20220914115217.117532-20-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220914115217.117532-1-richard.henderson@linaro.org>
From: Peter Maydell <peter.maydell@linaro.org>
Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
compliant PMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-11-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 2 +-
target/arm/cpu_tcg.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 811358fd0a..be7bbffe59 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -53,6 +53,7 @@ the following architecture extensions:
- FEAT_PMULL (PMULL, PMULL2 instructions)
- FEAT_PMUv3p1 (PMU Extensions v3.1)
- FEAT_PMUv3p4 (PMU Extensions v3.4)
+- FEAT_PMUv3p5 (PMU Extensions v3.5)
- FEAT_RAS (Reliability, availability, and serviceability)
- FEAT_RASv1p1 (RAS Extension v1.1)
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 3ac5e197a7..e6314e86d2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1152,7 +1152,7 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64dfr0;
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
cpu->isar.id_aa64dfr0 = t;
t = cpu->isar.id_aa64smfr0;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index b714c61d94..98b5ba2160 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -85,7 +85,7 @@ void aa32_max_features(ARMCPU *cpu)
t = cpu->isar.id_dfr0;
t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
cpu->isar.id_dfr0 = t;
}
--
2.34.1
next prev parent reply other threads:[~2022-09-14 13:09 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 11:51 [PULL 00/20] target-arm.next patch queue Richard Henderson
2022-09-14 11:51 ` [PULL 01/20] target/arm: Add cortex-a35 Richard Henderson
2022-09-14 11:51 ` [PATCH] target/arm: Do alignment check when translation disabled Richard Henderson
2022-09-22 15:31 ` Peter Maydell
2022-09-28 15:52 ` Richard Henderson
2022-09-14 11:51 ` [PULL 02/20] hw/arm/bcm2835_property: Add support for RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS Richard Henderson
2022-09-14 11:52 ` [PULL 03/20] target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8 Richard Henderson
2022-09-14 11:52 ` [PULL 04/20] target/arm: Sort KVM reads of AArch32 ID registers into encoding order Richard Henderson
2022-09-14 11:52 ` [PULL 05/20] target/arm: Implement ID_MMFR5 Richard Henderson
2022-09-14 11:52 ` [PULL 06/20] target/arm: Implement ID_DFR1 Richard Henderson
2022-09-14 11:52 ` [PULL 07/20] target/arm: Advertise FEAT_ETS for '-cpu max' Richard Henderson
2022-09-14 11:52 ` [PULL 08/20] target/arm: Add missing space in comment Richard Henderson
2022-09-14 11:52 ` [PULL 09/20] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows Richard Henderson
2022-09-14 11:52 ` [PULL 10/20] target/arm: Correct value returned by pmu_counter_mask() Richard Henderson
2022-09-14 11:52 ` [PULL 11/20] target/arm: Don't mishandle count when enabling or disabling PMU counters Richard Henderson
2022-09-20 16:45 ` Thomas Huth
2022-09-23 10:50 ` Peter Maydell
2022-09-14 11:52 ` [PULL 12/20] target/arm: Ignore PMCR.D when PMCR.LC is set Richard Henderson
2022-09-14 11:52 ` [PULL 13/20] target/arm: Honour MDCR_EL2.HPMD in Secure EL2 Richard Henderson
2022-09-14 11:52 ` [PULL 14/20] target/arm: Detect overflow when calculating next PMU interrupt Richard Henderson
2022-09-14 11:52 ` [PULL 15/20] target/arm: Rename pmu_8_n feature test functions Richard Henderson
2022-09-14 11:52 ` [PULL 16/20] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits Richard Henderson
2022-09-14 11:52 ` [PULL 17/20] target/arm: Support 64-bit event counters for FEAT_PMUv3p5 Richard Henderson
2022-09-14 11:52 ` Richard Henderson [this message]
2022-09-14 11:52 ` [PULL 19/20] target/arm: Remove useless TARGET_BIG_ENDIAN check in armv7m_load_kernel() Richard Henderson
2022-09-14 11:52 ` [PULL 20/20] target/arm: Make boards pass base address to armv7m_load_kernel() Richard Henderson
2022-09-17 20:13 ` [PULL 00/20] target-arm.next patch queue Stefan Hajnoczi
2022-09-20 13:06 ` Peter Maydell
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