From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, clg@kaod.org,
"Víctor Colombo" <victor.colombo@eldorado.org.br>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>
Subject: [PULL 10/17] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs
Date: Tue, 20 Sep 2022 16:41:55 -0300 [thread overview]
Message-ID: <20220920194202.82615-11-danielhb413@gmail.com> (raw)
In-Reply-To: <20220920194202.82615-1-danielhb413@gmail.com>
From: Víctor Colombo <victor.colombo@eldorado.org.br>
According to the ISA, for instruction DENBCD:
"If an invalid BCD digit or sign code is detected in the source
operand, an invalid-operation exception (VXCVI) occurs."
In the Invalid Operation Exception section, there is the situation:
"When Invalid Operation Exception is disabled (VE=0) and Invalid
Operation occurs (...) If the operation is an (...) or format the
target FPR is set to a Quiet NaN". This was not being done in
QEMU.
This patch sets the result to QNaN when the instruction DENBCD causes
an Invalid Operation Exception.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220906125523.38765-5-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/dfp_helper.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index be7aa5357a..cc024316d5 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -1147,6 +1147,26 @@ static inline uint8_t dfp_get_bcd_digit_128(ppc_vsr_t *t, unsigned n)
return t->VsrD((n & 0x10) ? 0 : 1) >> ((n << 2) & 63) & 15;
}
+static inline void dfp_invalid_op_vxcvi_64(struct PPC_DFP *dfp)
+{
+ /* TODO: fpscr is incorrectly not being saved to env */
+ dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FPSCR_VE);
+ if ((dfp->env->fpscr & FP_VE) == 0) {
+ dfp->vt.VsrD(1) = 0x7c00000000000000; /* QNaN */
+ }
+}
+
+
+static inline void dfp_invalid_op_vxcvi_128(struct PPC_DFP *dfp)
+{
+ /* TODO: fpscr is incorrectly not being saved to env */
+ dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FPSCR_VE);
+ if ((dfp->env->fpscr & FP_VE) == 0) {
+ dfp->vt.VsrD(0) = 0x7c00000000000000; /* QNaN */
+ dfp->vt.VsrD(1) = 0x0;
+ }
+}
+
#define DFP_HELPER_ENBCD(op, size) \
void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
uint32_t s) \
@@ -1173,7 +1193,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
sgn = 0; \
break; \
default: \
- dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FPSCR_VE); \
+ dfp_invalid_op_vxcvi_##size(&dfp); \
+ set_dfp##size(t, &dfp.vt); \
return; \
} \
} \
@@ -1183,7 +1204,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
digits[(size) / 4 - n] = dfp_get_bcd_digit_##size(&dfp.vb, \
offset++); \
if (digits[(size) / 4 - n] > 10) { \
- dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FPSCR_VE); \
+ dfp_invalid_op_vxcvi_##size(&dfp); \
+ set_dfp##size(t, &dfp.vt); \
return; \
} else { \
nonzero |= (digits[(size) / 4 - n] > 0); \
--
2.37.3
next prev parent reply other threads:[~2022-09-20 23:42 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 19:41 [PULL 00/17] ppc queue Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 01/17] target/ppc: Add HASHKEYR and HASHPKEYR SPRs Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 02/17] target/ppc: Implement hashst and hashchk Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 03/17] target/ppc: Implement hashstp and hashchkp Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 04/17] target/ppc: Move fsqrt to decodetree Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 05/17] target/ppc: Move fsqrts " Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 06/17] target/ppc: Merge fsqrt and fsqrts helpers Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 07/17] target/ppc: Remove extra space from s128 field in ppc_vsr_t Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 08/17] target/ppc: Remove unused xer_* macros Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 09/17] target/ppc: Zero second doubleword in DFP instructions Daniel Henrique Barboza
2022-09-20 19:41 ` Daniel Henrique Barboza [this message]
2022-09-20 19:41 ` [PULL 11/17] target/ppc: Zero second doubleword for VSX madd instructions Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 12/17] target/ppc: Set OV32 when OV is set Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 13/17] target/ppc: Zero second doubleword of VSR registers for FPR insns Daniel Henrique Barboza
2022-09-20 19:41 ` [PULL 14/17] target/ppc: Clear fpstatus flags on helpers missing it Daniel Henrique Barboza
2022-09-20 19:42 ` [PULL 15/17] hw/ppc: spapr: Use qemu_vfree() to free spapr->htab Daniel Henrique Barboza
2022-09-20 19:42 ` [PULL 16/17] hw/pci-host: pnv_phb{3, 4}: Fix heap out-of-bound access failure Daniel Henrique Barboza
2022-09-20 19:42 ` [PULL 17/17] hw/ppc/spapr: Fix code style problems reported by checkpatch Daniel Henrique Barboza
2022-09-21 19:44 ` [PULL 00/17] ppc queue Stefan Hajnoczi
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