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Tsirkin" To: Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= Cc: Gerd Hoffmann , qemu-devel@nongnu.org, Sergio Lopez , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , kvm@vger.kernel.org, Marcelo Tosatti , Paolo Bonzini Subject: Re: [PATCH v4] x86: add etc/phys-bits fw_cfg file Message-ID: <20220922074758-mutt-send-email-mst@kernel.org> References: <20220922101454.1069462-1-kraxel@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Sep 22, 2022 at 12:24:09PM +0100, Daniel P. Berrangé wrote: > On Thu, Sep 22, 2022 at 12:14:54PM +0200, Gerd Hoffmann wrote: > > In case phys bits are functional and can be used by the guest (aka > > host-phys-bits=on) add a fw_cfg file carrying the value. This can > > be used by the guest firmware for address space configuration. > > > > The value in the etc/phys-bits fw_cfg file should be identical to > > the phys bits value published via cpuid leaf 0x80000008. > > > > This is only enabled for 7.2+ machine types for live migration > > compatibility reasons. > > Is this going to have any implications for what mgmt apps must > take into account when selecting valid migration target hosts ? I don't think this does anything by itself. It just tells the firmware which value to use, since historically it ignored CPUID. I am still debating with myself whether a boolean would be better. Would appreciate KVM maintainer's take on this. But in any case guests already sometimes use CPUID (e.g. just grep for cpuid_maxphyaddr). This value is just for firmware use. > Historically, apps have tended to ignore any checks for phys > bits between src/dst migration hosts and hoped for the best. > > Will this new behaviour introduce / change any failure scenarios > where the target host has fewer phys bits than the src host, that > mgmt apps need to be made aware of ? > > > > > Signed-off-by: Gerd Hoffmann > > Reviewed-by: Michael S. Tsirkin > > --- > > hw/i386/fw_cfg.h | 1 + > > include/hw/i386/pc.h | 1 + > > hw/i386/fw_cfg.c | 12 ++++++++++++ > > hw/i386/pc.c | 5 +++++ > > hw/i386/pc_piix.c | 2 ++ > > hw/i386/pc_q35.c | 2 ++ > > 6 files changed, 23 insertions(+) > > > > diff --git a/hw/i386/fw_cfg.h b/hw/i386/fw_cfg.h > > index 275f15c1c5e8..6ff198a6cb85 100644 > > --- a/hw/i386/fw_cfg.h > > +++ b/hw/i386/fw_cfg.h > > @@ -26,5 +26,6 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms, > > void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg); > > void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg); > > void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg); > > +void fw_cfg_phys_bits(FWCfgState *fw_cfg); > > > > #endif > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > > index c95333514ed3..bedef1ee13c1 100644 > > --- a/include/hw/i386/pc.h > > +++ b/include/hw/i386/pc.h > > @@ -119,6 +119,7 @@ struct PCMachineClass { > > bool enforce_aligned_dimm; > > bool broken_reserved_end; > > bool enforce_amd_1tb_hole; > > + bool phys_bits_in_fw_cfg; > > > > /* generate legacy CPU hotplug AML */ > > bool legacy_cpu_hotplug; > > diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c > > index a283785a8de4..6a1f18925725 100644 > > --- a/hw/i386/fw_cfg.c > > +++ b/hw/i386/fw_cfg.c > > @@ -219,3 +219,15 @@ void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) > > aml_append(dev, aml_name_decl("_CRS", crs)); > > aml_append(scope, dev); > > } > > + > > +void fw_cfg_phys_bits(FWCfgState *fw_cfg) > > +{ > > + X86CPU *cpu = X86_CPU(first_cpu); > > + uint64_t phys_bits = cpu->phys_bits; > > + > > + if (cpu->host_phys_bits) { > > + fw_cfg_add_file(fw_cfg, "etc/phys-bits", > > + g_memdup2(&phys_bits, sizeof(phys_bits)), > > + sizeof(phys_bits)); > > + } > > +} > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > > index 566accf7e60a..17ecc7fe4331 100644 > > --- a/hw/i386/pc.c > > +++ b/hw/i386/pc.c > > @@ -744,6 +744,7 @@ void pc_machine_done(Notifier *notifier, void *data) > > { > > PCMachineState *pcms = container_of(notifier, > > PCMachineState, machine_done); > > + PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); > > X86MachineState *x86ms = X86_MACHINE(pcms); > > > > cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, > > @@ -764,6 +765,9 @@ void pc_machine_done(Notifier *notifier, void *data) > > fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); > > /* update FW_CFG_NB_CPUS to account for -device added CPUs */ > > fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); > > + if (pcmc->phys_bits_in_fw_cfg) { > > + fw_cfg_phys_bits(x86ms->fw_cfg); > > + } > > } > > } > > > > @@ -1907,6 +1911,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) > > pcmc->kvmclock_enabled = true; > > pcmc->enforce_aligned_dimm = true; > > pcmc->enforce_amd_1tb_hole = true; > > + pcmc->phys_bits_in_fw_cfg = true; > > /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported > > * to be used at the moment, 32K should be enough for a while. */ > > pcmc->acpi_data_size = 0x20000 + 0x8000; > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > > index 8043a250adf3..c6a4dbd5c0b0 100644 > > --- a/hw/i386/pc_piix.c > > +++ b/hw/i386/pc_piix.c > > @@ -447,9 +447,11 @@ DEFINE_I440FX_MACHINE(v7_2, "pc-i440fx-7.2", NULL, > > > > static void pc_i440fx_7_1_machine_options(MachineClass *m) > > { > > + PCMachineClass *pcmc = PC_MACHINE_CLASS(m); > > pc_i440fx_7_2_machine_options(m); > > m->alias = NULL; > > m->is_default = false; > > + pcmc->phys_bits_in_fw_cfg = false; > > compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); > > compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); > > } > > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > > index 53eda50e818c..c2b56daa1550 100644 > > --- a/hw/i386/pc_q35.c > > +++ b/hw/i386/pc_q35.c > > @@ -384,8 +384,10 @@ DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, > > > > static void pc_q35_7_1_machine_options(MachineClass *m) > > { > > + PCMachineClass *pcmc = PC_MACHINE_CLASS(m); > > pc_q35_7_2_machine_options(m); > > m->alias = NULL; > > + pcmc->phys_bits_in_fw_cfg = false; > > compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); > > compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); > > } > > -- > > 2.37.3 > > > > > > With regards, > Daniel > -- > |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| > |: https://libvirt.org -o- https://fstop138.berrange.com :| > |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|