From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, mads@ynddal.dk,
"Alex Bennée" <alex.bennee@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>
Subject: [PATCH v1 2/9] qtest: make read/write operation appear to be from CPU
Date: Thu, 22 Sep 2022 15:58:25 +0100 [thread overview]
Message-ID: <20220922145832.1934429-3-alex.bennee@linaro.org> (raw)
In-Reply-To: <20220922145832.1934429-1-alex.bennee@linaro.org>
The point of qtest is to simulate how running code might interact with
the system. However because it's not a real system we have places in
the code which especially handle check qtest_enabled() before
referencing current_cpu. Now we can encode these details in the
MemTxAttrs lets do that so we can start removing them.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
v2
- use a common macro instead of specific MEMTXATTRS_QTEST
---
include/exec/memattrs.h | 4 ++++
softmmu/qtest.c | 26 +++++++++++++-------------
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index e83a993c21..021b68dd06 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -70,6 +70,10 @@ typedef struct MemTxAttrs {
*/
#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 })
+/* Helper for setting a basic CPU id */
+#define MEMTXATTRS_CPU(id) ((MemTxAttrs) \
+ {.requester_is_cpu = true, .cpu_index = id})
+
/* New-style MMIO accessors can indicate that the transaction failed.
* A zero (MEMTX_OK) response means success; anything else is a failure
* of some kind. The memory subsystem will bitwise-OR together results
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index f8acef2628..3aa2218b95 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (words[0][5] == 'b') {
uint8_t data = value;
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&data, 1);
} else if (words[0][5] == 'w') {
uint16_t data = value;
tswap16s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&data, 2);
} else if (words[0][5] == 'l') {
uint32_t data = value;
tswap32s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&data, 4);
} else if (words[0][5] == 'q') {
uint64_t data = value;
tswap64s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&data, 8);
}
qtest_send_prefix(chr);
@@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (words[0][4] == 'b') {
uint8_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&data, 1);
value = data;
} else if (words[0][4] == 'w') {
uint16_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&data, 2);
value = tswap16(data);
} else if (words[0][4] == 'l') {
uint32_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&data, 4);
value = tswap32(data);
} else if (words[0][4] == 'q') {
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
&value, 8);
tswap64s(&value);
}
@@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
g_assert(len);
data = g_malloc(len);
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data,
len);
enc = g_malloc(2 * len + 1);
@@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
g_assert(ret == 0);
data = g_malloc(len);
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data,
len);
b64_data = g_base64_encode(data, len);
qtest_send_prefix(chr);
@@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
data[i] = 0;
}
}
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data,
len);
g_free(data);
@@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (len) {
data = g_malloc(len);
memset(data, pattern, len);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index),
data, len);
g_free(data);
}
@@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
out_len = MIN(out_len, len);
}
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data,
len);
qtest_send_prefix(chr);
--
2.34.1
next prev parent reply other threads:[~2022-09-22 15:13 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 14:58 [PATCH v1 0/9] MemTxAttrs cpu_index and gdbstub/next Alex Bennée
2022-09-22 14:58 ` [PATCH v1 1/9] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-09-25 10:08 ` Richard Henderson
2022-09-25 13:02 ` Alex Bennée
2022-09-26 7:33 ` Richard Henderson
2022-09-22 14:58 ` Alex Bennée [this message]
2022-09-22 14:58 ` [PATCH v1 3/9] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-09-25 10:11 ` Richard Henderson
2022-09-26 10:56 ` mads
2022-09-26 11:01 ` Alex Bennée
2022-09-26 11:20 ` mads
2022-09-22 14:58 ` [PATCH v1 4/9] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-09-25 10:11 ` Richard Henderson
2022-09-22 14:58 ` [PATCH v1 5/9] configure: move detected gdb to TCG's config-host.mak Alex Bennée
2022-09-25 10:11 ` Richard Henderson
2022-09-22 14:58 ` [PATCH v1 6/9] gdbstub: move into its own sub directory Alex Bennée
2022-09-25 10:13 ` Richard Henderson
2022-09-22 14:58 ` [PATCH v1 7/9] gdbstub: move sstep flags probing into AccelClass Alex Bennée
2022-09-22 21:49 ` Philippe Mathieu-Daudé via
2022-09-25 10:14 ` Richard Henderson
2022-09-22 14:58 ` [PATCH v1 8/9] gdbstub: move breakpoint logic to accel ops Alex Bennée
2022-09-25 10:18 ` Richard Henderson
2022-09-22 14:58 ` [PATCH v1 9/9] gdbstub: move guest debug support check to ops Alex Bennée
2022-09-22 21:51 ` Philippe Mathieu-Daudé via
2022-09-25 10:18 ` Richard Henderson
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