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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id ez24-20020a1709070bd800b00741383c1c5bsm2588662ejc.196.2022.09.22.06.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 06:46:19 -0700 (PDT) Date: Thu, 22 Sep 2022 15:46:17 +0200 From: Igor Mammedov To: Peter Xu Cc: qemu-devel@nongnu.org, Jason Wang , "Michael S . Tsirkin" , Paolo Bonzini , David Woodhouse , Claudio Fontana Subject: Re: [PATCH] Revert "intel_iommu: Fix irqchip / X2APIC configuration checks" Message-ID: <20220922154617.57d1a1fb@redhat.com> In-Reply-To: <20220921161227.57259-1-peterx@redhat.com> References: <20220921161227.57259-1-peterx@redhat.com> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.34; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 21 Sep 2022 12:12:27 -0400 Peter Xu wrote: > It's true that when vcpus<=255 we don't require the length of 32bit APIC > IDs. However here since we already have EIM=ON it means the hypervisor > will declare the VM as x2apic supported (e.g. VT-d ECAP register will have > EIM bit 4 set), so the guest should assume the APIC IDs are 32bits width > even if vcpus<=255. In short, commit 77250171bdc breaks any simple cmdline > that wants to boot a VM with >=9 but <=255 vcpus with: > > -device intel-iommu,intremap=on > > For anyone who does not want to enable x2apic, we can use eim=off in the > intel-iommu parameters to skip enabling KVM x2apic. > > This partly reverts commit 77250171bdc02aee106083fd2a068147befa1a38, while > keeping the valid bit on checking split irqchip, but revert the other change. > > Cc: David Woodhouse > Cc: Claudio Fontana > Cc: Igor Mammedov > Signed-off-by: Peter Xu > --- > hw/i386/intel_iommu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 05d53a1aa9..6524c2ee32 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -3818,6 +3818,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) > error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split"); > return false; > } > + if (!kvm_enable_x2apic()) { above 'check' has side-effects if it's supposed to be a check it would be better to use kvm_has_x2apic_api() instead. Also 77250171bdc says: " The check on kvm_enable_x2apic() needs to happen *anyway* in order to allow CPUs above 254 even without an IOMMU, so allow that to happen elsewhere. " Looking for that elsewhere, it looks like commit dc89f32d92b was supposed to take care of removed chunk, but that is not reachable because of > 255 vCPUs" Likely 77250171bdc just exposed a bug in dc89f32d92b, where the later removed kvm_enable_x2apic() always called (with split irqchip) and made it called only when > 255 vCPUs. So migration wise it looks like all version with it and less than 255 cpus are broken. Wait earlier c1bb5418e3, introduced that kvm_irqchip_is_split() && kvm_enable_x2apic() 'condition', also without any compat machinery to keep old behavior. And before that kvm_enable_x2apic() was affecting only configuration with intel_iommu (fb506e701e9b). I'm not sure if anything could be salvaged here migration wise PS: I'd keep kvm_enable_x2apic() only in corrected x86_cpus_init() and use kvm_has_x2apic_api() elsewhere for checks and bailing out. > + error_setg(errp, "eim=on requires support on the KVM side" > + "(X2APIC_API, first shipped in v4.7)"); > + return false; > + } > } > > /* Currently only address widths supported are 39 and 48 bits */