From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
Bin Meng <bmeng.cn@gmail.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written
Date: Tue, 27 Sep 2022 16:30:58 +1000 [thread overview]
Message-ID: <20220927063104.2846825-17-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220927063104.2846825-1-alistair.francis@opensource.wdc.com>
From: Frank Chang <frank.chang@sifive.com>
The value of tselect CSR can be written should be limited within the
range of supported triggers number.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20220909134215.1843865-5-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 06feef7d67..d6666164cd 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -127,10 +127,6 @@ bool tdata_available(CPURISCVState *env, int tdata_index)
return false;
}
- if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) {
- return false;
- }
-
return tdata_mapping[trigger_type][tdata_index];
}
@@ -141,8 +137,9 @@ target_ulong tselect_csr_read(CPURISCVState *env)
void tselect_csr_write(CPURISCVState *env, target_ulong val)
{
- /* all target_ulong bits of tselect are implemented */
- env->trigger_cur = val;
+ if (val < RV_MAX_TRIGGERS) {
+ env->trigger_cur = val;
+ }
}
static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
--
2.37.3
next prev parent reply other threads:[~2022-09-27 9:40 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 6:30 [PULL v2 00/22] riscv-to-apply queue Alistair Francis
2022-09-27 6:30 ` [PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-27 6:30 ` [PULL v2 02/22] hw/ssi: ibex_spi: update reg addr Alistair Francis
2022-09-27 6:30 ` [PULL v2 03/22] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-27 6:30 ` [PULL v2 04/22] target/riscv: Remove sideleg and sedeleg Alistair Francis
2022-09-27 6:30 ` [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-27 6:30 ` [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-27 6:30 ` [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files Alistair Francis
2022-09-27 6:30 ` [PULL v2 08/22] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-27 6:30 ` [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec Alistair Francis
2022-09-27 6:30 ` [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-27 6:30 ` [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-27 6:30 ` [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-27 6:30 ` [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type Alistair Francis
2022-09-27 6:30 ` [PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content Alistair Francis
2022-09-27 6:30 ` [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Alistair Francis
2022-09-27 6:30 ` Alistair Francis [this message]
2022-09-27 6:30 ` [PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR Alistair Francis
2022-09-27 6:31 ` [PULL v2 18/22] target/riscv: debug: Create common trigger actions function Alistair Francis
2022-09-27 6:31 ` [PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger Alistair Francis
2022-09-27 6:31 ` [PULL v2 20/22] target/riscv: debug: Add initial support of type 6 trigger Alistair Francis
2022-09-27 6:31 ` [PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code Alistair Francis
2022-09-27 6:31 ` [PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered Alistair Francis
2022-09-27 15:04 ` [PULL v2 00/22] riscv-to-apply queue Stefan Hajnoczi
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