From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Yang Liu <liuyang22@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>,
Frank Chang <frank.chang@sifive.com>
Subject: [PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code
Date: Tue, 27 Sep 2022 16:31:03 +1000 [thread overview]
Message-ID: <20220927063104.2846825-22-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220927063104.2846825-1-alistair.francis@opensource.wdc.com>
From: Yang Liu <liuyang22@iscas.ac.cn>
Remove duplicate code by wrapping vfwredsum_vs's OP function.
Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220817074802.20765-1-liuyang22@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 56 +++++++-----------------------------
1 file changed, 10 insertions(+), 46 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d224861c2c..2828073497 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4728,58 +4728,22 @@ GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_number)
GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_number)
GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_number)
-/* Vector Widening Floating-Point Reduction Instructions */
-/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
-void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
- void *vs2, CPURISCVState *env, uint32_t desc)
+/* Vector Widening Floating-Point Add Instructions */
+static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s)
{
- uint32_t vm = vext_vm(desc);
- uint32_t vl = env->vl;
- uint32_t esz = sizeof(uint32_t);
- uint32_t vlenb = simd_maxsz(desc);
- uint32_t vta = vext_vta(desc);
- uint32_t i;
- uint32_t s1 = *((uint32_t *)vs1 + H4(0));
-
- for (i = env->vstart; i < vl; i++) {
- uint16_t s2 = *((uint16_t *)vs2 + H2(i));
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
- s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
- &env->fp_status);
- }
- *((uint32_t *)vd + H4(0)) = s1;
- env->vstart = 0;
- /* set tail elements to 1s */
- vext_set_elems_1s(vd, vta, esz, vlenb);
+ return float32_add(a, float16_to_float32(b, true, s), s);
}
-void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
- void *vs2, CPURISCVState *env, uint32_t desc)
+static uint64_t fwadd32(uint64_t a, uint32_t b, float_status *s)
{
- uint32_t vm = vext_vm(desc);
- uint32_t vl = env->vl;
- uint32_t esz = sizeof(uint64_t);
- uint32_t vlenb = simd_maxsz(desc);
- uint32_t vta = vext_vta(desc);
- uint32_t i;
- uint64_t s1 = *((uint64_t *)vs1);
-
- for (i = env->vstart; i < vl; i++) {
- uint32_t s2 = *((uint32_t *)vs2 + H4(i));
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
- s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
- &env->fp_status);
- }
- *((uint64_t *)vd) = s1;
- env->vstart = 0;
- /* set tail elements to 1s */
- vext_set_elems_1s(vd, vta, esz, vlenb);
+ return float64_add(a, float32_to_float64(b, s), s);
}
+/* Vector Widening Floating-Point Reduction Instructions */
+/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
+GEN_VEXT_FRED(vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
+GEN_VEXT_FRED(vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
+
/*
*** Vector Mask Operations
*/
--
2.37.3
next prev parent reply other threads:[~2022-09-27 9:07 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 6:30 [PULL v2 00/22] riscv-to-apply queue Alistair Francis
2022-09-27 6:30 ` [PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-27 6:30 ` [PULL v2 02/22] hw/ssi: ibex_spi: update reg addr Alistair Francis
2022-09-27 6:30 ` [PULL v2 03/22] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-27 6:30 ` [PULL v2 04/22] target/riscv: Remove sideleg and sedeleg Alistair Francis
2022-09-27 6:30 ` [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-27 6:30 ` [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-27 6:30 ` [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files Alistair Francis
2022-09-27 6:30 ` [PULL v2 08/22] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-27 6:30 ` [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec Alistair Francis
2022-09-27 6:30 ` [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-27 6:30 ` [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-27 6:30 ` [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-27 6:30 ` [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type Alistair Francis
2022-09-27 6:30 ` [PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content Alistair Francis
2022-09-27 6:30 ` [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Alistair Francis
2022-09-27 6:30 ` [PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written Alistair Francis
2022-09-27 6:30 ` [PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR Alistair Francis
2022-09-27 6:31 ` [PULL v2 18/22] target/riscv: debug: Create common trigger actions function Alistair Francis
2022-09-27 6:31 ` [PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger Alistair Francis
2022-09-27 6:31 ` [PULL v2 20/22] target/riscv: debug: Add initial support of type 6 trigger Alistair Francis
2022-09-27 6:31 ` Alistair Francis [this message]
2022-09-27 6:31 ` [PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered Alistair Francis
2022-09-27 15:04 ` [PULL v2 00/22] riscv-to-apply queue Stefan Hajnoczi
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