From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Andrew Burgess <aburgess@redhat.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files
Date: Tue, 27 Sep 2022 16:30:49 +1000 [thread overview]
Message-ID: <20220927063104.2846825-8-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220927063104.2846825-1-alistair.francis@opensource.wdc.com>
From: Andrew Burgess <aburgess@redhat.com>
The fixed register numbering in the various GDB feature files for
RISC-V only exists because these files were originally copied from the
GDB source tree.
However, the fixed numbering only exists in the GDB source tree so
that GDB, when it connects to a target that doesn't provide a target
description, will use a specific numbering scheme.
That numbering scheme is designed to be compatible with the first
versions of QEMU (for RISC-V), that didn't send a target description,
and relied on a fixed numbering scheme.
Because of the way that QEMU manages its target descriptions,
recording the number of registers in each feature, and just relying on
GDB's numbering starting from 0, then I propose that we remove all the
fixed numbering from the RISC-V feature xml files, and just rely on
the standard numbering scheme. Plenty of other targets manage their
xml files this way, e.g. ARM, AArch64, Loongarch, m68k, rx, and s390.
Signed-off-by: Andrew Burgess <aburgess@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Message-Id: <6069395f90e6fc24dac92197be815fedf42f5974.1661934573.git.aburgess@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
gdb-xml/riscv-32bit-cpu.xml | 6 +-----
gdb-xml/riscv-32bit-fpu.xml | 6 +-----
gdb-xml/riscv-64bit-cpu.xml | 6 +-----
gdb-xml/riscv-64bit-fpu.xml | 6 +-----
4 files changed, 4 insertions(+), 20 deletions(-)
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
index 0d07aaec85..466f2c0648 100644
--- a/gdb-xml/riscv-32bit-cpu.xml
+++ b/gdb-xml/riscv-32bit-cpu.xml
@@ -5,13 +5,9 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
-<!-- Register numbers are hard-coded in order to maintain backward
- compatibility with older versions of tools that didn't use xml
- register descriptions. -->
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
- <reg name="zero" bitsize="32" type="int" regnum="0"/>
+ <reg name="zero" bitsize="32" type="int"/>
<reg name="ra" bitsize="32" type="code_ptr"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="gp" bitsize="32" type="data_ptr"/>
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
index 84a44ba8df..24aa087031 100644
--- a/gdb-xml/riscv-32bit-fpu.xml
+++ b/gdb-xml/riscv-32bit-fpu.xml
@@ -5,13 +5,9 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
-<!-- Register numbers are hard-coded in order to maintain backward
- compatibility with older versions of tools that didn't use xml
- register descriptions. -->
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.fpu">
- <reg name="ft0" bitsize="32" type="ieee_single" regnum="33"/>
+ <reg name="ft0" bitsize="32" type="ieee_single"/>
<reg name="ft1" bitsize="32" type="ieee_single"/>
<reg name="ft2" bitsize="32" type="ieee_single"/>
<reg name="ft3" bitsize="32" type="ieee_single"/>
diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
index b8aa424ae4..c4d83de09b 100644
--- a/gdb-xml/riscv-64bit-cpu.xml
+++ b/gdb-xml/riscv-64bit-cpu.xml
@@ -5,13 +5,9 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
-<!-- Register numbers are hard-coded in order to maintain backward
- compatibility with older versions of tools that didn't use xml
- register descriptions. -->
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
- <reg name="zero" bitsize="64" type="int" regnum="0"/>
+ <reg name="zero" bitsize="64" type="int"/>
<reg name="ra" bitsize="64" type="code_ptr"/>
<reg name="sp" bitsize="64" type="data_ptr"/>
<reg name="gp" bitsize="64" type="data_ptr"/>
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
index 9856a9d1d3..d0f17f9984 100644
--- a/gdb-xml/riscv-64bit-fpu.xml
+++ b/gdb-xml/riscv-64bit-fpu.xml
@@ -5,10 +5,6 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
-<!-- Register numbers are hard-coded in order to maintain backward
- compatibility with older versions of tools that didn't use xml
- register descriptions. -->
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.fpu">
@@ -17,7 +13,7 @@
<field name="double" type="ieee_double"/>
</union>
- <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
<reg name="ft1" bitsize="64" type="riscv_double"/>
<reg name="ft2" bitsize="64" type="riscv_double"/>
<reg name="ft3" bitsize="64" type="riscv_double"/>
--
2.37.3
next prev parent reply other threads:[~2022-09-27 6:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 6:30 [PULL v2 00/22] riscv-to-apply queue Alistair Francis
2022-09-27 6:30 ` [PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-27 6:30 ` [PULL v2 02/22] hw/ssi: ibex_spi: update reg addr Alistair Francis
2022-09-27 6:30 ` [PULL v2 03/22] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-27 6:30 ` [PULL v2 04/22] target/riscv: Remove sideleg and sedeleg Alistair Francis
2022-09-27 6:30 ` [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-27 6:30 ` [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-27 6:30 ` Alistair Francis [this message]
2022-09-27 6:30 ` [PULL v2 08/22] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-27 6:30 ` [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec Alistair Francis
2022-09-27 6:30 ` [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-27 6:30 ` [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-27 6:30 ` [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-27 6:30 ` [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type Alistair Francis
2022-09-27 6:30 ` [PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content Alistair Francis
2022-09-27 6:30 ` [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Alistair Francis
2022-09-27 6:30 ` [PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written Alistair Francis
2022-09-27 6:30 ` [PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR Alistair Francis
2022-09-27 6:31 ` [PULL v2 18/22] target/riscv: debug: Create common trigger actions function Alistair Francis
2022-09-27 6:31 ` [PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger Alistair Francis
2022-09-27 6:31 ` [PULL v2 20/22] target/riscv: debug: Add initial support of type 6 trigger Alistair Francis
2022-09-27 6:31 ` [PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code Alistair Francis
2022-09-27 6:31 ` [PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered Alistair Francis
2022-09-27 15:04 ` [PULL v2 00/22] riscv-to-apply queue Stefan Hajnoczi
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