From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>
Subject: [PATCH v3 07/15] qtest: make read/write operation appear to be from CPU
Date: Tue, 27 Sep 2022 15:14:56 +0100 [thread overview]
Message-ID: <20220927141504.3886314-8-alex.bennee@linaro.org> (raw)
In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org>
The point of qtest is to simulate how running code might interact with
the system. However because it's not a real system we have places in
the code which especially handle check qtest_enabled() before
referencing current_cpu. Now we can encode these details in the
MemTxAttrs lets do that so we can start removing them.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
v2
- use a common macro instead of specific MEMTXATTRS_QTEST
v3
- macro moved to earlier patch
---
softmmu/qtest.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index f8acef2628..7d29d54a4c 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (words[0][5] == 'b') {
uint8_t data = value;
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 1);
} else if (words[0][5] == 'w') {
uint16_t data = value;
tswap16s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 2);
} else if (words[0][5] == 'l') {
uint32_t data = value;
tswap32s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 4);
} else if (words[0][5] == 'q') {
uint64_t data = value;
tswap64s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 8);
}
qtest_send_prefix(chr);
@@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (words[0][4] == 'b') {
uint8_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 1);
value = data;
} else if (words[0][4] == 'w') {
uint16_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 2);
value = tswap16(data);
} else if (words[0][4] == 'l') {
uint32_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 4);
value = tswap32(data);
} else if (words[0][4] == 'q') {
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&value, 8);
tswap64s(&value);
}
@@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
g_assert(len);
data = g_malloc(len);
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data,
len);
enc = g_malloc(2 * len + 1);
@@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
g_assert(ret == 0);
data = g_malloc(len);
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data,
len);
b64_data = g_base64_encode(data, len);
qtest_send_prefix(chr);
@@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
data[i] = 0;
}
}
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data,
len);
g_free(data);
@@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (len) {
data = g_malloc(len);
memset(data, pattern, len);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
data, len);
g_free(data);
}
@@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
out_len = MIN(out_len, len);
}
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data,
len);
qtest_send_prefix(chr);
--
2.34.1
next prev parent reply other threads:[~2022-09-27 15:43 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 14:14 [PATCH v3 00/15] gdbstub/next (MemTxAttrs, re-factoring) Alex Bennée
2022-09-27 14:14 ` [PATCH v3 01/15] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-09-28 16:42 ` Richard Henderson
2022-09-28 18:56 ` Peter Maydell
2022-10-04 13:32 ` Alex Bennée
2022-10-04 14:54 ` Peter Maydell
2022-10-31 12:08 ` Philippe Mathieu-Daudé
2022-10-31 13:03 ` Peter Maydell
2022-11-11 13:23 ` Philippe Mathieu-Daudé
2022-11-11 13:58 ` Alex Bennée
2022-11-14 10:06 ` Peter Maydell
2022-09-27 14:14 ` [PATCH v3 02/15] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Alex Bennée
2022-09-28 16:45 ` Richard Henderson
2022-09-27 14:14 ` [PATCH v3 03/15] target/arm: ensure HVF traps " Alex Bennée
2022-09-28 16:47 ` Richard Henderson
2022-10-04 10:25 ` Mads Ynddal
2022-09-27 14:14 ` [PATCH v3 04/15] target/arm: ensure KVM " Alex Bennée
2022-09-28 16:49 ` Richard Henderson
2022-10-19 10:44 ` Philippe Mathieu-Daudé
2022-09-27 14:14 ` [PATCH v3 05/15] target/arm: ensure ptw accesses " Alex Bennée
2022-09-28 16:52 ` Richard Henderson
2022-09-27 14:14 ` [PATCH v3 06/15] target/arm: ensure m-profile helpers " Alex Bennée
2022-09-28 16:57 ` Richard Henderson
2022-09-27 14:14 ` Alex Bennée [this message]
2022-09-28 16:58 ` [PATCH v3 07/15] qtest: make read/write operation appear to be from CPU Richard Henderson
2022-09-27 14:14 ` [PATCH v3 08/15] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-09-28 17:03 ` Richard Henderson
2022-09-27 14:14 ` [PATCH v3 09/15] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-09-28 17:04 ` Richard Henderson
2022-10-19 10:46 ` Philippe Mathieu-Daudé
2022-09-27 14:14 ` [PATCH v3 10/15] configure: move detected gdb to TCG's config-host.mak Alex Bennée
2022-09-27 14:15 ` [PATCH v3 11/15] gdbstub: move into its own sub directory Alex Bennée
2022-10-19 10:47 ` Philippe Mathieu-Daudé
2022-09-27 14:15 ` [PATCH v3 12/15] gdbstub: move sstep flags probing into AccelClass Alex Bennée
2022-10-04 10:25 ` Mads Ynddal
2022-09-27 14:15 ` [PATCH v3 13/15] gdbstub: move breakpoint logic to accel ops Alex Bennée
2022-10-04 10:25 ` Mads Ynddal
2022-09-27 14:15 ` [PATCH v3 14/15] gdbstub: move guest debug support check to ops Alex Bennée
2022-10-04 10:25 ` Mads Ynddal
2022-09-27 14:15 ` [PATCH v3 15/15] accel/kvm: move kvm_update_guest_debug to inline stub Alex Bennée
2022-10-19 10:53 ` Philippe Mathieu-Daudé
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