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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [RFC 1/8] target/riscv: add cfg properties for Zc* extension
Date: Fri, 30 Sep 2022 09:23:38 +0800	[thread overview]
Message-ID: <20220930012345.5248-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220930012345.5248-1-liweiwei@iscas.ac.cn>

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
Add check for these properties

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 24 ++++++++++++++++++++++++
 target/riscv/cpu.h |  6 ++++++
 2 files changed, 30 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b29c88b9f0..7da3de1725 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -782,6 +782,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
         }
 
+        if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+            error_setg(errp, "Zcf is only relevant to RV32");
+            return;
+        }
+
+        if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
+             cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
+            error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt require Zca extension");
+            return;
+        }
+
+        if ((((env->misa_ext & RVD) && (env->misa_ext & RVC)) ||
+             cpu->cfg.ext_zcd) && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
+            error_setg(errp,
+                       "Zcmp/Zcmt are incompatible with Zcd, which is "
+                       "included when C and D extensions are both present");
+            return;
+        }
+
+        if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
+            error_setg(errp, "Zcmt extension requires Zicsr");
+            return;
+        }
+
         if (cpu->cfg.ext_zk) {
             cpu->cfg.ext_zkn = true;
             cpu->cfg.ext_zkr = true;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b131fa8c8e..db3eca1d8a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -428,6 +428,12 @@ struct RISCVCPUConfig {
     bool ext_zbkc;
     bool ext_zbkx;
     bool ext_zbs;
+    bool ext_zca;
+    bool ext_zcb;
+    bool ext_zcd;
+    bool ext_zcf;
+    bool ext_zcmp;
+    bool ext_zcmt;
     bool ext_zk;
     bool ext_zkn;
     bool ext_zknd;
-- 
2.25.1



  reply	other threads:[~2022-09-30  1:28 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-30  1:23 [RFC 0/8] support subsets of code size reduction extension Weiwei Li
2022-09-30  1:23 ` Weiwei Li [this message]
2022-10-25  3:14   ` [RFC 1/8] target/riscv: add cfg properties for Zc* extension Alistair Francis
2022-09-30  1:23 ` [RFC 2/8] target/riscv: add support for Zca, Zcf and Zcd extension Weiwei Li
2022-09-30  1:23 ` [RFC 3/8] target/riscv: add support for Zcb extension Weiwei Li
2022-09-30  1:23 ` [RFC 4/8] target/riscv: add support for Zcmp extension Weiwei Li
2022-09-30  1:23 ` [RFC 5/8] target/riscv: add support for Zcmt extension Weiwei Li
2022-09-30  1:23 ` [RFC 6/8] target/riscv: delete redundant check for zcd instructions in decode_opc Weiwei Li
2022-10-25  3:39   ` Alistair Francis
2022-10-25  7:03     ` weiwei
2022-09-30  1:23 ` [RFC 7/8] target/riscv: expose properties for Zc* extension Weiwei Li
2022-10-25  3:39   ` Alistair Francis
2022-09-30  1:23 ` [RFC 8/8] disas/riscv.c: add disasm support for Zc* Weiwei Li

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