From: Weiwei Li <liweiwei@iscas.ac.cn>
To: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [RFC 7/8] target/riscv: expose properties for Zc* extension
Date: Fri, 30 Sep 2022 09:23:44 +0800 [thread overview]
Message-ID: <20220930012345.5248-8-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220930012345.5248-1-liweiwei@iscas.ac.cn>
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7da3de1725..e6f722278c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -80,6 +80,12 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
+ ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
+ ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
+ ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
+ ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
+ ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
+ ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
@@ -1070,6 +1076,13 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+
+ DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
+ DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
+ DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
+ DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
+ DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
+ DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
--
2.25.1
next prev parent reply other threads:[~2022-09-30 1:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 1:23 [RFC 0/8] support subsets of code size reduction extension Weiwei Li
2022-09-30 1:23 ` [RFC 1/8] target/riscv: add cfg properties for Zc* extension Weiwei Li
2022-10-25 3:14 ` Alistair Francis
2022-09-30 1:23 ` [RFC 2/8] target/riscv: add support for Zca, Zcf and Zcd extension Weiwei Li
2022-09-30 1:23 ` [RFC 3/8] target/riscv: add support for Zcb extension Weiwei Li
2022-09-30 1:23 ` [RFC 4/8] target/riscv: add support for Zcmp extension Weiwei Li
2022-09-30 1:23 ` [RFC 5/8] target/riscv: add support for Zcmt extension Weiwei Li
2022-09-30 1:23 ` [RFC 6/8] target/riscv: delete redundant check for zcd instructions in decode_opc Weiwei Li
2022-10-25 3:39 ` Alistair Francis
2022-10-25 7:03 ` weiwei
2022-09-30 1:23 ` Weiwei Li [this message]
2022-10-25 3:39 ` [RFC 7/8] target/riscv: expose properties for Zc* extension Alistair Francis
2022-09-30 1:23 ` [RFC 8/8] disas/riscv.c: add disasm support for Zc* Weiwei Li
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