From: Jim Shu <jim.shu@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
chigot@adacore.com, Jim Shu <jim.shu@sifive.com>
Subject: [PATCH v2 0/2] Enhance maximum priority support of PLIC
Date: Fri, 30 Sep 2022 12:32:37 +0000 [thread overview]
Message-ID: <20220930123239.15515-1-jim.shu@sifive.com> (raw)
This patchset fixes hard-coded maximum priority of interrupt priority
register and also changes this register to WARL field to align the PLIC
spec.
Changelog:
v2:
* change interrupt priority register to WARL field.
Jim Shu (2):
hw/intc: sifive_plic: fix hard-coded max priority level
hw/intc: sifive_plic: change interrupt priority register to WARL field
hw/intc/sifive_plic.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
--
2.17.1
next reply other threads:[~2022-09-30 12:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 12:32 Jim Shu [this message]
2022-09-30 12:32 ` [PATCH v2 1/2] hw/intc: sifive_plic: fix hard-coded max priority level Jim Shu
2022-09-30 12:32 ` [PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field Jim Shu
2022-09-30 12:58 ` Clément Chigot
2022-09-30 13:09 ` Jim Shu
2022-10-03 4:13 ` Jim Shu
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