From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
Date: Fri, 30 Sep 2022 14:35:11 +0100 [thread overview]
Message-ID: <20220930133511.2112734-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org>
From: Jerome Forissier <jerome.forissier@linaro.org>
SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
it with ARM_CP_EL3_NO_EL2_KEEP.
Cc: qemu-stable@nongnu.org
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 24c592ffef8..db3b1ea72da 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5088,7 +5088,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
{ .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_ALIAS,
+ .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
.fieldoffset = offsetof(CPUARMState, sp_el[1]) },
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
--
2.25.1
next prev parent reply other threads:[~2022-09-30 13:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 13:35 [PULL 00/10] target-arm queue Peter Maydell
2022-09-30 13:35 ` [PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO Peter Maydell
2022-09-30 13:35 ` [PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls Peter Maydell
2022-09-30 13:35 ` [PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD Peter Maydell
2022-09-30 13:35 ` [PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together Peter Maydell
2022-09-30 13:35 ` [PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers Peter Maydell
2022-09-30 13:35 ` [PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node Peter Maydell
2022-09-30 13:35 ` [PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node Peter Maydell
2022-09-30 13:35 ` [PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI Peter Maydell
2022-09-30 13:35 ` [PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node Peter Maydell
2022-09-30 13:35 ` Peter Maydell [this message]
2022-10-03 23:01 ` [PULL 00/10] target-arm queue Stefan Hajnoczi
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