From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v5 5/9] target/arm: Remove gen_exception_internal_insn pc argument
Date: Fri, 30 Sep 2022 15:03:08 -0700 [thread overview]
Message-ID: <20220930220312.135327-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org>
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Since we always pass dc->pc_curr, fold the arithmetic to zero displacement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 6 +++---
target/arm/translate.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2621b3b36a..005fd767fb 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -340,9 +340,9 @@ static void gen_exception_internal(int excp)
gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
}
-static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
+static void gen_exception_internal_insn(DisasContext *s, int excp)
{
- gen_a64_update_pc(s, pc - s->pc_curr);
+ gen_a64_update_pc(s, 0);
gen_exception_internal(excp);
s->base.is_jmp = DISAS_NORETURN;
}
@@ -2219,7 +2219,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
*/
if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) {
- gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+ gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else {
unallocated_encoding(s);
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f9d3128656..e0b1d415a2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1078,10 +1078,10 @@ static inline void gen_smc(DisasContext *s)
s->base.is_jmp = DISAS_SMC;
}
-static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
+static void gen_exception_internal_insn(DisasContext *s, int excp)
{
gen_set_condexec(s);
- gen_update_pc(s, pc - s->pc_curr);
+ gen_update_pc(s, 0);
gen_exception_internal(excp);
s->base.is_jmp = DISAS_NORETURN;
}
@@ -1173,7 +1173,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
*/
if (semihosting_enabled(s->current_el != 0) &&
(imm == (s->thumb ? 0x3c : 0xf000))) {
- gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+ gen_exception_internal_insn(s, EXCP_SEMIHOST);
return;
}
@@ -6560,7 +6560,7 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
if (arm_dc_feature(s, ARM_FEATURE_M) &&
semihosting_enabled(s->current_el == 0) &&
(a->imm == 0xab)) {
- gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+ gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else {
gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
}
@@ -8766,7 +8766,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
if (!arm_dc_feature(s, ARM_FEATURE_M) &&
semihosting_enabled(s->current_el == 0) &&
(a->imm == semihost_imm)) {
- gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+ gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else {
gen_update_pc(s, curr_insn_len(s));
s->svc_imm = a->imm;
--
2.34.1
next prev parent reply other threads:[~2022-09-30 22:05 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 22:03 [PATCH v5 0/9] target/arm: pc-relative translation blocks Richard Henderson
2022-09-30 22:03 ` [PATCH v5 1/9] target/arm: Introduce curr_insn_len Richard Henderson
2022-09-30 22:03 ` [PATCH v5 2/9] target/arm: Change gen_goto_tb to work on displacements Richard Henderson
2022-09-30 22:03 ` [PATCH v5 3/9] target/arm: Change gen_*set_pc_im to gen_*update_pc Richard Henderson
2022-10-03 14:18 ` Philippe Mathieu-Daudé via
2022-09-30 22:03 ` [PATCH v5 4/9] target/arm: Change gen_exception_insn* to work on displacements Richard Henderson
2022-10-03 14:21 ` Philippe Mathieu-Daudé via
2022-09-30 22:03 ` Richard Henderson [this message]
2022-10-03 14:22 ` [PATCH v5 5/9] target/arm: Remove gen_exception_internal_insn pc argument Philippe Mathieu-Daudé via
2022-09-30 22:03 ` [PATCH v5 6/9] target/arm: Change gen_jmp* to work on displacements Richard Henderson
2022-10-04 15:58 ` Peter Maydell
2022-10-04 20:57 ` Richard Henderson
2022-10-05 14:15 ` Peter Maydell
2022-09-30 22:03 ` [PATCH v5 7/9] target/arm: Introduce gen_pc_plus_diff for aarch64 Richard Henderson
2022-10-04 16:10 ` Peter Maydell
2022-09-30 22:03 ` [PATCH v5 8/9] target/arm: Introduce gen_pc_plus_diff for aarch32 Richard Henderson
2022-10-11 14:51 ` Peter Maydell
2022-10-11 15:52 ` Richard Henderson
2022-09-30 22:03 ` [PATCH v5 9/9] target/arm: Enable TARGET_TB_PCREL Richard Henderson
2022-10-04 16:23 ` Peter Maydell
2022-10-04 19:27 ` Richard Henderson
2022-10-04 21:09 ` Richard Henderson
2022-10-14 17:49 ` Peter Maydell
2022-10-14 19:01 ` Richard Henderson
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