From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v3 18/42] target/arm: Split out get_phys_addr_disabled
Date: Sat, 1 Oct 2022 09:22:54 -0700 [thread overview]
Message-ID: <20221001162318.153420-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 138 +++++++++++++++++++++++++----------------------
1 file changed, 74 insertions(+), 64 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 7bf79779da..e494a9de67 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2272,6 +2272,78 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
return ret;
}
+/*
+ * MMU disabled. S1 addresses within aa64 translation regimes are
+ * still checked for bounds -- see AArch64.S1DisabledOutput().
+ */
+static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+ MMUAccessType access_type,
+ ARMMMUIdx mmu_idx, bool is_secure,
+ GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
+{
+ uint64_t hcr;
+ uint8_t memattr;
+
+ if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
+ int r_el = regime_el(env, mmu_idx);
+ if (arm_el_is_aa64(env, r_el)) {
+ int pamax = arm_pamax(env_archcpu(env));
+ uint64_t tcr = env->cp15.tcr_el[r_el];
+ int addrtop, tbi;
+
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
+ if (access_type == MMU_INST_FETCH) {
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
+ }
+ tbi = (tbi >> extract64(address, 55, 1)) & 1;
+ addrtop = (tbi ? 55 : 63);
+
+ if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
+ fi->type = ARMFault_AddressSize;
+ fi->level = 0;
+ fi->stage2 = false;
+ return 1;
+ }
+
+ /*
+ * When TBI is disabled, we've just validated that all of the
+ * bits above PAMax are zero, so logically we only need to
+ * clear the top byte for TBI. But it's clearer to follow
+ * the pseudocode set of addrdesc.paddress.
+ */
+ address = extract64(address, 0, 52);
+ }
+ }
+
+ result->phys = address;
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ result->page_size = TARGET_PAGE_SIZE;
+
+ /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+ result->cacheattrs.shareability = 0;
+ result->cacheattrs.is_s2_format = false;
+ if (hcr & HCR_DC) {
+ if (hcr & HCR_DCT) {
+ memattr = 0xf0; /* Tagged, Normal, WB, RWA */
+ } else {
+ memattr = 0xff; /* Normal, WB, RWA */
+ }
+ } else if (access_type == MMU_INST_FETCH) {
+ if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
+ memattr = 0xee; /* Normal, WT, RA, NT */
+ } else {
+ memattr = 0x44; /* Normal, NC, No */
+ }
+ result->cacheattrs.shareability = 2; /* outer sharable */
+ } else {
+ memattr = 0x00; /* Device, nGnRnE */
+ }
+ result->cacheattrs.attrs = memattr;
+ return 0;
+}
+
bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool is_secure, GetPhysAddrResult *result,
@@ -2432,71 +2504,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
/* Definitely a real MMU, not an MPU */
if (regime_translation_disabled(env, mmu_idx, is_secure)) {
- uint64_t hcr;
- uint8_t memattr;
-
- /*
- * MMU disabled. S1 addresses within aa64 translation regimes are
- * still checked for bounds -- see AArch64.TranslateAddressS1Off.
- */
- if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
- int r_el = regime_el(env, mmu_idx);
- if (arm_el_is_aa64(env, r_el)) {
- int pamax = arm_pamax(env_archcpu(env));
- uint64_t tcr = env->cp15.tcr_el[r_el];
- int addrtop, tbi;
-
- tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
- if (access_type == MMU_INST_FETCH) {
- tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
- }
- tbi = (tbi >> extract64(address, 55, 1)) & 1;
- addrtop = (tbi ? 55 : 63);
-
- if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
- fi->type = ARMFault_AddressSize;
- fi->level = 0;
- fi->stage2 = false;
- return 1;
- }
-
- /*
- * When TBI is disabled, we've just validated that all of the
- * bits above PAMax are zero, so logically we only need to
- * clear the top byte for TBI. But it's clearer to follow
- * the pseudocode set of addrdesc.paddress.
- */
- address = extract64(address, 0, 52);
- }
- }
- result->phys = address;
- result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- result->page_size = TARGET_PAGE_SIZE;
-
- /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
- hcr = arm_hcr_el2_eff_secstate(env, is_secure);
- result->cacheattrs.shareability = 0;
- result->cacheattrs.is_s2_format = false;
- if (hcr & HCR_DC) {
- if (hcr & HCR_DCT) {
- memattr = 0xf0; /* Tagged, Normal, WB, RWA */
- } else {
- memattr = 0xff; /* Normal, WB, RWA */
- }
- } else if (access_type == MMU_INST_FETCH) {
- if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
- memattr = 0xee; /* Normal, WT, RA, NT */
- } else {
- memattr = 0x44; /* Normal, NC, No */
- }
- result->cacheattrs.shareability = 2; /* outer sharable */
- } else {
- memattr = 0x00; /* Device, nGnRnE */
- }
- result->cacheattrs.attrs = memattr;
- return 0;
+ return get_phys_addr_disabled(env, address, access_type, mmu_idx,
+ is_secure, result, fi);
}
-
if (regime_using_lpae_format(env, mmu_idx)) {
return get_phys_addr_lpae(env, address, access_type, mmu_idx,
is_secure, false, result, fi);
--
2.34.1
next prev parent reply other threads:[~2022-10-01 16:43 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-01 16:22 [PATCH v3 00/42] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-10-01 16:22 ` [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr Richard Henderson
2022-10-06 14:27 ` Peter Maydell
2022-10-06 15:10 ` Richard Henderson
2022-10-06 15:22 ` Peter Maydell
2022-10-06 18:20 ` Richard Henderson
2022-10-06 18:55 ` Peter Maydell
2022-10-06 20:58 ` Richard Henderson
2022-10-07 13:50 ` Peter Maydell
2022-10-01 16:22 ` [PATCH v3 02/42] target/arm: Add is_secure parameter to get_phys_addr_lpae Richard Henderson
2022-10-01 16:22 ` [PATCH v3 03/42] target/arm: Fix S2 disabled check in S1_ptw_translate Richard Henderson
2022-10-06 14:28 ` Peter Maydell
2022-10-01 16:22 ` [PATCH v3 04/42] target/arm: Add is_secure parameter to regime_translation_disabled Richard Henderson
2022-10-01 16:22 ` [PATCH v3 05/42] target/arm: Split out get_phys_addr_with_secure Richard Henderson
2022-10-01 16:22 ` [PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn Richard Henderson
2022-10-01 16:22 ` [PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE Richard Henderson
2022-10-01 16:22 ` [PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr Richard Henderson
2022-10-01 16:22 ` [PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write Richard Henderson
2022-10-01 16:22 ` [PATCH v3 10/42] target/arm: Fold secure and non-secure a-profile mmu indexes Richard Henderson
2022-10-01 16:22 ` [PATCH v3 11/42] target/arm: Reorg regime_translation_disabled Richard Henderson
2022-10-01 16:22 ` [PATCH v3 12/42] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Richard Henderson
2022-10-01 16:22 ` [PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate Richard Henderson
2022-10-01 16:22 ` [PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate Richard Henderson
2022-10-01 16:22 ` [PATCH v3 15/42] target/arm: Remove env argument from combined_attrs_fwb Richard Henderson
2022-10-06 14:30 ` Peter Maydell
2022-10-01 16:22 ` [PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines Richard Henderson
2022-10-01 16:22 ` [PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1 Richard Henderson
2022-10-01 16:22 ` Richard Henderson [this message]
2022-10-01 16:22 ` [PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled Richard Henderson
2022-10-06 14:33 ` Peter Maydell
2022-10-01 16:22 ` [PATCH v3 20/42] target/arm: Use tlb_set_page_full Richard Henderson
2022-10-06 14:36 ` Peter Maydell
2022-10-01 16:22 ` [PATCH v3 21/42] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA Richard Henderson
2022-10-06 14:44 ` Peter Maydell
2022-10-01 16:22 ` [PATCH v3 22/42] target/arm: Use probe_access_full for MTE Richard Henderson
2022-10-06 14:52 ` Peter Maydell
2022-10-01 16:22 ` [PATCH v3 23/42] target/arm: Use probe_access_full for BTI Richard Henderson
2022-10-06 14:57 ` Peter Maydell
2022-10-06 18:53 ` Richard Henderson
2022-10-01 16:23 ` [PATCH v3 24/42] target/arm: Add ARMMMUIdx_Phys_{S,NS} Richard Henderson
2022-10-06 15:29 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 25/42] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx Richard Henderson
2022-10-06 15:46 ` Peter Maydell
2022-10-06 19:21 ` Richard Henderson
2022-10-01 16:23 ` [PATCH v3 26/42] target/arm: Plumb debug into S1_ptw_translate Richard Henderson
2022-10-06 15:54 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking Richard Henderson
2022-10-07 9:01 ` Peter Maydell
2022-10-07 15:27 ` Richard Henderson
2022-10-07 16:08 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 28/42] target/arm: Split out get_phys_addr_twostage Richard Henderson
2022-10-06 16:00 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 29/42] target/arm: Use bool consistently for get_phys_addr subroutines Richard Henderson
2022-10-06 16:01 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 30/42] target/arm: Add ptw_idx argument to S1_ptw_translate Richard Henderson
2022-10-07 9:19 ` Peter Maydell
2022-10-07 15:34 ` Richard Henderson
2022-10-01 16:23 ` [PATCH v3 31/42] target/arm: Add isar predicates for FEAT_HAFDBS Richard Henderson
2022-10-07 9:21 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters Richard Henderson
2022-10-07 9:24 ` Peter Maydell
2022-10-07 15:37 ` Richard Henderson
2022-10-07 16:11 ` Peter Maydell
2022-10-07 16:13 ` Richard Henderson
2022-10-07 16:23 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 33/42] target/arm: Split out S1TranslateResult type Richard Henderson
2022-10-07 9:27 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 34/42] target/arm: Move be test for regime into S1TranslateResult Richard Henderson
2022-10-07 9:29 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 35/42] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Richard Henderson
2022-10-07 9:33 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 36/42] target/arm: Add ARMFault_UnsuppAtomicUpdate Richard Henderson
2022-10-07 9:36 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 37/42] target/arm: Remove loop from get_phys_addr_lpae Richard Henderson
2022-10-07 10:20 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 38/42] target/arm: Fix fault reporting in get_phys_addr_lpae Richard Henderson
2022-10-07 10:26 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 39/42] target/arm: Don't shift attrs " Richard Henderson
2022-10-07 10:35 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 40/42] target/arm: Consider GP an attribute " Richard Henderson
2022-10-07 10:40 ` Peter Maydell
2022-10-01 16:23 ` [PATCH v3 41/42] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-10-07 13:47 ` Peter Maydell
2022-10-07 16:04 ` Peter Maydell
2022-10-07 16:45 ` Richard Henderson
2022-10-07 16:50 ` Peter Maydell
2022-10-07 17:35 ` Richard Henderson
2022-10-01 16:23 ` [PATCH v3 42/42] target/arm: Use the max page size in a 2-stage ptw Richard Henderson
2022-10-07 10:42 ` Peter Maydell
2022-10-10 13:10 ` [PATCH v3 00/42] target/arm: Implement FEAT_HAFDBS Peter Maydell
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