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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org, "Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH v7 01/18] cpu: cache CPUClass in CPUState for hot code paths
Date: Tue,  4 Oct 2022 07:10:34 -0700	[thread overview]
Message-ID: <20221004141051.110653-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221004141051.110653-1-richard.henderson@linaro.org>

From: Alex Bennée <alex.bennee@linaro.org>

The class cast checkers are quite expensive and always on (unlike the
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
avoid the overhead of repeatedly checking something which should never
change we cache the CPUClass reference for use in the hot code paths.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220923084803.498337-3-clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/core/cpu.h | 9 +++++++++
 cpu.c                 | 9 ++++-----
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 500503da13..1a7e1a9380 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -51,6 +51,13 @@ typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  */
 #define CPU(obj) ((CPUState *)(obj))
 
+/*
+ * The class checkers bring in CPU_GET_CLASS() which is potentially
+ * expensive given the eventual call to
+ * object_class_dynamic_cast_assert(). Because of this the CPUState
+ * has a cached value for the class in cs->cc which is set up in
+ * cpu_exec_realizefn() for use in hot code paths.
+ */
 typedef struct CPUClass CPUClass;
 DECLARE_CLASS_CHECKERS(CPUClass, CPU,
                        TYPE_CPU)
@@ -317,6 +324,8 @@ struct qemu_work_item;
 struct CPUState {
     /*< private >*/
     DeviceState parent_obj;
+    /* cache to avoid expensive CPU_GET_CLASS */
+    CPUClass *cc;
     /*< public >*/
 
     int nr_cores;
diff --git a/cpu.c b/cpu.c
index 584ac78baf..14365e36f3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -131,9 +131,8 @@ const VMStateDescription vmstate_cpu_common = {
 
 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
 {
-#ifndef CONFIG_USER_ONLY
-    CPUClass *cc = CPU_GET_CLASS(cpu);
-#endif
+    /* cache the cpu class for the hotpath */
+    cpu->cc = CPU_GET_CLASS(cpu);
 
     cpu_list_add(cpu);
     if (!accel_cpu_realizefn(cpu, errp)) {
@@ -151,8 +150,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
         vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
     }
-    if (cc->sysemu_ops->legacy_vmsd != NULL) {
-        vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
+    if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
+        vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
     }
 #endif /* CONFIG_USER_ONLY */
 }
-- 
2.34.1



  reply	other threads:[~2022-10-04 14:36 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-04 14:10 [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Richard Henderson
2022-10-04 14:10 ` Richard Henderson [this message]
2022-10-04 14:10 ` [PATCH v7 02/18] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs Richard Henderson
2022-10-04 14:10 ` [PATCH v7 03/18] cputlb: used cached CPUClass in our hot-paths Richard Henderson
2022-10-04 14:10 ` [PATCH v7 04/18] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull Richard Henderson
2022-10-04 14:10 ` [PATCH v7 05/18] accel/tcg: Drop addr member from SavedIOTLB Richard Henderson
2022-10-04 14:10 ` [PATCH v7 06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal Richard Henderson
2022-10-04 14:10 ` [PATCH v7 07/18] accel/tcg: Introduce probe_access_full Richard Henderson
2022-10-04 14:10 ` [PATCH v7 08/18] accel/tcg: Introduce tlb_set_page_full Richard Henderson
2022-10-11  5:01   ` Alistair Francis
2022-10-11 15:08     ` Richard Henderson
2022-10-04 14:10 ` [PATCH v7 09/18] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA Richard Henderson
2022-10-04 14:10 ` [PATCH v7 10/18] accel/tcg: Remove PageDesc code_bitmap Richard Henderson
2022-10-04 14:10 ` [PATCH v7 11/18] accel/tcg: Use bool for page_find_alloc Richard Henderson
2022-10-04 14:10 ` [PATCH v7 12/18] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Richard Henderson
2022-10-04 14:10 ` [PATCH v7 13/18] accel/tcg: Do not align tb->page_addr[0] Richard Henderson
2022-10-04 15:34   ` Alex Bennée
2022-10-04 14:10 ` [PATCH v7 14/18] accel/tcg: Inline tb_flush_jmp_cache Richard Henderson
2022-10-04 14:10 ` [PATCH v7 15/18] include/hw/core: Create struct CPUJumpCache Richard Henderson
2022-10-04 14:10 ` [PATCH v7 16/18] hw/core: Add CPUClass.get_pc Richard Henderson
2022-10-04 14:10 ` [PATCH v7 17/18] accel/tcg: Introduce tb_pc and log_pc Richard Henderson
2022-10-04 15:39   ` Alex Bennée
2022-10-04 14:10 ` [PATCH v7 18/18] accel/tcg: Introduce TARGET_TB_PCREL Richard Henderson
2022-10-04 15:48   ` Alex Bennée

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