* [PATCH] hw/arm/aspeed: increase Bletchley memory size
@ 2022-10-06 22:52 Patrick Williams
2022-10-07 7:28 ` Cédric Le Goater
2022-10-07 11:05 ` [PATCH v2] " Patrick Williams
0 siblings, 2 replies; 5+ messages in thread
From: Patrick Williams @ 2022-10-06 22:52 UTC (permalink / raw)
Cc: Patrick Williams, Cédric Le Goater, Peter Maydell,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
For the PVT-class hardware we have increased the memory size of
this device to 2 GiB. Adjust the device model accordingly.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
---
hw/arm/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 7d2162c6ed..ab5725fff1 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1344,7 +1344,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = bletchley_bmc_i2c_init;
- mc->default_ram_size = 512 * MiB;
+ mc->default_ram_size = 2 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
}
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] hw/arm/aspeed: increase Bletchley memory size
2022-10-06 22:52 [PATCH] hw/arm/aspeed: increase Bletchley memory size Patrick Williams
@ 2022-10-07 7:28 ` Cédric Le Goater
2022-10-07 8:08 ` Peter Maydell
2022-10-07 11:05 ` [PATCH v2] " Patrick Williams
1 sibling, 1 reply; 5+ messages in thread
From: Cédric Le Goater @ 2022-10-07 7:28 UTC (permalink / raw)
To: Patrick Williams
Cc: Peter Maydell, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here,
Richard Henderson
On 10/7/22 00:52, Patrick Williams wrote:
> For the PVT-class hardware we have increased the memory size of
> this device to 2 GiB. Adjust the device model accordingly.
You should add some defines similar to :
/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
#if HOST_LONG_BITS == 32
#define FUJI_BMC_RAM_SIZE (1 * GiB)
#else
#define FUJI_BMC_RAM_SIZE (2 * GiB)
#endif
or are we done with 32bit hosts ?
Thanks,
C.
>
> Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
> ---
> hw/arm/aspeed.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 7d2162c6ed..ab5725fff1 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1344,7 +1344,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = bletchley_bmc_i2c_init;
> - mc->default_ram_size = 512 * MiB;
> + mc->default_ram_size = 2 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> }
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] hw/arm/aspeed: increase Bletchley memory size
2022-10-07 7:28 ` Cédric Le Goater
@ 2022-10-07 8:08 ` Peter Maydell
0 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2022-10-07 8:08 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Patrick Williams, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here,
Richard Henderson
On Fri, 7 Oct 2022 at 08:28, Cédric Le Goater <clg@kaod.org> wrote:
>
> On 10/7/22 00:52, Patrick Williams wrote:
> > For the PVT-class hardware we have increased the memory size of
> > this device to 2 GiB. Adjust the device model accordingly.
>
> You should add some defines similar to :
>
> /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
> #if HOST_LONG_BITS == 32
> #define FUJI_BMC_RAM_SIZE (1 * GiB)
> #else
> #define FUJI_BMC_RAM_SIZE (2 * GiB)
> #endif
>
> or are we done with 32bit hosts ?
We are not.
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] hw/arm/aspeed: increase Bletchley memory size
2022-10-06 22:52 [PATCH] hw/arm/aspeed: increase Bletchley memory size Patrick Williams
2022-10-07 7:28 ` Cédric Le Goater
@ 2022-10-07 11:05 ` Patrick Williams
2022-10-07 13:13 ` Cédric Le Goater
1 sibling, 1 reply; 5+ messages in thread
From: Patrick Williams @ 2022-10-07 11:05 UTC (permalink / raw)
Cc: Patrick Williams, Cédric Le Goater, Peter Maydell,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
For the PVT-class hardware we have increased the memory size of
this device to 2 GiB. Adjust the device model accordingly.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
---
hw/arm/aspeed.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 7d2162c6ed..f8bc6d4a14 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1330,6 +1330,13 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
aspeed_soc_num_cpus(amc->soc_name);
};
+/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
+#if HOST_LONG_BITS == 32
+#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
+#else
+#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
+#endif
+
static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1344,7 +1351,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = bletchley_bmc_i2c_init;
- mc->default_ram_size = 512 * MiB;
+ mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
}
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2] hw/arm/aspeed: increase Bletchley memory size
2022-10-07 11:05 ` [PATCH v2] " Patrick Williams
@ 2022-10-07 13:13 ` Cédric Le Goater
0 siblings, 0 replies; 5+ messages in thread
From: Cédric Le Goater @ 2022-10-07 13:13 UTC (permalink / raw)
To: Patrick Williams
Cc: Peter Maydell, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here
On 10/7/22 13:05, Patrick Williams wrote:
> For the PVT-class hardware we have increased the memory size of
> this device to 2 GiB. Adjust the device model accordingly.
>
> Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 7d2162c6ed..f8bc6d4a14 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1330,6 +1330,13 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
> aspeed_soc_num_cpus(amc->soc_name);
> };
>
> +/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
> +#if HOST_LONG_BITS == 32
> +#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
> +#else
> +#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
> +#endif
> +
> static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -1344,7 +1351,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = bletchley_bmc_i2c_init;
> - mc->default_ram_size = 512 * MiB;
> + mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> }
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-10-07 14:57 UTC | newest]
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2022-10-06 22:52 [PATCH] hw/arm/aspeed: increase Bletchley memory size Patrick Williams
2022-10-07 7:28 ` Cédric Le Goater
2022-10-07 8:08 ` Peter Maydell
2022-10-07 11:05 ` [PATCH v2] " Patrick Williams
2022-10-07 13:13 ` Cédric Le Goater
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