[PATCH v3 00/35] target/i386: new decoder + AVX implementation

[Paolo Bonzini <pbonzini@redhat.com>]

Both PC-relative translation blocks and XSAVE state support in linux-user
signal handlers are in; as mentioned in the post of v2, this is the time
for a (mostly) final version of the AVX patches, with more review comments
addressed and a few more bugs fixed.

Paolo

v2->v3:
- removed patches that are now upstream
- change if to switch in gen_load_sse
- adjusted generic decoder code (e.g. gen_load_ea) for PC-relative TB changes
- fixed overlap checks for VSIB instructions
- changed vex_class from uint8_t:8 to unsigned:8
- changed gen_MOVD_to to use tcg_gen_st32_tl
- changed make_imm8u_xmm_vec to use cpu_env as base for xmm_t0 access
- changed gen_VZEROUPPER to not use maxsz=32 (for big-endian hosts)
- assume vece == MO_64 in gen_pmovmskb_vec
- fix #ifdef TARGET_I386 vs. #ifdef TARGET_X86_64 confusion
- change MOVNTDQA to use WM operand like LDDQU
- minor changes to fix qemu-i386 compilation (patches 27-29)
- removed dead helper_movq

Paolo Bonzini (30):
  target/i386: make ldo/sto operations consistent with ldq
  target/i386: add core of new i386 decoder
  target/i386: add ALU load/writeback core
  target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContext
  target/i386: add CPUID feature checks to new decoder
  target/i386: validate VEX prefixes via the instructions' exception
    classes
  target/i386: validate SSE prefixes directly in the decoding table
  target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder
  target/i386: extend helpers to support VEX.V 3- and 4- operand
    encodings
  target/i386: support operand merging in binary scalar helpers
  target/i386: provide 3-operand versions of unary scalar helpers
  target/i386: implement additional AVX comparison operators
  target/i386: Introduce 256-bit vector helpers
  target/i386: reimplement 0x0f 0x60-0x6f, add AVX
  target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX
  target/i386: reimplement 0x0f 0x50-0x5f, add AVX
  target/i386: reimplement 0x0f 0x78-0x7f, add AVX
  target/i386: reimplement 0x0f 0x70-0x77, add AVX
  target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX
  target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes
  target/i386: reimplement 0x0f 0x3a, add AVX
  target/i386: reimplement 0x0f 0x38, add AVX
  target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX
  target/i386: reimplement 0x0f 0x10-0x17, add AVX
  target/i386: reimplement 0x0f 0x28-0x2f, add AVX
  target/i386: implement XSAVE and XRSTOR of AVX registers
  target/i386: implement VLDMXCSR/VSTMXCSR
  tests/tcg: extend SSE tests to AVX
  target/i386: move 3DNow to the new decoder
  target/i386: remove old SSE decoder

Paul Brook (3):
  target/i386: add AVX_EN hflag
  target/i386: Prepare ops_sse_header.h for 256 bit AVX
  target/i386: Enable AVX cpuid bits when using TCG

Richard Henderson (2):
  target/i386: Define XMMReg and access macros, align ZMM registers
  target/i386: Use tcg gvec ops for pmovmskb

 target/i386/cpu.c                |   10 +-
 target/i386/cpu.h                |   59 +-
 target/i386/helper.c             |   12 +
 target/i386/helper.h             |    3 +-
 target/i386/ops_sse.h            |  700 ++++++----
 target/i386/ops_sse_header.h     |  347 +++--
 target/i386/tcg/decode-new.c.inc | 1802 ++++++++++++++++++++++++
 target/i386/tcg/decode-new.h     |  249 ++++
 target/i386/tcg/emit.c.inc       | 2239 ++++++++++++++++++++++++++++++
 target/i386/tcg/fpu_helper.c     |   88 +-
 target/i386/tcg/translate.c      | 2078 ++-------------------------
 tests/tcg/i386/Makefile.target   |    2 +-
 tests/tcg/i386/test-avx.c        |  201 +--
 tests/tcg/i386/test-avx.py       |    5 +-
 14 files changed, 5286 insertions(+), 2509 deletions(-)
 create mode 100644 target/i386/tcg/decode-new.c.inc
 create mode 100644 target/i386/tcg/decode-new.h
 create mode 100644 target/i386/tcg/emit.c.inc

-- 
2.37.3