From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: paul@nowt.org, richard.henderson@linaro.org
Subject: [PATCH 23/35] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes
Date: Thu, 13 Oct 2022 23:46:39 +0200 [thread overview]
Message-ID: <20221013214651.672114-24-pbonzini@redhat.com> (raw)
In-Reply-To: <20221013214651.672114-1-pbonzini@redhat.com>
Three-byte opcodes from the 0F3Ah area all have an immediate byte which
is usually unsigned. Clarify in the helper code that it is unsigned;
the new decoder treats immediates as signed by default, and seeing
an intN_t in the prototype might give the wrong impression that one
can use decode->immediate directly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 8 ++++----
| 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 090ba013b3..e7830ff277 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -1605,17 +1605,17 @@ SSE_HELPER_W(helper_psignw, FSIGNW)
SSE_HELPER_L(helper_psignd, FSIGNL)
void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
- int32_t shift)
+ uint32_t imm)
{
int i;
/* XXX could be checked during translation */
- if (shift >= (SHIFT ? 32 : 16)) {
+ if (imm >= (SHIFT ? 32 : 16)) {
for (i = 0; i < (1 << SHIFT); i++) {
d->Q(i) = 0;
}
} else {
- shift <<= 3;
+ int shift = imm * 8;
#define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0)
#if SHIFT == 0
d->Q(0) = SHR(s->Q(0), shift - 0) |
@@ -2093,7 +2093,7 @@ static inline int pcmp_val(Reg *r, uint8_t ctrl, int i)
}
static inline unsigned pcmpxstrx(CPUX86State *env, Reg *d, Reg *s,
- int8_t ctrl, int valids, int validd)
+ uint8_t ctrl, int valids, int validd)
{
unsigned int res = 0;
int v;
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 440f1c0e78..98178be148 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -335,7 +335,7 @@ DEF_HELPER_4(glue(pshufb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignd, SUFFIX), void, env, Reg, Reg, Reg)
-DEF_HELPER_5(glue(palignr, SUFFIX), void, env, Reg, Reg, Reg, s32)
+DEF_HELPER_5(glue(palignr, SUFFIX), void, env, Reg, Reg, Reg, i32)
/* SSE4.1 op helpers */
#if SHIFT >= 1
--
2.37.3
next prev parent reply other threads:[~2022-10-13 22:12 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 21:46 [PATCH v3 00/35] target/i386: new decoder + AVX implementation Paolo Bonzini
2022-10-13 21:46 ` [PATCH 01/35] target/i386: Define XMMReg and access macros, align ZMM registers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 02/35] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
2022-10-13 21:46 ` [PATCH 03/35] target/i386: add core of new i386 decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 04/35] target/i386: add ALU load/writeback core Paolo Bonzini
2022-10-13 21:46 ` [PATCH 05/35] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext Paolo Bonzini
2022-10-13 21:46 ` [PATCH 06/35] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 07/35] target/i386: add AVX_EN hflag Paolo Bonzini
2022-10-13 21:46 ` [PATCH 08/35] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
2022-10-13 21:46 ` [PATCH 09/35] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
2022-10-13 21:46 ` [PATCH 10/35] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 11/35] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 12/35] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
2022-10-13 21:46 ` [PATCH 13/35] target/i386: support operand merging in binary scalar helpers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 14/35] target/i386: provide 3-operand versions of unary " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 15/35] target/i386: implement additional AVX comparison operators Paolo Bonzini
2022-10-13 21:46 ` [PATCH 16/35] target/i386: Introduce 256-bit vector helpers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 17/35] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 18/35] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 19/35] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 20/35] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 21/35] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 22/35] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
2022-10-13 21:46 ` Paolo Bonzini [this message]
2022-10-13 21:46 ` [PATCH 24/35] target/i386: reimplement 0x0f 0x3a, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 25/35] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
2022-10-13 21:46 ` [PATCH 26/35] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 27/35] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 28/35] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 29/35] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 30/35] target/i386: implement XSAVE and XRSTOR of AVX registers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 31/35] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
2022-10-13 21:46 ` [PATCH 32/35] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
2022-10-13 21:46 ` [PATCH 33/35] tests/tcg: extend SSE tests to AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 34/35] target/i386: move 3DNow to the new decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 35/35] target/i386: remove old SSE decoder Paolo Bonzini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221013214651.672114-24-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=paul@nowt.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).