From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: paul@nowt.org, richard.henderson@linaro.org
Subject: [PATCH 05/35] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext
Date: Thu, 13 Oct 2022 23:46:21 +0200 [thread overview]
Message-ID: <20221013214651.672114-6-pbonzini@redhat.com> (raw)
In-Reply-To: <20221013214651.672114-1-pbonzini@redhat.com>
TCG will shortly implement VAES instructions, so add the relevant feature
word to the DisasContext.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 4403d376e0..f3ba3275d2 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -116,6 +116,7 @@ typedef struct DisasContext {
int cpuid_ext2_features;
int cpuid_ext3_features;
int cpuid_7_0_ebx_features;
+ int cpuid_7_0_ecx_features;
int cpuid_xsave_features;
/* TCG local temps */
@@ -8851,6 +8852,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
+ dc->cpuid_7_0_ecx_features = env->features[FEAT_7_0_ECX];
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
--
2.37.3
next prev parent reply other threads:[~2022-10-13 21:54 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 21:46 [PATCH v3 00/35] target/i386: new decoder + AVX implementation Paolo Bonzini
2022-10-13 21:46 ` [PATCH 01/35] target/i386: Define XMMReg and access macros, align ZMM registers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 02/35] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
2022-10-13 21:46 ` [PATCH 03/35] target/i386: add core of new i386 decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 04/35] target/i386: add ALU load/writeback core Paolo Bonzini
2022-10-13 21:46 ` Paolo Bonzini [this message]
2022-10-13 21:46 ` [PATCH 06/35] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 07/35] target/i386: add AVX_EN hflag Paolo Bonzini
2022-10-13 21:46 ` [PATCH 08/35] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
2022-10-13 21:46 ` [PATCH 09/35] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
2022-10-13 21:46 ` [PATCH 10/35] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 11/35] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 12/35] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
2022-10-13 21:46 ` [PATCH 13/35] target/i386: support operand merging in binary scalar helpers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 14/35] target/i386: provide 3-operand versions of unary " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 15/35] target/i386: implement additional AVX comparison operators Paolo Bonzini
2022-10-13 21:46 ` [PATCH 16/35] target/i386: Introduce 256-bit vector helpers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 17/35] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 18/35] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 19/35] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 20/35] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 21/35] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 22/35] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 23/35] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes Paolo Bonzini
2022-10-13 21:46 ` [PATCH 24/35] target/i386: reimplement 0x0f 0x3a, add AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 25/35] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
2022-10-13 21:46 ` [PATCH 26/35] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 27/35] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 28/35] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 29/35] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
2022-10-13 21:46 ` [PATCH 30/35] target/i386: implement XSAVE and XRSTOR of AVX registers Paolo Bonzini
2022-10-13 21:46 ` [PATCH 31/35] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
2022-10-13 21:46 ` [PATCH 32/35] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
2022-10-13 21:46 ` [PATCH 33/35] tests/tcg: extend SSE tests to AVX Paolo Bonzini
2022-10-13 21:46 ` [PATCH 34/35] target/i386: move 3DNow to the new decoder Paolo Bonzini
2022-10-13 21:46 ` [PATCH 35/35] target/i386: remove old SSE decoder Paolo Bonzini
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