* [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro
@ 2022-10-17 5:49 Wilfred Mallawa
2022-10-17 5:49 ` [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro Wilfred Mallawa
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Wilfred Mallawa @ 2022-10-17 5:49 UTC (permalink / raw)
To: alistair, qemu-riscv; +Cc: qemu-devel, Wilfred Mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This patch series implements a `FIELDx_1CLEAR()` macro and implements it
in the `hw/ssi/ibex_spi.c` model.
*** Changelog ***
Since v2:
- change the macro arguments name to match
the existing macros.
(reg_val, reg, field) -> (storage, reg, field)
- Add the use of this macro to `ibex_spi`
Since v1:
- Instead of needing all field bits to be set
we clear the field if any are set.
If the field is 0/clear then no change.
Wilfred Mallawa (2):
hw/registerfields: add `FIELDx_1CLEAR()` macro
hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
hw/ssi/ibex_spi_host.c | 21 +++++++++------------
include/hw/registerfields.h | 22 ++++++++++++++++++++++
2 files changed, 31 insertions(+), 12 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro
2022-10-17 5:49 [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro Wilfred Mallawa
@ 2022-10-17 5:49 ` Wilfred Mallawa
2022-10-24 3:26 ` Alistair Francis
2022-10-17 5:49 ` [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Wilfred Mallawa
2022-10-24 5:02 ` [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro Alistair Francis
2 siblings, 1 reply; 6+ messages in thread
From: Wilfred Mallawa @ 2022-10-17 5:49 UTC (permalink / raw)
To: alistair, qemu-riscv; +Cc: qemu-devel, Wilfred Mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Adds a helper macro that implements the register `w1c`
functionality.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
If ANY bits of the specified `FIELD` is set
then the respective field is cleared and returned to `data`.
If the field is cleared (0), then no change and
val is returned.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
include/hw/registerfields.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 1330ca77de..0b8404c2f7 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -115,6 +115,28 @@
R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
_d; })
+/*
+ * Clear the specified field in storage if
+ * any field bits are set, else no changes made. Implements
+ * single/multi-bit `w1c`
+ *
+ */
+#define FIELD8_1CLEAR(storage, reg, field) \
+ (FIELD_EX8(storage, reg, field) ? \
+ FIELD_DP8(storage, reg, field, 0x00) : storage)
+
+#define FIELD16_1CLEAR(storage, reg, field) \
+ (FIELD_EX16(storage, reg, field) ? \
+ FIELD_DP16(storage, reg, field, 0x00) : storage)
+
+#define FIELD32_1CLEAR(storage, reg, field) \
+ (FIELD_EX32(storage, reg, field) ? \
+ FIELD_DP32(storage, reg, field, 0x00) : storage)
+
+#define FIELD64_1CLEAR(storage, reg, field) \
+ (FIELD_EX64(storage, reg, field) ? \
+ FIELD_DP64(storage, reg, field, 0x00) : storage)
+
#define FIELD_SDP8(storage, reg, field, val) ({ \
struct { \
signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
--
2.37.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
2022-10-17 5:49 [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro Wilfred Mallawa
2022-10-17 5:49 ` [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro Wilfred Mallawa
@ 2022-10-17 5:49 ` Wilfred Mallawa
2022-10-24 3:25 ` Alistair Francis
2022-10-24 5:02 ` [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro Alistair Francis
2 siblings, 1 reply; 6+ messages in thread
From: Wilfred Mallawa @ 2022-10-17 5:49 UTC (permalink / raw)
To: alistair, qemu-riscv; +Cc: qemu-devel, Wilfred Mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
use the `FIELD32_1CLEAR` macro to implement register
`rw1c` functionality to `ibex_spi`.
This change was tested by running the `SPI_HOST` from TockOS.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
hw/ssi/ibex_spi_host.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index 57df462e3c..0a456cd1ed 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -342,7 +342,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
{
IbexSPIHostState *s = opaque;
uint32_t val32 = val64;
- uint32_t shift_mask = 0xff, status = 0, data = 0;
+ uint32_t shift_mask = 0xff, status = 0;
uint8_t txqd_len;
trace_ibex_spi_host_write(addr, size, val64);
@@ -355,12 +355,11 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
case IBEX_SPI_HOST_INTR_STATE:
/* rw1c status register */
if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
- data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, ERROR);
}
if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
- data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, SPI_EVENT);
}
- s->regs[addr] = data;
break;
case IBEX_SPI_HOST_INTR_ENABLE:
s->regs[addr] = val32;
@@ -505,27 +504,25 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
* When an error occurs, the corresponding bit must be cleared
* here before issuing any further commands
*/
- status = s->regs[addr];
/* rw1c status register */
if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
- status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDBUSY);
}
if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
- status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, OVERFLOW);
}
if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
- status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, UNDERFLOW);
}
if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
- status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDINVAL);
}
if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
- status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CSIDINVAL);
}
if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
- status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
+ s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, ACCESSINVAL);
}
- s->regs[addr] = status;
break;
case IBEX_SPI_HOST_EVENT_ENABLE:
/* Controls which classes of SPI events raise an interrupt. */
--
2.37.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
2022-10-17 5:49 ` [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Wilfred Mallawa
@ 2022-10-24 3:25 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2022-10-24 3:25 UTC (permalink / raw)
To: Wilfred Mallawa; +Cc: alistair, qemu-riscv, qemu-devel, Wilfred Mallawa
On Mon, Oct 17, 2022 at 3:55 PM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> use the `FIELD32_1CLEAR` macro to implement register
> `rw1c` functionality to `ibex_spi`.
>
> This change was tested by running the `SPI_HOST` from TockOS.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/ssi/ibex_spi_host.c | 21 +++++++++------------
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
> index 57df462e3c..0a456cd1ed 100644
> --- a/hw/ssi/ibex_spi_host.c
> +++ b/hw/ssi/ibex_spi_host.c
> @@ -342,7 +342,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
> {
> IbexSPIHostState *s = opaque;
> uint32_t val32 = val64;
> - uint32_t shift_mask = 0xff, status = 0, data = 0;
> + uint32_t shift_mask = 0xff, status = 0;
> uint8_t txqd_len;
>
> trace_ibex_spi_host_write(addr, size, val64);
> @@ -355,12 +355,11 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
> case IBEX_SPI_HOST_INTR_STATE:
> /* rw1c status register */
> if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
> - data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, ERROR);
> }
> if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
> - data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, SPI_EVENT);
> }
> - s->regs[addr] = data;
> break;
> case IBEX_SPI_HOST_INTR_ENABLE:
> s->regs[addr] = val32;
> @@ -505,27 +504,25 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
> * When an error occurs, the corresponding bit must be cleared
> * here before issuing any further commands
> */
> - status = s->regs[addr];
> /* rw1c status register */
> if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
> - status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDBUSY);
> }
> if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
> - status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, OVERFLOW);
> }
> if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
> - status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, UNDERFLOW);
> }
> if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
> - status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDINVAL);
> }
> if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
> - status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CSIDINVAL);
> }
> if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
> - status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
> + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, ACCESSINVAL);
> }
> - s->regs[addr] = status;
> break;
> case IBEX_SPI_HOST_EVENT_ENABLE:
> /* Controls which classes of SPI events raise an interrupt. */
> --
> 2.37.3
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro
2022-10-17 5:49 ` [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro Wilfred Mallawa
@ 2022-10-24 3:26 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2022-10-24 3:26 UTC (permalink / raw)
To: Wilfred Mallawa; +Cc: alistair, qemu-riscv, qemu-devel, Wilfred Mallawa
On Mon, Oct 17, 2022 at 3:59 PM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Adds a helper macro that implements the register `w1c`
> functionality.
>
> Ex:
> uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
>
> If ANY bits of the specified `FIELD` is set
> then the respective field is cleared and returned to `data`.
>
> If the field is cleared (0), then no change and
> val is returned.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/registerfields.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> index 1330ca77de..0b8404c2f7 100644
> --- a/include/hw/registerfields.h
> +++ b/include/hw/registerfields.h
> @@ -115,6 +115,28 @@
> R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
> _d; })
>
> +/*
> + * Clear the specified field in storage if
> + * any field bits are set, else no changes made. Implements
> + * single/multi-bit `w1c`
> + *
> + */
> +#define FIELD8_1CLEAR(storage, reg, field) \
> + (FIELD_EX8(storage, reg, field) ? \
> + FIELD_DP8(storage, reg, field, 0x00) : storage)
> +
> +#define FIELD16_1CLEAR(storage, reg, field) \
> + (FIELD_EX16(storage, reg, field) ? \
> + FIELD_DP16(storage, reg, field, 0x00) : storage)
> +
> +#define FIELD32_1CLEAR(storage, reg, field) \
> + (FIELD_EX32(storage, reg, field) ? \
> + FIELD_DP32(storage, reg, field, 0x00) : storage)
> +
> +#define FIELD64_1CLEAR(storage, reg, field) \
> + (FIELD_EX64(storage, reg, field) ? \
> + FIELD_DP64(storage, reg, field, 0x00) : storage)
> +
> #define FIELD_SDP8(storage, reg, field, val) ({ \
> struct { \
> signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
> --
> 2.37.3
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro
2022-10-17 5:49 [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro Wilfred Mallawa
2022-10-17 5:49 ` [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro Wilfred Mallawa
2022-10-17 5:49 ` [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Wilfred Mallawa
@ 2022-10-24 5:02 ` Alistair Francis
2 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2022-10-24 5:02 UTC (permalink / raw)
To: Wilfred Mallawa; +Cc: alistair, qemu-riscv, qemu-devel, Wilfred Mallawa
On Mon, Oct 17, 2022 at 3:52 PM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> This patch series implements a `FIELDx_1CLEAR()` macro and implements it
> in the `hw/ssi/ibex_spi.c` model.
>
> *** Changelog ***
> Since v2:
> - change the macro arguments name to match
> the existing macros.
> (reg_val, reg, field) -> (storage, reg, field)
>
> - Add the use of this macro to `ibex_spi`
>
> Since v1:
> - Instead of needing all field bits to be set
> we clear the field if any are set.
> If the field is 0/clear then no change.
>
> Wilfred Mallawa (2):
> hw/registerfields: add `FIELDx_1CLEAR()` macro
> hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/ssi/ibex_spi_host.c | 21 +++++++++------------
> include/hw/registerfields.h | 22 ++++++++++++++++++++++
> 2 files changed, 31 insertions(+), 12 deletions(-)
>
> --
> 2.37.3
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-10-24 6:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-10-17 5:49 [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro Wilfred Mallawa
2022-10-17 5:49 ` [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro Wilfred Mallawa
2022-10-24 3:26 ` Alistair Francis
2022-10-17 5:49 ` [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Wilfred Mallawa
2022-10-24 3:25 ` Alistair Francis
2022-10-24 5:02 ` [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro Alistair Francis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).