* [PULL 00/38] ppc queue
@ 2022-10-17 19:19 Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 01/38] MAINTAINERS: step back from PPC Daniel Henrique Barboza
` (38 more replies)
0 siblings, 39 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, stefanha, Daniel Henrique Barboza
The following changes since commit 5c2439a92ce4a1c5a53070bd803d6f7647e702ca:
Merge tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu into staging (2022-10-16 15:53:13 -0400)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20221017
for you to fetch changes up to 719b718ce27f52b2da600cc1abf6a41ac54dfa36:
hw/riscv: set machine->fdt in spike_board_init() (2022-10-17 16:15:10 -0300)
----------------------------------------------------------------
ppc patch queue for 2022-10-17:
This queue contains improvements in the e500 and ppc4xx boards, changes
in the maintainership of the project, a new QMP/HMP command and bug
fixes:
- Cedric is stepping back from qemu-ppc maintainership;
- ppc4xx_sdram: QOMification and clean ups;
- e500: add new types of flash and clean ups;
- QMP/HMP: introduce dumpdtb command;
- spapr_pci, booke doorbell interrupt and xvcmp* bit fixes;
The 'dumpdtb' implementation is also making changes to RISC-V files that
were acked by Alistair Francis and are being included in this queue.
----------------------------------------------------------------
BALATON Zoltan (17):
ppc440_bamboo: Remove unnecessary memsets
ppc4xx: Introduce Ppc4xxSdramBank struct
ppc4xx_sdram: Get rid of the init RAM hack
ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
ppc440_bamboo: Add missing 4 MiB valid memory size
ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
ppc4xx_sdram: QOM'ify
ppc4xx_sdram: Drop extra zeros for readability
ppc440_sdram: Split off map/unmap of sdram banks for later reuse
ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller
ppc440_sdram: Get rid of the init RAM hack
ppc440_sdram: Rename local variable for readability
ppc4xx_sdram: Rename functions to prevent name clashes
ppc440_sdram: Move RAM size check to ppc440_sdram_init
ppc440_sdram: QOM'ify
ppc440_uc.c: Move some macros to ppc4xx.h
ppc440_uc.c: Remove unneeded parenthesis
Bernhard Beschow (7):
hw/ppc/meson: Allow e500 boards to be enabled separately
hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx
docs/system/ppc/ppce500: Add heading for networking chapter
hw/ppc/e500: Reduce usage of sysbus API
hw/ppc/mpc8544ds: Rename wrongly named method
hw/ppc/mpc8544ds: Add platform bus
hw/ppc/e500: Remove if statement which is now always true
Cédric Le Goater (1):
MAINTAINERS: step back from PPC
Daniel Henrique Barboza (10):
qmp/hmp, device_tree.c: introduce dumpdtb
hw/nios2: set machine->fdt in nios2_load_dtb()
hw/ppc: set machine->fdt in bamboo_load_device_tree()
hw/ppc: set machine->fdt in sam460ex_load_device_tree()
hw/ppc: set machine->fdt in xilinx_load_device_tree()
hw/ppc: set machine->fdt in pegasos2_machine_reset()
hw/ppc: set machine->fdt in pnv_reset()
hw/ppc: set machine->fdt in spapr machine
hw/riscv: set machine->fdt in sifive_u_machine_init()
hw/riscv: set machine->fdt in spike_board_init()
Nicholas Piggin (1):
target/ppc: restore powerpc_excp_booke doorbell interrupts
Peter Maydell (1):
hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset()
Víctor Colombo (1):
target/ppc: Fix xvcmp* clearing FI bit
MAINTAINERS | 10 +-
configs/devices/ppc-softmmu/default.mak | 3 +-
docs/system/ppc/ppce500.rst | 3 +
hmp-commands.hx | 15 ++
hw/gpio/Kconfig | 3 +
hw/gpio/meson.build | 2 +-
hw/nios2/boot.c | 8 +-
hw/nios2/meson.build | 2 +-
hw/ppc/Kconfig | 9 ++
hw/ppc/e500.c | 30 ++--
hw/ppc/e500.h | 1 -
hw/ppc/e500plat.c | 1 -
hw/ppc/meson.build | 6 +-
hw/ppc/mpc8544ds.c | 9 +-
hw/ppc/pegasos2.c | 4 +
hw/ppc/pnv.c | 8 +-
hw/ppc/ppc405.h | 8 +-
hw/ppc/ppc405_boards.c | 13 +-
hw/ppc/ppc405_uc.c | 33 ++--
hw/ppc/ppc440.h | 4 -
hw/ppc/ppc440_bamboo.c | 50 +++----
hw/ppc/ppc440_uc.c | 257 ++++++++++++++++++++------------
hw/ppc/ppc4xx_devs.c | 241 +++++++++++++++---------------
hw/ppc/sam460ex.c | 65 ++++----
hw/ppc/spapr.c | 3 +
hw/ppc/spapr_hcall.c | 8 +
hw/ppc/spapr_pci.c | 2 +-
hw/ppc/virtex_ml507.c | 25 ++--
hw/riscv/sifive_u.c | 3 +
hw/riscv/spike.c | 6 +
include/hw/ppc/ppc4xx.h | 63 +++++++-
include/sysemu/device_tree.h | 1 +
monitor/misc.c | 1 +
qapi/machine.json | 18 +++
softmmu/device_tree.c | 37 +++++
target/ppc/excp_helper.c | 6 +
target/ppc/translate/vsx-impl.c.inc | 1 -
37 files changed, 589 insertions(+), 370 deletions(-)
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PULL 01/38] MAINTAINERS: step back from PPC
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 02/38] target/ppc: restore powerpc_excp_booke doorbell interrupts Daniel Henrique Barboza
` (37 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Cédric Le Goater, Greg Kurz,
David Gibson, Alex Bennée, Daniel Henrique Barboza
From: Cédric Le Goater <clg@kaod.org>
I am not active anymore on the PPC maintainership, degrade my self as
standard Reviewer. Also degrade PowerNV and XIVE status since I am not
funded for this work.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220929180946.848721-1-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
MAINTAINERS | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8ae2e43c83..d86d21ae4e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -267,8 +267,8 @@ F: hw/openrisc/
F: tests/tcg/openrisc/
PowerPC TCG CPUs
-M: Cédric Le Goater <clg@kaod.org>
M: Daniel Henrique Barboza <danielhb413@gmail.com>
+R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
@@ -392,8 +392,8 @@ F: target/mips/kvm*
F: target/mips/sysemu/
PPC KVM CPUs
-M: Cédric Le Goater <clg@kaod.org>
M: Daniel Henrique Barboza <danielhb413@gmail.com>
+R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
S: Maintained
@@ -1365,8 +1365,8 @@ F: include/hw/rtc/m48t59.h
F: tests/avocado/ppc_prep_40p.py
sPAPR (pseries)
-M: Cédric Le Goater <clg@kaod.org>
M: Daniel Henrique Barboza <danielhb413@gmail.com>
+R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
@@ -1387,7 +1387,7 @@ F: tests/avocado/ppc_pseries.py
PowerNV (Non-Virtualized)
M: Cédric Le Goater <clg@kaod.org>
L: qemu-ppc@nongnu.org
-S: Maintained
+S: Odd Fixes
F: docs/system/ppc/powernv.rst
F: hw/ppc/pnv*
F: hw/intc/pnv*
@@ -2333,7 +2333,7 @@ T: git https://github.com/philmd/qemu.git fw_cfg-next
XIVE
M: Cédric Le Goater <clg@kaod.org>
L: qemu-ppc@nongnu.org
-S: Supported
+S: Odd Fixes
F: hw/*/*xive*
F: include/hw/*/*xive*
F: docs/*/*xive*
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 02/38] target/ppc: restore powerpc_excp_booke doorbell interrupts
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 01/38] MAINTAINERS: step back from PPC Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 03/38] ppc440_bamboo: Remove unnecessary memsets Daniel Henrique Barboza
` (36 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Nicholas Piggin, Cédric Le Goater,
Daniel Henrique Barboza
From: Nicholas Piggin <npiggin@gmail.com>
This partially reverts commit 9dc20cc37db9 ("target/ppc: Simplify
powerpc_excp_booke"), which removed DOORI and DOORCI interrupts.
Without this patch, a -cpu e5500 -smp 2 machine booting Linux
crashes with:
qemu: fatal: Invalid PowerPC exception 36. Aborting
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220924114436.1422786-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/excp_helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 214acf5ac4..43f2480e94 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1247,6 +1247,12 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
break;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ break;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
cpu_abort(cs, "Trying to deliver power-saving system reset "
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 03/38] ppc440_bamboo: Remove unnecessary memsets
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 01/38] MAINTAINERS: step back from PPC Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 02/38] target/ppc: restore powerpc_excp_booke doorbell interrupts Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 04/38] ppc4xx: Introduce Ppc4xxSdramBank struct Daniel Henrique Barboza
` (35 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, stefanha, BALATON Zoltan, Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no
need to clear its elements. In the bamboo machine init memset can be
replaced with array initialiser which is shorter.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <529adc7705fb3e3e777439895bdaa136bacb9403.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_bamboo.c | 6 ++----
hw/ppc/ppc4xx_devs.c | 8 ++------
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index ea945a1c99..5ec82fa8c2 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -169,8 +169,8 @@ static void bamboo_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
- hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
- hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
+ hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -205,8 +205,6 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- memset(ram_bases, 0, sizeof(ram_bases));
- memset(ram_sizes, 0, sizeof(ram_sizes));
ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index ce38ae65e6..b4cd10f735 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -363,12 +363,8 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
sdram->ram_memories = ram_memories;
- memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
- memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(hwaddr));
- memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(hwaddr));
+ memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
+ memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 04/38] ppc4xx: Introduce Ppc4xxSdramBank struct
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (2 preceding siblings ...)
2022-10-17 19:19 ` [PULL 03/38] ppc440_bamboo: Remove unnecessary memsets Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 05/38] ppc4xx_sdram: Get rid of the init RAM hack Daniel Henrique Barboza
` (34 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <5eb82d0424c584b2b9e6f7bc51560f8189ed21bb.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_uc.c | 49 +++++++++++++++++-----------------
hw/ppc/ppc4xx_devs.c | 59 ++++++++++++++++++++---------------------
include/hw/ppc/ppc4xx.h | 8 ++++++
3 files changed, 61 insertions(+), 55 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 53e981ddf4..db33334e29 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -16,7 +16,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "exec/memory.h"
-#include "hw/ppc/ppc.h"
+#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
#include "sysemu/block-backend.h"
@@ -485,11 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
int nbanks;
- MemoryRegion containers[4]; /* used for clipping */
- MemoryRegion *ram_memories;
- hwaddr ram_bases[4];
- hwaddr ram_sizes[4];
- uint32_t bcr[4];
+ Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
enum {
@@ -570,23 +566,23 @@ static uint64_t sdram_size(uint32_t bcr)
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bcr[i] & 1) {
+ if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
memory_region_del_subregion(get_system_memory(),
- &sdram->containers[i]);
- memory_region_del_subregion(&sdram->containers[i],
- &sdram->ram_memories[i]);
- object_unparent(OBJECT(&sdram->containers[i]));
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
}
- sdram->bcr[i] = bcr & 0xffe0ffc1;
+ sdram->bank[i].bcr = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
- memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
- memory_region_add_subregion(&sdram->containers[i], 0,
- &sdram->ram_memories[i]);
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
sdram_base(bcr),
- &sdram->containers[i]);
+ &sdram->bank[i].container);
}
}
@@ -595,9 +591,9 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
- sdram->ram_sizes[i]), 1);
+ if (sdram->bank[i].size != 0) {
+ sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0, 0);
}
@@ -614,9 +610,9 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R1BAS:
case SDRAM_R2BAS:
case SDRAM_R3BAS:
- if (sdram->ram_sizes[dcrn - SDRAM_R0BAS]) {
- ret = sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS],
- sdram->ram_sizes[dcrn - SDRAM_R0BAS]);
+ if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
+ ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -701,12 +697,15 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
int do_init)
{
ppc440_sdram_t *sdram;
+ int i;
sdram = g_malloc0(sizeof(*sdram));
sdram->nbanks = nbanks;
- sdram->ram_memories = ram_memories;
- memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
+ for (i = 0; i < nbanks; i++) {
+ sdram->bank[i].ram = ram_memories[i];
+ sdram->bank[i].base = ram_bases[i];
+ sdram->bank[i].size = ram_sizes[i];
+ }
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index b4cd10f735..1226ec4aa9 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -42,10 +42,7 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
- MemoryRegion containers[4]; /* used for clipping */
- MemoryRegion *ram_memories;
- hwaddr ram_bases[4];
- hwaddr ram_sizes[4];
+ Ppc4xxSdramBank bank[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
@@ -53,7 +50,6 @@ struct ppc4xx_sdram_t {
uint32_t status;
uint32_t rtr;
uint32_t pmit;
- uint32_t bcr[4];
uint32_t tr;
uint32_t ecccfg;
uint32_t eccesr;
@@ -131,26 +127,26 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bcr[i] & 0x00000001) {
+ if (sdram->bank[i].bcr & 0x00000001) {
/* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
- &sdram->containers[i]);
- memory_region_del_subregion(&sdram->containers[i],
- &sdram->ram_memories[i]);
- object_unparent(OBJECT(&sdram->containers[i]));
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
}
- sdram->bcr[i] = bcr & 0xFFDEE001;
+ sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
- memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
- memory_region_add_subregion(&sdram->containers[i], 0,
- &sdram->ram_memories[i]);
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
sdram_base(bcr),
- &sdram->containers[i]);
+ &sdram->bank[i].container);
}
}
@@ -159,9 +155,9 @@ static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
- sdram->ram_sizes[i]), 1);
+ if (sdram->bank[i].size != 0) {
+ sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0x00000000, 0);
}
@@ -173,10 +169,10 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
- &sdram->ram_memories[i]);
+ &sdram->bank[i].ram);
}
}
@@ -214,16 +210,16 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = sdram->pmit;
break;
case 0x40: /* SDRAM_B0CR */
- ret = sdram->bcr[0];
+ ret = sdram->bank[0].bcr;
break;
case 0x44: /* SDRAM_B1CR */
- ret = sdram->bcr[1];
+ ret = sdram->bank[1].bcr;
break;
case 0x48: /* SDRAM_B2CR */
- ret = sdram->bcr[2];
+ ret = sdram->bank[2].bcr;
break;
case 0x4C: /* SDRAM_B3CR */
- ret = sdram->bcr[3];
+ ret = sdram->bank[3].bcr;
break;
case 0x80: /* SDRAM_TR */
ret = -1; /* ? */
@@ -358,13 +354,16 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
int do_init)
{
ppc4xx_sdram_t *sdram;
+ int i;
sdram = g_new0(ppc4xx_sdram_t, 1);
sdram->irq = irq;
sdram->nbanks = nbanks;
- sdram->ram_memories = ram_memories;
- memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
+ for (i = 0; i < nbanks; i++) {
+ sdram->bank[i].ram = ram_memories[i];
+ sdram->bank[i].base = ram_bases[i];
+ sdram->bank[i].size = ram_sizes[i];
+ }
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index a1781afa8e..2af0d60577 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -29,6 +29,14 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
+typedef struct {
+ MemoryRegion ram;
+ MemoryRegion container; /* used for clipping */
+ hwaddr base;
+ hwaddr size;
+ uint32_t bcr;
+} Ppc4xxSdramBank;
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
hwaddr ram_bases[], hwaddr ram_sizes[],
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 05/38] ppc4xx_sdram: Get rid of the init RAM hack
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (3 preceding siblings ...)
2022-10-17 19:19 ` [PULL 04/38] ppc4xx: Introduce Ppc4xxSdramBank struct Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 06/38] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() Daniel Henrique Barboza
` (33 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, stefanha, BALATON Zoltan, Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. Do this from board code emulating what firmware would do
when booting a kernel directly from -kernel without a firmware so we
can get rid of this do_init hack.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <d6c44c870befa1a075e21f1a59926dcdaff63f6b.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc405.h | 1 -
hw/ppc/ppc405_boards.c | 3 +--
hw/ppc/ppc405_uc.c | 4 +---
hw/ppc/ppc440_bamboo.c | 4 +++-
hw/ppc/ppc4xx_devs.c | 12 +++++++-----
include/hw/ppc/ppc4xx.h | 5 +++--
6 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 1e558c7831..756865621b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -169,7 +169,6 @@ struct Ppc405SoCState {
/* Public */
MemoryRegion ram_banks[2];
hwaddr ram_bases[2], ram_sizes[2];
- bool do_dram_init;
MemoryRegion *dram_mr;
hwaddr ram_size;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 083f12b23e..1eaeca8806 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -288,8 +288,6 @@ static void ppc405_init(MachineState *machine)
machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
- object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
- kernel_filename != NULL, &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
&error_abort);
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
@@ -349,6 +347,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
+ ppc4xx_sdram_enable(&ppc405->soc.cpu.env);
boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2ca42fdef6..1e02347e57 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->ram_bases[0], s->ram_sizes[0]);
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks, s->ram_bases, s->ram_sizes,
- s->do_dram_init);
+ s->ram_banks, s->ram_bases, s->ram_sizes);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 5ec82fa8c2..409a8840da 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -211,7 +211,9 @@ static void bamboo_init(MachineState *machine)
ppc4xx_sdram_init(env,
qdev_get_gpio_in(uicdev, 14),
PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
+ ram_bases, ram_sizes);
+ /* Enable SDRAM memory regions, this should be done by the firmware */
+ ppc4xx_sdram_enable(env);
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 1226ec4aa9..3475589679 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -350,8 +350,7 @@ static void sdram_reset(void *opaque)
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
hwaddr *ram_bases,
- hwaddr *ram_sizes,
- int do_init)
+ hwaddr *ram_sizes)
{
ppc4xx_sdram_t *sdram;
int i;
@@ -369,9 +368,12 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
- if (do_init) {
- sdram_map_bcr(sdram);
- }
+}
+
+void ppc4xx_sdram_enable(CPUPPCState *env)
+{
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20);
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000);
}
/*
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 2af0d60577..13b3229851 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,6 +37,8 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
+void ppc4xx_sdram_enable(CPUPPCState *env);
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
hwaddr ram_bases[], hwaddr ram_sizes[],
@@ -45,8 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
hwaddr *ram_bases,
- hwaddr *ram_sizes,
- int do_init);
+ hwaddr *ram_sizes);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 06/38] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (4 preceding siblings ...)
2022-10-17 19:19 ` [PULL 05/38] ppc4xx_sdram: Get rid of the init RAM hack Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 07/38] ppc440_bamboo: Add missing 4 MiB valid memory size Daniel Henrique Barboza
` (32 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <e3a1fea51f29779fd6a61be90a29c684f3299544.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc405.h | 4 +---
hw/ppc/ppc405_uc.c | 10 +++++-----
hw/ppc/ppc440.h | 5 ++---
hw/ppc/ppc440_bamboo.c | 15 ++++++---------
hw/ppc/ppc440_uc.c | 9 ++++-----
hw/ppc/ppc4xx_devs.c | 21 +++++++++------------
hw/ppc/sam460ex.c | 15 +++++----------
include/hw/ppc/ppc4xx.h | 9 +++------
8 files changed, 35 insertions(+), 53 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 756865621b..ca0972b88b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- MemoryRegion ram_banks[2];
- hwaddr ram_bases[2], ram_sizes[2];
-
+ Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
hwaddr ram_size;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 1e02347e57..bcbf35bc14 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1074,14 +1074,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- s->ram_bases[0] = 0;
- s->ram_sizes[0] = s->ram_size;
- memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
+ s->ram_banks[0].base = 0;
+ s->ram_banks[0].size = s->ram_size;
+ memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
"ppc405.sdram0", s->dram_mr,
- s->ram_bases[0], s->ram_sizes[0]);
+ s->ram_banks[0].base, s->ram_banks[0].size);
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks, s->ram_bases, s->ram_sizes);
+ s->ram_banks);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 7cef936125..e6c905b7d6 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,14 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc.h"
+#include "hw/ppc/ppc4xx.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases, hwaddr *ram_sizes,
+ Ppc4xxSdramBank *ram_banks,
int do_init);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 409a8840da..edfb8c9709 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -168,9 +168,8 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
- hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
- hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
+ Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
+ PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -205,13 +204,11 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
+ ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env,
- qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes);
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
+ PPC440EP_SDRAM_NR_BANKS, ram_banks);
/* Enable SDRAM memory regions, this should be done by the firmware */
ppc4xx_sdram_enable(env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index db33334e29..8eae4ad9f0 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -692,8 +692,7 @@ static void sdram_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases, hwaddr *ram_sizes,
+ Ppc4xxSdramBank *ram_banks,
int do_init)
{
ppc440_sdram_t *sdram;
@@ -702,9 +701,9 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram = g_malloc0(sizeof(*sdram));
sdram->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_memories[i];
- sdram->bank[i].base = ram_bases[i];
- sdram->bank[i].size = ram_sizes[i];
+ sdram->bank[i].ram = ram_banks[i].ram;
+ sdram->bank[i].base = ram_banks[i].base;
+ sdram->bank[i].size = ram_banks[i].size;
}
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 3475589679..fcbda57c55 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -348,9 +348,7 @@ static void sdram_reset(void *opaque)
}
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases,
- hwaddr *ram_sizes)
+ Ppc4xxSdramBank *ram_banks)
{
ppc4xx_sdram_t *sdram;
int i;
@@ -359,9 +357,9 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_memories[i];
- sdram->bank[i].base = ram_bases[i];
- sdram->bank[i].size = ram_sizes[i];
+ sdram->bank[i].ram = ram_banks[i].ram;
+ sdram->bank[i].base = ram_banks[i].base;
+ sdram->bank[i].size = ram_banks[i].size;
}
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
@@ -387,8 +385,7 @@ void ppc4xx_sdram_enable(CPUPPCState *env)
* sizes varies by SoC.
*/
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[], hwaddr ram_sizes[],
+ Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[])
{
ram_addr_t size_left = memory_region_size(ram);
@@ -403,13 +400,13 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
if (bank_size <= size_left) {
char name[32];
- ram_bases[i] = base;
- ram_sizes[i] = bank_size;
+ ram_banks[i].base = base;
+ ram_banks[i].size = bank_size;
base += bank_size;
size_left -= bank_size;
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- memory_region_init_alias(&ram_memories[i], NULL, name, ram,
- ram_bases[i], ram_sizes[i]);
+ memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
+ ram_banks[i].base, ram_banks[i].size);
break;
}
}
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 850bb3b817..f4c2a693fb 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -73,7 +73,6 @@
#define OPB_FREQ 115000000
#define EBC_FREQ 115000000
#define UART_FREQ 11059200
-#define SDRAM_NR_BANKS 4
/* The SoC could also handle 4 GiB but firmware does not work with that. */
/* Maybe it overflows a signed 32 bit number somewhere? */
@@ -274,9 +273,7 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
- hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
- hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
+ Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -345,20 +342,18 @@ static void sam460ex_init(MachineState *machine)
/* SDRAM controller */
/* put all RAM on first bank because board has one slot
* and firmware only checks that */
- ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes,
- ppc460ex_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
+ ppc440_sdram_init(env, 1, ram_banks, 1);
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
qdev_get_gpio_in(uic[0], 2));
i2c = PPC4xx_I2C(dev)->bus;
/* SPD EEPROM on RAM module */
- spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2,
- ram_sizes[0]);
+ spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
+ ram_banks->size);
spd_data[20] = 4; /* SO-DIMM module */
smbus_eeprom_init_one(i2c, 0x50, spd_data);
/* RTC */
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 13b3229851..a7b41c7eaa 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -40,14 +40,11 @@ typedef struct {
void ppc4xx_sdram_enable(CPUPPCState *env);
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[], hwaddr ram_sizes[],
+ Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
-void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion ram_memories[],
- hwaddr *ram_bases,
- hwaddr *ram_sizes);
+void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
+ Ppc4xxSdramBank *ram_banks);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 07/38] ppc440_bamboo: Add missing 4 MiB valid memory size
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (5 preceding siblings ...)
2022-10-17 19:19 ` [PULL 06/38] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 08/38] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() Daniel Henrique Barboza
` (31 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <05836e38be84729c1c6b5b609e7aa2ea60435033.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index edfb8c9709..7ec7c7c43d 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -51,7 +51,7 @@
#define PPC440EP_SDRAM_NR_BANKS 4
static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
static hwaddr entry;
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 08/38] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (6 preceding siblings ...)
2022-10-17 19:19 ` [PULL 07/38] ppc440_bamboo: Add missing 4 MiB valid memory size Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 09/38] ppc4xx_sdram: QOM'ify Daniel Henrique Barboza
` (30 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <39e5129dd095b285676a6267c5753786da1bc30d.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10 ----------
hw/ppc/ppc405_uc.c | 11 ++---------
hw/ppc/ppc440_bamboo.c | 10 +---------
hw/ppc/ppc4xx_devs.c | 14 ++++++--------
include/hw/ppc/ppc4xx.h | 2 +-
6 files changed, 10 insertions(+), 39 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ca0972b88b..ad54dff542 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
- hwaddr ram_size;
PowerPCCPU cpu;
PPCUIC uic;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1eaeca8806..824acf7a80 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -271,21 +271,11 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
- MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
MemoryRegion *sysmem = get_system_memory();
- if (machine->ram_size != mc->default_ram_size) {
- char *sz = size_to_str(mc->default_ram_size);
- error_report("Invalid RAM size, should be %s", sz);
- g_free(sz);
- exit(EXIT_FAILURE);
- }
-
object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
TYPE_PPC405_SOC);
- object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
- machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index bcbf35bc14..e1c7188e61 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1073,15 +1073,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- /* XXX 405EP has no ECC interrupt */
- s->ram_banks[0].base = 0;
- s->ram_banks[0].size = s->ram_size;
- memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
- "ppc405.sdram0", s->dram_mr,
- s->ram_banks[0].base, s->ram_banks[0].size);
-
+ /* XXX 405EP has no ECC interrupt */
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks);
+ s->dram_mr);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1159,7 +1153,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 7ec7c7c43d..91d9a4eef3 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -50,10 +50,6 @@
#define PPC440EP_SDRAM_NR_BANKS 4
-static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
-};
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
- PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
- ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, ram_banks);
+ PPC440EP_SDRAM_NR_BANKS, machine->ram);
/* Enable SDRAM memory regions, this should be done by the firmware */
ppc4xx_sdram_enable(env);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index fcbda57c55..2e0343970f 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -41,7 +41,7 @@
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
- int nbanks;
+ int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
uint32_t besr0;
uint32_t besr1;
@@ -348,19 +348,17 @@ static void sdram_reset(void *opaque)
}
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- Ppc4xxSdramBank *ram_banks)
+ MemoryRegion *ram)
{
ppc4xx_sdram_t *sdram;
- int i;
+ const ram_addr_t valid_bank_sizes[] = {
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
+ };
sdram = g_new0(ppc4xx_sdram_t, 1);
sdram->irq = irq;
sdram->nbanks = nbanks;
- for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_banks[i].ram;
- sdram->bank[i].base = ram_banks[i].base;
- sdram->bank[i].size = ram_banks[i].size;
- }
+ ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index a7b41c7eaa..1d41db9b30 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -44,7 +44,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
const ram_addr_t sdram_bank_sizes[]);
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- Ppc4xxSdramBank *ram_banks);
+ MemoryRegion *ram);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 09/38] ppc4xx_sdram: QOM'ify
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (7 preceding siblings ...)
2022-10-17 19:19 ` [PULL 08/38] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 10/38] ppc4xx_sdram: Drop extra zeros for readability Daniel Henrique Barboza
` (29 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use it for those now. This
likely does not cause problems for guests we run as the new features
are just not accessed but to model 405 SoC accurately some features
may have to be disabled or the model split between 440 and older.
Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an
updated DDR2 SDRAM controller implemented by the ppc440_sdram model
(only partially, enough for the 460EX on the sam460ex) that is not yet
QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2
when QOM'ified later.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <8f820487fc9011343032c422ecdf3e8ee74d8c11.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc405.h | 3 +-
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc405_uc.c | 22 +++++----
hw/ppc/ppc440_bamboo.c | 12 +++--
hw/ppc/ppc4xx_devs.c | 105 ++++++++++++++++++++++------------------
include/hw/ppc/ppc4xx.h | 31 ++++++++++--
6 files changed, 105 insertions(+), 70 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ad54dff542..9a4312691e 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,8 +167,6 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- MemoryRegion *dram_mr;
-
PowerPCCPU cpu;
PPCUIC uic;
Ppc405CpcState cpc;
@@ -182,6 +180,7 @@ struct Ppc405SoCState {
Ppc405PobState pob;
Ppc4xxPlbState plb;
Ppc4xxMalState mal;
+ Ppc4xxSdramDdrState sdram;
};
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 824acf7a80..b59393d4bd 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -337,7 +337,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- ppc4xx_sdram_enable(&ppc405->soc.cpu.env);
+ ppc4xx_sdram_enable(&ppc405->soc.sdram);
boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e1c7188e61..c973cfb04e 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1016,6 +1016,9 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB);
object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
+
+ object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR);
+ object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram");
}
static void ppc405_reset(void *opaque)
@@ -1073,9 +1076,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+ /*
+ * We use the 440 DDR SDRAM controller which has more regs and features
+ * but it's compatible enough for now
+ */
+ object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
+ return;
+ }
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->dram_mr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0,
+ qdev_get_gpio_in(DEVICE(&s->uic), 17));
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1150,12 +1161,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Uses UIC IRQs 9, 15, 17 */
}
-static Property ppc405_soc_properties[] = {
- DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void ppc405_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -1163,7 +1168,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
dc->realize = ppc405_soc_realize;
/* Reason: only works as part of a ppc405 board/machine */
dc->user_creatable = false;
- device_class_set_props(dc, ppc405_soc_properties);
}
static const TypeInfo ppc405_types[] = {
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 91d9a4eef3..5c35ba6086 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -48,8 +48,6 @@
#define PPC440EP_PCI_IO 0xe8000000
#define PPC440EP_PCI_IOLEN 0x00010000
-#define PPC440EP_SDRAM_NR_BANKS 4
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -198,11 +196,15 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
+ object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, machine->ram);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14));
/* Enable SDRAM memory regions, this should be done by the firmware */
- ppc4xx_sdram_enable(env);
+ ppc4xx_sdram_enable(PPC4xx_SDRAM_DDR(dev));
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 2e0343970f..3d700e5c85 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -38,24 +38,6 @@
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
-struct ppc4xx_sdram_t {
- uint32_t addr;
- int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
- Ppc4xxSdramBank bank[4];
- uint32_t besr0;
- uint32_t besr1;
- uint32_t bear;
- uint32_t cfg;
- uint32_t status;
- uint32_t rtr;
- uint32_t pmit;
- uint32_t tr;
- uint32_t ecccfg;
- uint32_t eccesr;
- qemu_irq irq;
-};
-
enum {
SDRAM0_CFGADDR = 0x010,
SDRAM0_CFGDATA = 0x011,
@@ -66,7 +48,7 @@ enum {
* there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -124,7 +106,7 @@ static target_ulong sdram_size(uint32_t bcr)
return size;
}
-static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
+static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 0x00000001) {
@@ -150,21 +132,21 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
}
-static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
+static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
+ sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0x00000000, 0);
}
}
}
-static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
+static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
@@ -176,12 +158,11 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = opaque;
uint32_t ret;
- sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
ret = sdram->addr;
@@ -244,11 +225,10 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = opaque;
- sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
sdram->addr = val;
@@ -327,11 +307,10 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_reset(void *opaque)
+static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
- sdram = opaque;
sdram->addr = 0x00000000;
sdram->bear = 0x00000000;
sdram->besr0 = 0x00000000; /* No error */
@@ -347,29 +326,54 @@ static void sdram_reset(void *opaque)
sdram->cfg = 0x00800000;
}
-void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram)
+static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
const ram_addr_t valid_bank_sizes[] = {
256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
- sdram = g_new0(ppc4xx_sdram_t, 1);
- sdram->irq = irq;
- sdram->nbanks = nbanks;
- ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
- qemu_register_reset(&sdram_reset, sdram);
- ppc_dcr_register(env, SDRAM0_CFGADDR,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
- ppc_dcr_register(env, SDRAM0_CFGDATA,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
}
-void ppc4xx_sdram_enable(CPUPPCState *env)
+static Property ppc4xx_sdram_ddr_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr_realize;
+ dc->reset = ppc4xx_sdram_ddr_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr_props);
+}
+
+void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s)
{
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20);
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000);
+ sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
+ sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
}
/*
@@ -959,6 +963,11 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
+ .name = TYPE_PPC4xx_SDRAM_DDR,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdrState),
+ .class_init = ppc4xx_sdram_ddr_class_init,
+ }, {
.name = TYPE_PPC4xx_MAL,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc4xxMalState),
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 1d41db9b30..558500fb97 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,15 +37,10 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
-void ppc4xx_sdram_enable(CPUPPCState *env);
-
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
-void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram);
-
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/*
@@ -115,4 +110,30 @@ struct Ppc4xxEbcState {
uint32_t cfg;
};
+/* SDRAM DDR controller */
+#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
+struct Ppc4xxSdramDdrState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion *dram_mr;
+ uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
+ Ppc4xxSdramBank bank[4];
+ qemu_irq irq;
+
+ uint32_t addr;
+ uint32_t besr0;
+ uint32_t besr1;
+ uint32_t bear;
+ uint32_t cfg;
+ uint32_t status;
+ uint32_t rtr;
+ uint32_t pmit;
+ uint32_t tr;
+ uint32_t ecccfg;
+ uint32_t eccesr;
+};
+
+void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s);
+
#endif /* PPC4XX_H */
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 10/38] ppc4xx_sdram: Drop extra zeros for readability
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (8 preceding siblings ...)
2022-10-17 19:19 ` [PULL 09/38] ppc4xx_sdram: QOM'ify Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 11/38] ppc440_sdram: Split off map/unmap of sdram banks for later reuse Daniel Henrique Barboza
` (28 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <93974622c3d398c7d3a3488b678b74c3807849de.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc4xx_devs.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 3d700e5c85..02ac8ff335 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -54,31 +54,31 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
switch (ram_size) {
case 4 * MiB:
- bcr = 0x00000000;
+ bcr = 0;
break;
case 8 * MiB:
- bcr = 0x00020000;
+ bcr = 0x20000;
break;
case 16 * MiB:
- bcr = 0x00040000;
+ bcr = 0x40000;
break;
case 32 * MiB:
- bcr = 0x00060000;
+ bcr = 0x60000;
break;
case 64 * MiB:
- bcr = 0x00080000;
+ bcr = 0x80000;
break;
case 128 * MiB:
- bcr = 0x000A0000;
+ bcr = 0xA0000;
break;
case 256 * MiB:
- bcr = 0x000C0000;
+ bcr = 0xC0000;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
ram_size);
- return 0x00000000;
+ return 0;
}
bcr |= ram_base & 0xFF800000;
bcr |= 1;
@@ -109,7 +109,7 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bank[i].bcr & 0x00000001) {
+ if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
sdram_size(sdram->bank[i].bcr));
@@ -120,7 +120,7 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
object_unparent(OBJECT(&sdram->bank[i].container));
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
- if (enabled && (bcr & 0x00000001)) {
+ if (enabled && (bcr & 1)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
@@ -141,7 +141,7 @@ static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0x00000000, 0);
+ sdram_set_bcr(sdram, i, 0, 0);
}
}
}
@@ -218,7 +218,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
break;
default:
/* Avoid gcc warning */
- ret = 0x00000000;
+ ret = 0;
break;
}
@@ -311,18 +311,18 @@ static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
- sdram->addr = 0x00000000;
- sdram->bear = 0x00000000;
- sdram->besr0 = 0x00000000; /* No error */
- sdram->besr1 = 0x00000000; /* No error */
- sdram->cfg = 0x00000000;
- sdram->ecccfg = 0x00000000; /* No ECC */
- sdram->eccesr = 0x00000000; /* No error */
+ sdram->addr = 0;
+ sdram->bear = 0;
+ sdram->besr0 = 0; /* No error */
+ sdram->besr1 = 0; /* No error */
+ sdram->cfg = 0;
+ sdram->ecccfg = 0; /* No ECC */
+ sdram->eccesr = 0; /* No error */
sdram->pmit = 0x07C00000;
sdram->rtr = 0x05F00000;
sdram->tr = 0x00854009;
/* We pre-initialize RAM banks */
- sdram->status = 0x00000000;
+ sdram->status = 0;
sdram->cfg = 0x00800000;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 11/38] ppc440_sdram: Split off map/unmap of sdram banks for later reuse
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (9 preceding siblings ...)
2022-10-17 19:19 ` [PULL 10/38] ppc4xx_sdram: Drop extra zeros for readability Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 12/38] ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller Daniel Henrique Barboza
` (27 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <23560b6a71682d513f3dd8e9ed3852f51d5eb309.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_uc.c | 33 +++++++++++++++++++++------------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 8eae4ad9f0..900b7ab998 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -23,6 +23,7 @@
#include "sysemu/reset.h"
#include "ppc440.h"
#include "qom/object.h"
+#include "trace.h"
/*****************************************************************************/
/* L2 Cache as SRAM */
@@ -563,26 +564,34 @@ static uint64_t sdram_size(uint32_t bcr)
return size;
}
+static void sdram_bank_map(Ppc4xxSdramBank *bank)
+{
+ memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
+ memory_region_add_subregion(&bank->container, 0, &bank->ram);
+ memory_region_add_subregion(get_system_memory(), bank->base,
+ &bank->container);
+}
+
+static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
+{
+ memory_region_del_subregion(get_system_memory(), &bank->container);
+ memory_region_del_subregion(&bank->container, &bank->ram);
+ object_unparent(OBJECT(&bank->container));
+}
+
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].container);
- memory_region_del_subregion(&sdram->bank[i].container,
- &sdram->bank[i].ram);
- object_unparent(OBJECT(&sdram->bank[i].container));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
+ sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
- memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
- memory_region_add_subregion(&sdram->bank[i].container, 0,
- &sdram->bank[i].ram);
- memory_region_add_subregion(get_system_memory(),
- sdram_base(bcr),
- &sdram->bank[i].container);
+ trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ sdram_bank_map(&sdram->bank[i]);
}
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 12/38] ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (10 preceding siblings ...)
2022-10-17 19:19 ` [PULL 11/38] ppc440_sdram: Split off map/unmap of sdram banks for later reuse Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 13/38] ppc440_sdram: Get rid of the init RAM hack Daniel Henrique Barboza
` (26 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, stefanha, BALATON Zoltan, Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <f8900aadb1a4426a6444741e6876c898b3b77f7b.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_uc.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 900b7ab998..3fbfe4ad13 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -485,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/* SDRAM controller */
typedef struct ppc440_sdram_t {
uint32_t addr;
+ uint32_t mcopt2;
int nbanks;
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -600,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size != 0) {
+ if (sdram->bank[i].size) {
sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
@@ -609,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
}
}
+static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size) {
+ sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ }
+ }
+}
+
static uint32_t dcr_read_sdram(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
@@ -640,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = 0x80000000;
break;
case 0x21: /* SDRAM_MCOPT2 */
- ret = 0x08000000;
+ ret = sdram->mcopt2;
break;
case 0x40: /* SDRAM_MB0CF */
ret = 0x00008001;
@@ -662,6 +674,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
+#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
+
static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -684,6 +698,21 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
switch (sdram->addr) {
case 0x00: /* B0CR */
break;
+ case 0x21: /* SDRAM_MCOPT2 */
+ if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ (val & SDRAM_DDR2_MCOPT2_DCEN)) {
+ trace_ppc4xx_sdram_enable("enable");
+ /* validate all RAM mappings */
+ sdram_map_bcr(sdram);
+ sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
+ } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
+ trace_ppc4xx_sdram_enable("disable");
+ /* invalidate all RAM mappings */
+ sdram_unmap_bcr(sdram);
+ sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
+ }
+ break;
default:
break;
}
@@ -698,6 +727,7 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
+ sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN;
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 13/38] ppc440_sdram: Get rid of the init RAM hack
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (11 preceding siblings ...)
2022-10-17 19:19 ` [PULL 12/38] ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 14/38] ppc440_sdram: Rename local variable for readability Daniel Henrique Barboza
` (25 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, stefanha, BALATON Zoltan, Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <c2eda8f83c82f655aa7821a5a8c9310484bd6a1d.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440.h | 3 +--
hw/ppc/ppc440_uc.c | 15 +++++++++------
hw/ppc/sam460ex.c | 4 +++-
include/hw/ppc/ppc4xx.h | 2 ++
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index e6c905b7d6..01d76b8000 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init);
+ Ppc4xxSdramBank *ram_banks);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 3fbfe4ad13..e8bc088c8f 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -16,6 +16,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "exec/memory.h"
+#include "cpu.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
@@ -727,12 +728,11 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
- sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN;
+ sdram->mcopt2 = 0;
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init)
+ Ppc4xxSdramBank *ram_banks)
{
ppc440_sdram_t *sdram;
int i;
@@ -749,9 +749,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
- if (do_init) {
- sdram_map_bcr(sdram);
- }
ppc_dcr_register(env, SDRAM_R0BAS,
sdram, &dcr_read_sdram, &dcr_write_sdram);
@@ -773,6 +770,12 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
}
+void ppc440_sdram_enable(CPUPPCState *env)
+{
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21);
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000);
+}
+
/*****************************************************************************/
/* PLB to AHB bridge */
enum {
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index f4c2a693fb..9c01211b20 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -345,7 +345,9 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, 1, ram_banks, 1);
+ ppc440_sdram_init(env, 1, ram_banks);
+ /* Enable SDRAM memory regions as we may boot without firmware */
+ ppc440_sdram_enable(env);
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 558500fb97..78a845399e 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,6 +37,8 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
+void ppc440_sdram_enable(CPUPPCState *env);
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 14/38] ppc440_sdram: Rename local variable for readability
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (12 preceding siblings ...)
2022-10-17 19:19 ` [PULL 13/38] ppc440_sdram: Get rid of the init RAM hack Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 15/38] ppc4xx_sdram: Rename functions to prevent name clashes Daniel Henrique Barboza
` (24 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Rename local sdram variable in ppc440_sdram_init to s for readability.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <7351b80fa321c32a6229e685dfdc940232f8b788.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_uc.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index e8bc088c8f..97e6d5f5b2 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -734,40 +734,40 @@ static void sdram_reset(void *opaque)
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
Ppc4xxSdramBank *ram_banks)
{
- ppc440_sdram_t *sdram;
+ ppc440_sdram_t *s;
int i;
- sdram = g_malloc0(sizeof(*sdram));
- sdram->nbanks = nbanks;
+ s = g_malloc0(sizeof(*s));
+ s->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_banks[i].ram;
- sdram->bank[i].base = ram_banks[i].base;
- sdram->bank[i].size = ram_banks[i].size;
+ s->bank[i].ram = ram_banks[i].ram;
+ s->bank[i].base = ram_banks[i].base;
+ s->bank[i].size = ram_banks[i].size;
}
- qemu_register_reset(&sdram_reset, sdram);
+ qemu_register_reset(&sdram_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R0BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R1BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R2BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R3BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1HB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1LL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
}
void ppc440_sdram_enable(CPUPPCState *env)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 15/38] ppc4xx_sdram: Rename functions to prevent name clashes
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (13 preceding siblings ...)
2022-10-17 19:19 ` [PULL 14/38] ppc440_sdram: Rename local variable for readability Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 16/38] ppc440_sdram: Move RAM size check to ppc440_sdram_init Daniel Henrique Barboza
` (23 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <9c09d10fbf36940ebbe30d7038d69cf3f2e58371.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc440_bamboo.c | 2 +-
hw/ppc/ppc440_uc.c | 67 +++++++++++++++++++++--------------------
hw/ppc/ppc4xx_devs.c | 46 ++++++++++++++--------------
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 4 +--
6 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index b59393d4bd..4092ebc1ab 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -337,7 +337,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- ppc4xx_sdram_enable(&ppc405->soc.sdram);
+ ppc4xx_sdram_ddr_enable(&ppc405->soc.sdram);
boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 5c35ba6086..56f47e7509 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -204,7 +204,7 @@ static void bamboo_init(MachineState *machine)
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14));
/* Enable SDRAM memory regions, this should be done by the firmware */
- ppc4xx_sdram_enable(PPC4xx_SDRAM_DDR(dev));
+ ppc4xx_sdram_ddr_enable(PPC4xx_SDRAM_DDR(dev));
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 97e6d5f5b2..edd0781eb7 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -505,7 +505,7 @@ enum {
SDRAM_PLBADDUHB = 0x50,
};
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -550,12 +550,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
{
return (bcr & 0xffe00000) << 2;
}
-static uint64_t sdram_size(uint32_t bcr)
+static uint64_t sdram_ddr2_size(uint32_t bcr)
{
uint64_t size;
int sh;
@@ -581,48 +581,49 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
-static void sdram_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr2_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
}
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
uint32_t ret = 0;
@@ -633,8 +634,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R2BAS:
case SDRAM_R3BAS:
if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
+ ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -677,7 +678,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -704,13 +705,13 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr2_map_bcr(sdram);
sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
} else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr2_unmap_bcr(sdram);
sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
}
break;
@@ -723,7 +724,7 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_reset(void *opaque)
+static void sdram_ddr2_reset(void *opaque)
{
ppc440_sdram_t *sdram = opaque;
@@ -744,33 +745,33 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
s->bank[i].base = ram_banks[i].base;
s->bank[i].size = ram_banks[i].size;
}
- qemu_register_reset(&sdram_reset, s);
+ qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R0BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R1BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R2BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R3BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1LL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
}
-void ppc440_sdram_enable(CPUPPCState *env)
+void ppc4xx_sdram_ddr2_enable(CPUPPCState *env)
{
ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21);
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 02ac8ff335..12af90f244 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -86,12 +86,12 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
-static target_ulong sdram_size(uint32_t bcr)
+static target_ulong sdram_ddr_size(uint32_t bcr)
{
target_ulong size;
int sh;
@@ -106,13 +106,13 @@ static target_ulong sdram_size(uint32_t bcr)
return size;
}
-static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].container);
memory_region_del_subregion(&sdram->bank[i].container,
@@ -121,38 +121,38 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
+ sdram_ddr_size(bcr));
memory_region_add_subregion(&sdram->bank[i].container, 0,
&sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
- sdram_base(bcr),
+ sdram_ddr_base(bcr),
&sdram->bank[i].container);
}
}
-static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size != 0) {
- sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
+ sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].ram);
}
@@ -249,12 +249,12 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr_map_bcr(sdram);
sdram->status &= ~0x80000000;
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr_unmap_bcr(sdram);
sdram->status |= 0x80000000;
}
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
@@ -274,16 +274,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
@@ -370,7 +370,7 @@ static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
device_class_set_props(dc, ppc4xx_sdram_ddr_props);
}
-void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s)
+void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
{
sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 9c01211b20..b318521b01 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -347,7 +347,7 @@ static void sam460ex_init(MachineState *machine)
/* FIXME: does 460EX have ECC interrupts? */
ppc440_sdram_init(env, 1, ram_banks);
/* Enable SDRAM memory regions as we may boot without firmware */
- ppc440_sdram_enable(env);
+ ppc4xx_sdram_ddr2_enable(env);
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 78a845399e..fd0b3ca82a 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,7 +37,7 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
-void ppc440_sdram_enable(CPUPPCState *env);
+void ppc4xx_sdram_ddr2_enable(CPUPPCState *env);
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
@@ -136,6 +136,6 @@ struct Ppc4xxSdramDdrState {
uint32_t eccesr;
};
-void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s);
+void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s);
#endif /* PPC4XX_H */
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 16/38] ppc440_sdram: Move RAM size check to ppc440_sdram_init
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (14 preceding siblings ...)
2022-10-17 19:19 ` [PULL 15/38] ppc4xx_sdram: Rename functions to prevent name clashes Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 17/38] ppc440_sdram: QOM'ify Daniel Henrique Barboza
` (22 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Move the check for valid memory sizes from board to sdram controller
init. This adds the missing valid memory sizes of 16 and 8 MiB to the
DoC and the board now only checks for additional restrictions imposed
by its firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <41da3797392acaacc7963b79512c8af8005fa4b0.1664021647.git.balaton@eik.bme.hu>
[danielhb: avoid 4*GiB size due to 32 bit build problems]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440.h | 4 ++--
hw/ppc/ppc440_uc.c | 19 +++++++++++--------
hw/ppc/sam460ex.c | 32 +++++++++++++++++---------------
3 files changed, 30 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 01d76b8000..29f6f14ed7 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,13 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc4xx.h"
+#include "hw/ppc/ppc.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks);
+ MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index edd0781eb7..dd873d892c 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -487,7 +487,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
uint32_t mcopt2;
- int nbanks;
+ int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -733,18 +733,21 @@ static void sdram_ddr2_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks)
+ MemoryRegion *ram)
{
ppc440_sdram_t *s;
- int i;
+ /*
+ * SoC also has 4 GiB but that causes problem with 32 bit
+ * builds (4*GiB overflows the 32 bit ram_addr_t).
+ */
+ const ram_addr_t valid_bank_sizes[] = {
+ 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB,
+ 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
+ };
s = g_malloc0(sizeof(*s));
s->nbanks = nbanks;
- for (i = 0; i < nbanks; i++) {
- s->bank[i].ram = ram_banks[i].ram;
- s->bank[i].base = ram_banks[i].base;
- s->bank[i].size = ram_banks[i].size;
- }
+ ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index b318521b01..13055a8916 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -74,13 +74,6 @@
#define EBC_FREQ 115000000
#define UART_FREQ 11059200
-/* The SoC could also handle 4 GiB but firmware does not work with that. */
-/* Maybe it overflows a signed 32 bit number somewhere? */
-static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
- 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
- 32 * MiB, 0
-};
-
struct boot_info {
uint32_t dt_base;
uint32_t dt_size;
@@ -273,7 +266,6 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -340,12 +332,22 @@ static void sam460ex_init(MachineState *machine)
}
/* SDRAM controller */
- /* put all RAM on first bank because board has one slot
- * and firmware only checks that */
- ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
-
+ /* The SoC could also handle 4 GiB but firmware does not work with that. */
+ if (machine->ram_size > 2 * GiB) {
+ error_report("Memory over 2 GiB is not supported");
+ exit(1);
+ }
+ /* Firmware needs at least 64 MiB */
+ if (machine->ram_size < 64 * MiB) {
+ error_report("Memory below 64 MiB is not supported");
+ exit(1);
+ }
+ /*
+ * Put all RAM on first bank because board has one slot
+ * and firmware only checks that
+ */
+ ppc440_sdram_init(env, 1, machine->ram);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, 1, ram_banks);
/* Enable SDRAM memory regions as we may boot without firmware */
ppc4xx_sdram_ddr2_enable(env);
@@ -354,8 +356,8 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 2));
i2c = PPC4xx_I2C(dev)->bus;
/* SPD EEPROM on RAM module */
- spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
- ram_banks->size);
+ spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2,
+ machine->ram_size);
spd_data[20] = 4; /* SO-DIMM module */
smbus_eeprom_init_one(i2c, 0x50, spd_data);
/* RTC */
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 17/38] ppc440_sdram: QOM'ify
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (15 preceding siblings ...)
2022-10-17 19:19 ` [PULL 16/38] ppc440_sdram: Move RAM size check to ppc440_sdram_init Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 18/38] ppc440_uc.c: Move some macros to ppc4xx.h Daniel Henrique Barboza
` (21 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <3e82ae575c7c41e464a0082d55ecb4ebcc4d4329.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440.h | 2 -
hw/ppc/ppc440_uc.c | 121 ++++++++++++++++++++++++----------------
hw/ppc/sam460ex.c | 9 ++-
include/hw/ppc/ppc4xx.h | 18 +++++-
4 files changed, 97 insertions(+), 53 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 29f6f14ed7..7c24db8504 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -16,8 +16,6 @@
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index dd873d892c..55082f2b88 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -484,13 +484,6 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc440_sdram_t {
- uint32_t addr;
- uint32_t mcopt2;
- int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
- Ppc4xxSdramBank bank[4];
-} ppc440_sdram_t;
-
enum {
SDRAM0_CFGADDR = 0x10,
SDRAM0_CFGDATA,
@@ -581,7 +574,7 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
@@ -597,7 +590,7 @@ static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
}
}
-static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -612,7 +605,7 @@ static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
}
}
-static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -625,7 +618,7 @@ static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = opaque;
uint32_t ret = 0;
switch (dcrn) {
@@ -680,7 +673,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = opaque;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -724,18 +717,18 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_ddr2_reset(void *opaque)
+static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
sdram->addr = 0;
sdram->mcopt2 = 0;
}
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram)
+static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
{
- ppc440_sdram_t *s;
+ Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
/*
* SoC also has 4 GiB but that causes problem with 32 bit
* builds (4*GiB overflows the 32 bit ram_addr_t).
@@ -745,41 +738,75 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
};
- s = g_malloc0(sizeof(*s));
- s->nbanks = nbanks;
- ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
- qemu_register_reset(&sdram_ddr2_reset, s);
- ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-
- ppc_dcr_register(env, SDRAM_R0BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R1BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R2BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R3BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_PLBADDULL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONF1LL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONFPATHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_PLBADDUHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+
+ ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr2_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr2_realize;
+ dc->reset = ppc4xx_sdram_ddr2_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
}
-void ppc4xx_sdram_ddr2_enable(CPUPPCState *env)
+void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
{
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21);
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000);
+ sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
+ sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
}
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_SDRAM_DDR2,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdr2State),
+ .class_init = ppc4xx_sdram_ddr2_class_init,
+ }
+};
+DEFINE_TYPES(ppc4xx_types)
+
/*****************************************************************************/
/* PLB to AHB bridge */
enum {
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 13055a8916..f03cdc9ecc 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -342,14 +342,19 @@ static void sam460ex_init(MachineState *machine)
error_report("Memory below 64 MiB is not supported");
exit(1);
}
+ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
+ object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
/*
* Put all RAM on first bank because board has one slot
* and firmware only checks that
*/
- ppc440_sdram_init(env, 1, machine->ram);
+ object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* FIXME: does 460EX have ECC interrupts? */
/* Enable SDRAM memory regions as we may boot without firmware */
- ppc4xx_sdram_ddr2_enable(env);
+ ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev));
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index fd0b3ca82a..ff88385ac0 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,8 +37,6 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
-void ppc4xx_sdram_ddr2_enable(CPUPPCState *env);
-
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
@@ -138,4 +136,20 @@ struct Ppc4xxSdramDdrState {
void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s);
+/* SDRAM DDR2 controller */
+#define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2);
+struct Ppc4xxSdramDdr2State {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion *dram_mr;
+ uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
+ Ppc4xxSdramBank bank[4];
+
+ uint32_t addr;
+ uint32_t mcopt2;
+};
+
+void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s);
+
#endif /* PPC4XX_H */
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 18/38] ppc440_uc.c: Move some macros to ppc4xx.h
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (16 preceding siblings ...)
2022-10-17 19:19 ` [PULL 17/38] ppc440_sdram: QOM'ify Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 19/38] ppc440_uc.c: Remove unneeded parenthesis Daniel Henrique Barboza
` (20 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
These are used by both the SDRAM controller model and system DCRs. In
preparation to move SDRAM controller in its own file move these macros
to the ppc4xx.h header.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <74d9bf4891e2ccceb52bb6ca6b54fd3f37a9fb04.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_uc.c | 4 ----
include/hw/ppc/ppc4xx.h | 4 ++++
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 55082f2b88..57274b56dd 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -380,10 +380,6 @@ enum {
PESDR1_RSTSTA = 0x365,
};
-#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
-#define SDR0_DDR0_DDRM_DDR1 0x20000000
-#define SDR0_DDR0_DDRM_DDR2 0x40000000
-
static uint32_t dcr_read_sdr(void *opaque, int dcrn)
{
ppc4xx_sdr_t *sdr = opaque;
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index ff88385ac0..10c6dd535f 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -111,6 +111,10 @@ struct Ppc4xxEbcState {
};
/* SDRAM DDR controller */
+#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
+#define SDR0_DDR0_DDRM_DDR1 0x20000000
+#define SDR0_DDR0_DDRM_DDR2 0x40000000
+
#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
struct Ppc4xxSdramDdrState {
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 19/38] ppc440_uc.c: Remove unneeded parenthesis
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (17 preceding siblings ...)
2022-10-17 19:19 ` [PULL 18/38] ppc440_uc.c: Move some macros to ppc4xx.h Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 20/38] hw/ppc/meson: Allow e500 boards to be enabled separately Daniel Henrique Barboza
` (19 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, BALATON Zoltan, Cédric Le Goater,
Daniel Henrique Barboza
From: BALATON Zoltan <balaton@eik.bme.hu>
Remove unneeded parenthesis around case labels.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <19db326bea989c03e08f2853f789315bbe806fe9.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_uc.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 57274b56dd..5fbf44009e 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -499,34 +499,34 @@ static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
uint32_t bcr;
switch (ram_size) {
- case (8 * MiB):
+ case 8 * MiB:
bcr = 0xffc0;
break;
- case (16 * MiB):
+ case 16 * MiB:
bcr = 0xff80;
break;
- case (32 * MiB):
+ case 32 * MiB:
bcr = 0xff00;
break;
- case (64 * MiB):
+ case 64 * MiB:
bcr = 0xfe00;
break;
- case (128 * MiB):
+ case 128 * MiB:
bcr = 0xfc00;
break;
- case (256 * MiB):
+ case 256 * MiB:
bcr = 0xf800;
break;
- case (512 * MiB):
+ case 512 * MiB:
bcr = 0xf000;
break;
- case (1 * GiB):
+ case 1 * GiB:
bcr = 0xe000;
break;
- case (2 * GiB):
+ case 2 * GiB:
bcr = 0xc000;
break;
- case (4 * GiB):
+ case 4 * GiB:
bcr = 0x8000;
break;
default:
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 20/38] hw/ppc/meson: Allow e500 boards to be enabled separately
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (18 preceding siblings ...)
2022-10-17 19:19 ` [PULL 19/38] ppc440_uc.c: Remove unneeded parenthesis Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 21/38] hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx Daniel Henrique Barboza
` (18 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Bernhard Beschow, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza
From: Bernhard Beschow <shentey@gmail.com>
Gives users more fine-grained control over what should be compiled into
QEMU.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-2-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
configs/devices/ppc-softmmu/default.mak | 3 ++-
hw/ppc/Kconfig | 8 ++++++++
hw/ppc/meson.build | 6 ++----
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/configs/devices/ppc-softmmu/default.mak b/configs/devices/ppc-softmmu/default.mak
index 658a454426..a887f5438b 100644
--- a/configs/devices/ppc-softmmu/default.mak
+++ b/configs/devices/ppc-softmmu/default.mak
@@ -1,7 +1,8 @@
# Default configuration for ppc-softmmu
# For embedded PPCs:
-CONFIG_E500=y
+CONFIG_E500PLAT=y
+CONFIG_MPC8544DS=y
CONFIG_PPC405=y
CONFIG_PPC440=y
CONFIG_VIRTEX=y
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 3a4418a69e..22a64745d4 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -132,6 +132,14 @@ config E500
select FDT_PPC
select DS1338
+config E500PLAT
+ bool
+ select E500
+
+config MPC8544DS
+ bool
+ select E500
+
config VIRTEX
bool
select PPC4XX
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 62801923f3..32babc9b48 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -71,12 +71,10 @@ ppc_ss.add(when: 'CONFIG_MAC_OLDWORLD', if_true: files('mac_oldworld.c'))
# NewWorld PowerMac
ppc_ss.add(when: 'CONFIG_MAC_NEWWORLD', if_true: files('mac_newworld.c'))
# e500
+ppc_ss.add(when: 'CONFIG_E500PLAT', if_true: files('e500plat.c'))
+ppc_ss.add(when: 'CONFIG_MPC8544DS', if_true: files('mpc8544ds.c'))
ppc_ss.add(when: 'CONFIG_E500', if_true: files(
'e500.c',
- 'mpc8544ds.c',
- 'e500plat.c'
-))
-ppc_ss.add(when: 'CONFIG_E500', if_true: files(
'mpc8544_guts.c',
'ppce500_spin.c'
))
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 21/38] hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (19 preceding siblings ...)
2022-10-17 19:19 ` [PULL 20/38] hw/ppc/meson: Allow e500 boards to be enabled separately Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 22/38] docs/system/ppc/ppce500: Add heading for networking chapter Daniel Henrique Barboza
` (17 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Bernhard Beschow, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza
From: Bernhard Beschow <shentey@gmail.com>
Having a dedicated config switch makes dependency handling cleaner.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-3-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/gpio/Kconfig | 3 +++
hw/gpio/meson.build | 2 +-
hw/ppc/Kconfig | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index f0e7405f6e..d2cf3accc8 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -8,6 +8,9 @@ config PL061
config GPIO_KEY
bool
+config GPIO_MPC8XXX
+ bool
+
config GPIO_PWR
bool
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 7bd6a57264..b726e6d27a 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -1,5 +1,5 @@
-softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c'))
softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c'))
+softmmu_ss.add(when: 'CONFIG_GPIO_MPC8XXX', if_true: files('mpc8xxx.c'))
softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c'))
softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c'))
softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c'))
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 22a64745d4..791fe78a50 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -124,6 +124,7 @@ config E500
imply AT24C
imply VIRTIO_PCI
select ETSEC
+ select GPIO_MPC8XXX
select OPENPIC
select PLATFORM_BUS
select PPCE500_PCI
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 22/38] docs/system/ppc/ppce500: Add heading for networking chapter
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (20 preceding siblings ...)
2022-10-17 19:19 ` [PULL 21/38] hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 23/38] hw/ppc/e500: Reduce usage of sysbus API Daniel Henrique Barboza
` (16 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Bernhard Beschow, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza
From: Bernhard Beschow <shentey@gmail.com>
The sudden change of topics is slightly confusing and makes the
networking information less visible. So separate the networking chapter
to improve comprehensibility.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-4-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
docs/system/ppc/ppce500.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index 9beef39171..ba6bcb7314 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -146,6 +146,9 @@ You can specify a real world SoC device that QEMU has built-in support but all
these SoCs are e500v2 based MPC85xx series, hence you cannot test anything
built for P4080 (e500mc), P5020 (e5500) and T2080 (e6500).
+Networking
+----------
+
By default a VirtIO standard PCI networking device is connected as an ethernet
interface at PCI address 0.1.0, but we can switch that to an e1000 NIC by:
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 23/38] hw/ppc/e500: Reduce usage of sysbus API
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (21 preceding siblings ...)
2022-10-17 19:19 ` [PULL 22/38] docs/system/ppc/ppce500: Add heading for networking chapter Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 24/38] hw/ppc/mpc8544ds: Rename wrongly named method Daniel Henrique Barboza
` (15 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Bernhard Beschow, Philippe Mathieu-Daudé,
Bin Meng, Daniel Henrique Barboza
From: Bernhard Beschow <shentey@gmail.com>
PlatformBusDevice has an mmio attribute which gets aliased to
SysBusDevice::mmio[0]. So PlatformbusDevice::mmio can be used directly,
avoiding the sysbus API.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20221003203142.24355-5-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/e500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 32495d0123..496c61b612 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -1023,7 +1023,7 @@ void ppce500_init(MachineState *machine)
memory_region_add_subregion(address_space_mem,
pmc->platform_bus_base,
- sysbus_mmio_get_region(s, 0));
+ &pms->pbus_dev->mmio);
}
/*
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 24/38] hw/ppc/mpc8544ds: Rename wrongly named method
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (22 preceding siblings ...)
2022-10-17 19:19 ` [PULL 23/38] hw/ppc/e500: Reduce usage of sysbus API Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 25/38] hw/ppc/mpc8544ds: Add platform bus Daniel Henrique Barboza
` (14 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Bernhard Beschow, Philippe Mathieu-Daudé,
Daniel Henrique Barboza
From: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-6-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/mpc8544ds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 81177505f0..8e674ad195 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -36,7 +36,7 @@ static void mpc8544ds_init(MachineState *machine)
ppce500_init(machine);
}
-static void e500plat_machine_class_init(ObjectClass *oc, void *data)
+static void mpc8544ds_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
PPCE500MachineClass *pmc = PPCE500_MACHINE_CLASS(oc);
@@ -63,7 +63,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo mpc8544ds_info = {
.name = TYPE_MPC8544DS_MACHINE,
.parent = TYPE_PPCE500_MACHINE,
- .class_init = e500plat_machine_class_init,
+ .class_init = mpc8544ds_machine_class_init,
};
static void mpc8544ds_register_types(void)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 25/38] hw/ppc/mpc8544ds: Add platform bus
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (23 preceding siblings ...)
2022-10-17 19:19 ` [PULL 24/38] hw/ppc/mpc8544ds: Rename wrongly named method Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 26/38] hw/ppc/e500: Remove if statement which is now always true Daniel Henrique Barboza
` (13 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Bernhard Beschow, Bin Meng,
Daniel Henrique Barboza
From: Bernhard Beschow <shentey@gmail.com>
Models the real device more closely.
Address and size values are taken from mpc8544.dts from the linux-5.17.7
tree. The IRQ range is taken from e500plat.c.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20221003203142.24355-7-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/mpc8544ds.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 8e674ad195..9c81477698 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -14,6 +14,7 @@
#include "sysemu/device_tree.h"
#include "hw/ppc/openpic.h"
#include "qemu/error-report.h"
+#include "qemu/units.h"
#include "cpu.h"
static void mpc8544ds_fixup_devtree(void *fdt)
@@ -45,6 +46,11 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, void *data)
pmc->pci_nr_slots = 2;
pmc->fixup_devtree = mpc8544ds_fixup_devtree;
pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
+ pmc->has_platform_bus = true;
+ pmc->platform_bus_base = 0xFF800000ULL;
+ pmc->platform_bus_size = 8 * MiB;
+ pmc->platform_bus_first_irq = 5;
+ pmc->platform_bus_num_irqs = 10;
pmc->ccsrbar_base = 0xE0000000ULL;
pmc->pci_mmio_base = 0xC0000000ULL;
pmc->pci_mmio_bus_base = 0xC0000000ULL;
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 26/38] hw/ppc/e500: Remove if statement which is now always true
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (24 preceding siblings ...)
2022-10-17 19:19 ` [PULL 25/38] hw/ppc/mpc8544ds: Add platform bus Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 27/38] target/ppc: Fix xvcmp* clearing FI bit Daniel Henrique Barboza
` (12 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Bernhard Beschow, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza
From: Bernhard Beschow <shentey@gmail.com>
Now that the MPC8544DS board also has a platform bus, the if statement
is always true.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-8-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/e500.c | 30 ++++++++++++++----------------
hw/ppc/e500.h | 1 -
hw/ppc/e500plat.c | 1 -
hw/ppc/mpc8544ds.c | 1 -
4 files changed, 14 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 496c61b612..3e950ea3ba 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -1007,25 +1007,23 @@ void ppce500_init(MachineState *machine)
}
/* Platform Bus Device */
- if (pmc->has_platform_bus) {
- dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
- dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
- qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
- qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
-
- s = SYS_BUS_DEVICE(pms->pbus_dev);
- for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
- int irqn = pmc->platform_bus_first_irq + i;
- sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
- }
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
+ dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
+ qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
+ qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
- memory_region_add_subregion(address_space_mem,
- pmc->platform_bus_base,
- &pms->pbus_dev->mmio);
+ s = SYS_BUS_DEVICE(pms->pbus_dev);
+ for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
+ int irqn = pmc->platform_bus_first_irq + i;
+ sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
}
+ memory_region_add_subregion(address_space_mem,
+ pmc->platform_bus_base,
+ &pms->pbus_dev->mmio);
+
/*
* Smart firmware defaults ahead!
*
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 1e5853b032..68f754ce50 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -27,7 +27,6 @@ struct PPCE500MachineClass {
int mpic_version;
bool has_mpc8xxx_gpio;
- bool has_platform_bus;
hwaddr platform_bus_base;
hwaddr platform_bus_size;
int platform_bus_first_irq;
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index fc911bbb7b..5bb1c603da 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -86,7 +86,6 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
pmc->fixup_devtree = e500plat_fixup_devtree;
pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
pmc->has_mpc8xxx_gpio = true;
- pmc->has_platform_bus = true;
pmc->platform_bus_base = 0xf00000000ULL;
pmc->platform_bus_size = 128 * MiB;
pmc->platform_bus_first_irq = 5;
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 9c81477698..7dd5219736 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -46,7 +46,6 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, void *data)
pmc->pci_nr_slots = 2;
pmc->fixup_devtree = mpc8544ds_fixup_devtree;
pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
- pmc->has_platform_bus = true;
pmc->platform_bus_base = 0xFF800000ULL;
pmc->platform_bus_size = 8 * MiB;
pmc->platform_bus_first_irq = 5;
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 27/38] target/ppc: Fix xvcmp* clearing FI bit
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (25 preceding siblings ...)
2022-10-17 19:19 ` [PULL 26/38] hw/ppc/e500: Remove if statement which is now always true Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 28/38] hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset() Daniel Henrique Barboza
` (11 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Víctor Colombo, Richard Henderson,
Daniel Henrique Barboza
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Vector instructions in general are not supposed to change the FI bit.
However, xvcmp* instructions are calling gen_helper_float_check_status,
which is leading to a cleared FI flag where it should be kept
unchanged.
As helper_float_check_status only affects inexact, overflow and
underflow, and the xvcmp* instructions don't change these flags, this
issue can be fixed by removing the call to helper_float_check_status.
By doing this, the FI bit in FPSCR will be preserved as expected.
Fixes: 00084a25adf ("target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions")
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221005121551.27957-1-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/translate/vsx-impl.c.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 7acdbceec4..e6e5c45ffd 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -810,7 +810,6 @@ static void gen_##name(DisasContext *ctx) \
gen_helper_##name(ignored, cpu_env, xt, xa, xb); \
tcg_temp_free_i32(ignored); \
} \
- gen_helper_float_check_status(cpu_env); \
tcg_temp_free_ptr(xt); \
tcg_temp_free_ptr(xa); \
tcg_temp_free_ptr(xb); \
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 28/38] hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (26 preceding siblings ...)
2022-10-17 19:19 ` [PULL 27/38] target/ppc: Fix xvcmp* clearing FI bit Daniel Henrique Barboza
@ 2022-10-17 19:19 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 29/38] qmp/hmp, device_tree.c: introduce dumpdtb Daniel Henrique Barboza
` (10 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Peter Maydell, Cédric Le Goater,
Daniel Henrique Barboza
From: Peter Maydell <peter.maydell@linaro.org>
In spapr_phb_children_reset() we call device_legacy_reset() to reset any
QOM children of the SPAPR PCI host bridge device. This will not reset
any qbus such a child might own. Switch to device_cold_reset(), which will
reset both the device and its buses. (If the child has no qbuses then
there will be no change in behaviour.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221014142841.2092784-1-peter.maydell@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/spapr_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 57c8a4f085..7b7618d5da 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -2045,7 +2045,7 @@ static int spapr_phb_children_reset(Object *child, void *opaque)
DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
if (dev) {
- device_legacy_reset(dev);
+ device_cold_reset(dev);
}
return 0;
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 29/38] qmp/hmp, device_tree.c: introduce dumpdtb
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (27 preceding siblings ...)
2022-10-17 19:19 ` [PULL 28/38] hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 30/38] hw/nios2: set machine->fdt in nios2_load_dtb() Daniel Henrique Barboza
` (9 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza,
Dr . David Alan Gilbert, Markus Armbruster, Alistair Francis,
David Gibson, Philippe Mathieu-Daudé
To save the FDT blob we have the '-machine dumpdtb=<file>' property.
With this property set, the machine saves the FDT in <file> and exit.
The created file can then be converted to plain text dts format using
'dtc'.
There's nothing particularly sophisticated into saving the FDT that
can't be done with the machine at any state, as long as the machine has
a valid FDT to be saved.
The 'dumpdtb' command receives a 'filename' parameter and, if the FDT is
available via current_machine->fdt, save it in dtb format to 'filename'.
In short, this is a '-machine dumpdtb' that can be fired on demand via
QMP/HMP.
This command will always be executed in-band (i.e. holding BQL),
avoiding potential race conditions with machines that might change the
FDT during runtime (e.g. PowerPC 'pseries' machine).
Cc: Dr. David Alan Gilbert <dgilbert@redhat.com>
Cc: Markus Armbruster <armbru@redhat.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-2-danielhb413@gmail.com>
---
hmp-commands.hx | 15 +++++++++++++++
include/sysemu/device_tree.h | 1 +
monitor/misc.c | 1 +
qapi/machine.json | 18 ++++++++++++++++++
softmmu/device_tree.c | 37 ++++++++++++++++++++++++++++++++++++
5 files changed, 72 insertions(+)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index 8ab8000acd..12b6d4e2dc 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1800,3 +1800,18 @@ ERST
.sub_table = hmp_info_cmds,
.flags = "p",
},
+
+#if defined(CONFIG_FDT)
+ {
+ .name = "dumpdtb",
+ .args_type = "filename:F",
+ .params = "filename",
+ .help = "dump the FDT in dtb format to 'filename'",
+ .cmd = hmp_dumpdtb,
+ },
+
+SRST
+``dumpdtb`` *filename*
+ Dump the FDT in dtb format to *filename*.
+ERST
+#endif
diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h
index ef060a9759..e7c5441f56 100644
--- a/include/sysemu/device_tree.h
+++ b/include/sysemu/device_tree.h
@@ -136,6 +136,7 @@ int qemu_fdt_add_path(void *fdt, const char *path);
} while (0)
void qemu_fdt_dumpdtb(void *fdt, int size);
+void hmp_dumpdtb(Monitor *mon, const QDict *qdict);
/**
* qemu_fdt_setprop_sized_cells_from_array:
diff --git a/monitor/misc.c b/monitor/misc.c
index 6436a8786b..205487e2b9 100644
--- a/monitor/misc.c
+++ b/monitor/misc.c
@@ -49,6 +49,7 @@
#include "sysemu/blockdev.h"
#include "sysemu/sysemu.h"
#include "sysemu/tpm.h"
+#include "sysemu/device_tree.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qerror.h"
#include "qapi/qmp/qstring.h"
diff --git a/qapi/machine.json b/qapi/machine.json
index abb2f48808..b9228a5e46 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -1664,3 +1664,21 @@
'*size': 'size',
'*max-size': 'size',
'*slots': 'uint64' } }
+
+##
+# @dumpdtb:
+#
+# Save the FDT in dtb format.
+#
+# @filename: name of the dtb file to be created
+#
+# Since: 7.2
+#
+# Example:
+# {"execute": "dumpdtb"}
+# "arguments": { "filename": "fdt.dtb" } }
+#
+##
+{ 'command': 'dumpdtb',
+ 'data': { 'filename': 'str' },
+ 'if': 'CONFIG_FDT' }
diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
index 6ca3fad285..ce74f3d48d 100644
--- a/softmmu/device_tree.c
+++ b/softmmu/device_tree.c
@@ -26,6 +26,9 @@
#include "hw/loader.h"
#include "hw/boards.h"
#include "qemu/config-file.h"
+#include "qapi/qapi-commands-machine.h"
+#include "qapi/qmp/qdict.h"
+#include "monitor/hmp.h"
#include <libfdt.h>
@@ -643,3 +646,37 @@ out:
g_free(propcells);
return ret;
}
+
+void qmp_dumpdtb(const char *filename, Error **errp)
+{
+ g_autoptr(GError) err = NULL;
+ uint32_t size;
+
+ if (!current_machine->fdt) {
+ error_setg(errp, "This machine doesn't have a FDT");
+ return;
+ }
+
+ size = fdt_totalsize(current_machine->fdt);
+
+ g_assert(size > 0);
+
+ if (!g_file_set_contents(filename, current_machine->fdt, size, &err)) {
+ error_setg(errp, "Error saving FDT to file %s: %s",
+ filename, err->message);
+ }
+}
+
+void hmp_dumpdtb(Monitor *mon, const QDict *qdict)
+{
+ const char *filename = qdict_get_str(qdict, "filename");
+ Error *local_err = NULL;
+
+ qmp_dumpdtb(filename, &local_err);
+
+ if (hmp_handle_error(mon, local_err)) {
+ return;
+ }
+
+ info_report("dtb dumped to %s", filename);
+}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 30/38] hw/nios2: set machine->fdt in nios2_load_dtb()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (28 preceding siblings ...)
2022-10-17 19:20 ` [PULL 29/38] qmp/hmp, device_tree.c: introduce dumpdtb Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 31/38] hw/ppc: set machine->fdt in bamboo_load_device_tree() Daniel Henrique Barboza
` (8 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza, Chris Wulff,
Marek Vasut, Philippe Mathieu-Daudé
This will enable support for 'dumpdtb' QMP/HMP command for all nios2
machines that uses nios2_load_dtb().
Cc: Chris Wulff <crwulff@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-7-danielhb413@gmail.com>
---
hw/nios2/boot.c | 8 +++++++-
hw/nios2/meson.build | 2 +-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c
index 21cbffff47..b30a7b1efb 100644
--- a/hw/nios2/boot.c
+++ b/hw/nios2/boot.c
@@ -43,6 +43,8 @@
#include "boot.h"
+#include <libfdt.h>
+
#define NIOS2_MAGIC 0x534f494e
static struct nios2_boot_info {
@@ -81,6 +83,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
static int nios2_load_dtb(struct nios2_boot_info bi, const uint32_t ramsize,
const char *kernel_cmdline, const char *dtb_filename)
{
+ MachineState *machine = MACHINE(qdev_get_machine());
int fdt_size;
void *fdt = NULL;
int r;
@@ -113,7 +116,10 @@ static int nios2_load_dtb(struct nios2_boot_info bi, const uint32_t ramsize,
}
cpu_physical_memory_write(bi.fdt, fdt, fdt_size);
- g_free(fdt);
+
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
+
return fdt_size;
}
diff --git a/hw/nios2/meson.build b/hw/nios2/meson.build
index 6c58e8082b..22277bd6c5 100644
--- a/hw/nios2/meson.build
+++ b/hw/nios2/meson.build
@@ -1,5 +1,5 @@
nios2_ss = ss.source_set()
-nios2_ss.add(files('boot.c'))
+nios2_ss.add(files('boot.c'), fdt)
nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c'))
nios2_ss.add(when: 'CONFIG_NIOS2_GENERIC_NOMMU', if_true: files('generic_nommu.c'))
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 31/38] hw/ppc: set machine->fdt in bamboo_load_device_tree()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (29 preceding siblings ...)
2022-10-17 19:20 ` [PULL 30/38] hw/nios2: set machine->fdt in nios2_load_dtb() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 32/38] hw/ppc: set machine->fdt in sam460ex_load_device_tree() Daniel Henrique Barboza
` (7 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza,
Cédric Le Goater, BALATON Zoltan
This will enable support for 'dumpdtb' QMP/HMP command for the bamboo
machine.
Setting machine->fdt requires a MachineState pointer to be used inside
bamboo_load_device_tree(). Let's change the function to receive this
pointer from the caller. 'ramsize' and 'kernel_cmdline' can be retrieved
directly from the 'machine' pointer.
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-9-danielhb413@gmail.com>
---
hw/ppc/ppc440_bamboo.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 56f47e7509..81d71adf34 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -34,6 +34,8 @@
#include "hw/qdev-properties.h"
#include "qapi/error.h"
+#include <libfdt.h>
+
#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
/* from u-boot */
@@ -50,14 +52,13 @@
static hwaddr entry;
-static int bamboo_load_device_tree(hwaddr addr,
- uint32_t ramsize,
- hwaddr initrd_base,
- hwaddr initrd_size,
- const char *kernel_cmdline)
+static int bamboo_load_device_tree(MachineState *machine,
+ hwaddr addr,
+ hwaddr initrd_base,
+ hwaddr initrd_size)
{
int ret = -1;
- uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
+ uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) };
char *filename;
int fdt_size;
void *fdt;
@@ -92,7 +93,7 @@ static int bamboo_load_device_tree(hwaddr addr,
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
}
ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
- kernel_cmdline);
+ machine->kernel_cmdline);
if (ret < 0) {
fprintf(stderr, "couldn't set /chosen/bootargs\n");
}
@@ -113,7 +114,10 @@ static int bamboo_load_device_tree(hwaddr addr,
tb_freq);
rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
- g_free(fdt);
+
+ /* Set ms->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
+
return 0;
}
@@ -157,7 +161,6 @@ static void main_cpu_reset(void *opaque)
static void bamboo_init(MachineState *machine)
{
const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
@@ -280,8 +283,8 @@ static void bamboo_init(MachineState *machine)
/* If we're loading a kernel directly, we must load the device tree too. */
if (kernel_filename) {
- if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
- initrd_size, kernel_cmdline) < 0) {
+ if (bamboo_load_device_tree(machine, FDT_ADDR,
+ RAMDISK_ADDR, initrd_size) < 0) {
error_report("couldn't load device tree");
exit(1);
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 32/38] hw/ppc: set machine->fdt in sam460ex_load_device_tree()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (30 preceding siblings ...)
2022-10-17 19:20 ` [PULL 31/38] hw/ppc: set machine->fdt in bamboo_load_device_tree() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 33/38] hw/ppc: set machine->fdt in xilinx_load_device_tree() Daniel Henrique Barboza
` (6 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza, BALATON Zoltan,
Philippe Mathieu-Daudé
This will enable support for 'dumpdtb' QMP/HMP command for the sam460ex
machine.
Setting machine->fdt requires a MachineState pointer to be used inside
sam460ex_load_device_tree(). Let's change the function to receive this
pointer from the caller. 'ramsize' and 'kernel_cmdline' can be retrieved
directly from the 'machine' pointer.
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-10-danielhb413@gmail.com>
---
hw/ppc/sam460ex.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index f03cdc9ecc..4a22ce3761 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -123,13 +123,12 @@ static int sam460ex_load_uboot(void)
return 0;
}
-static int sam460ex_load_device_tree(hwaddr addr,
- uint32_t ramsize,
+static int sam460ex_load_device_tree(MachineState *machine,
+ hwaddr addr,
hwaddr initrd_base,
- hwaddr initrd_size,
- const char *kernel_cmdline)
+ hwaddr initrd_size)
{
- uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
+ uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) };
char *filename;
int fdt_size;
void *fdt;
@@ -163,7 +162,8 @@ static int sam460ex_load_device_tree(hwaddr addr,
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
(initrd_base + initrd_size));
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
/* Copy data from the host device tree into the guest. Since the guest can
* directly access the timebase without host involvement, we must expose
@@ -200,7 +200,9 @@ static int sam460ex_load_device_tree(hwaddr addr,
EBC_FREQ);
rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
- g_free(fdt);
+
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
return fdt_size;
}
@@ -500,9 +502,8 @@ static void sam460ex_init(MachineState *machine)
if (machine->kernel_filename) {
int dt_size;
- dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
- RAMDISK_ADDR, initrd_size,
- machine->kernel_cmdline);
+ dt_size = sam460ex_load_device_tree(machine, FDT_ADDR,
+ RAMDISK_ADDR, initrd_size);
boot_info->dt_base = FDT_ADDR;
boot_info->dt_size = dt_size;
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 33/38] hw/ppc: set machine->fdt in xilinx_load_device_tree()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (31 preceding siblings ...)
2022-10-17 19:20 ` [PULL 32/38] hw/ppc: set machine->fdt in sam460ex_load_device_tree() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 34/38] hw/ppc: set machine->fdt in pegasos2_machine_reset() Daniel Henrique Barboza
` (5 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza, Edgar E . Iglesias,
Philippe Mathieu-Daudé
This will enable support for 'dumpdtb' QMP/HMP command for the
virtex_ml507 machine.
Setting machine->fdt requires a MachineState pointer to be used inside
xilinx_load_device_tree(). Let's change the function to receive this
pointer from the caller. kernel_cmdline' can be retrieved directly from
the 'machine' pointer. 'ramsize' wasn't being used so can be removed.
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-11-danielhb413@gmail.com>
---
hw/ppc/virtex_ml507.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 493ea0c19f..13cace229b 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -45,6 +45,8 @@
#include "hw/qdev-properties.h"
#include "ppc405.h"
+#include <libfdt.h>
+
#define EPAPR_MAGIC (0x45504150)
#define FLASH_SIZE (16 * MiB)
@@ -144,11 +146,10 @@ static void main_cpu_reset(void *opaque)
}
#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
-static int xilinx_load_device_tree(hwaddr addr,
- uint32_t ramsize,
- hwaddr initrd_base,
- hwaddr initrd_size,
- const char *kernel_cmdline)
+static int xilinx_load_device_tree(MachineState *machine,
+ hwaddr addr,
+ hwaddr initrd_base,
+ hwaddr initrd_size)
{
char *path;
int fdt_size;
@@ -190,18 +191,21 @@ static int xilinx_load_device_tree(hwaddr addr,
error_report("couldn't set /chosen/linux,initrd-end");
}
- r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
+ r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
if (r < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n");
cpu_physical_memory_write(addr, fdt, fdt_size);
- g_free(fdt);
+
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
+
return fdt_size;
}
static void virtex_init(MachineState *machine)
{
const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
hwaddr initrd_base = 0;
int initrd_size = 0;
MemoryRegion *address_space_mem = get_system_memory();
@@ -294,9 +298,8 @@ static void virtex_init(MachineState *machine)
boot_info.fdt = high + (8192 * 2);
boot_info.fdt &= ~8191;
- xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
- initrd_base, initrd_size,
- kernel_cmdline);
+ xilinx_load_device_tree(machine, boot_info.fdt,
+ initrd_base, initrd_size);
}
env->load_info = &boot_info;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 34/38] hw/ppc: set machine->fdt in pegasos2_machine_reset()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (32 preceding siblings ...)
2022-10-17 19:20 ` [PULL 33/38] hw/ppc: set machine->fdt in xilinx_load_device_tree() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 35/38] hw/ppc: set machine->fdt in pnv_reset() Daniel Henrique Barboza
` (4 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza, BALATON Zoltan,
Philippe Mathieu-Daudé
We'll introduce a QMP/HMP command that requires machine->fdt to be set
properly.
Cc: BALATON Zoltan <balaton@eik.bme.hu>
Cc: qemu-ppc@nongnu.org
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-12-danielhb413@gmail.com>
---
hw/ppc/pegasos2.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 61f4263953..ecf682b148 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -331,6 +331,10 @@ static void pegasos2_machine_reset(MachineState *machine)
vof_build_dt(fdt, pm->vof);
vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
+
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
+
pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 35/38] hw/ppc: set machine->fdt in pnv_reset()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (33 preceding siblings ...)
2022-10-17 19:20 ` [PULL 34/38] hw/ppc: set machine->fdt in pegasos2_machine_reset() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 36/38] hw/ppc: set machine->fdt in spapr machine Daniel Henrique Barboza
` (3 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza,
Cédric Le Goater, Frederic Barrat
This will enable support for the 'dumpdtb' QMP/HMP command for
all powernv machines.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-13-danielhb413@gmail.com>
---
hw/ppc/pnv.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 78e00afb9b..40bb573d1a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -678,7 +678,13 @@ static void pnv_reset(MachineState *machine)
qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
- g_free(fdt);
+ /*
+ * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free
+ * the existing machine->fdt to avoid leaking it during
+ * a reset.
+ */
+ g_free(machine->fdt);
+ machine->fdt = fdt;
}
static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 36/38] hw/ppc: set machine->fdt in spapr machine
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (34 preceding siblings ...)
2022-10-17 19:20 ` [PULL 35/38] hw/ppc: set machine->fdt in pnv_reset() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 37/38] hw/riscv: set machine->fdt in sifive_u_machine_init() Daniel Henrique Barboza
` (2 subsequent siblings)
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza, David Gibson,
Philippe Mathieu-Daudé
The pSeries machine never bothered with the common machine->fdt
attribute. We do all the FDT related work using spapr->fdt_blob.
We're going to introduce a QMP/HMP command to dump the FDT, which will
rely on setting machine->fdt properly to work across all machine
archs/types.
Let's set machine->fdt in two places where we manipulate the FDT:
spapr_machine_reset() and CAS. There are other places where the FDT is
manipulated in the pSeries machines, most notably the hotplug/unplug
path. For now we'll acknowledge that we won't have the most accurate
representation of the FDT, depending on the current machine state, when
using this QMP/HMP fdt command. Making the internal FDT representation
always match the actual FDT representation that the guest is using is a
problem for another day.
spapr->fdt_blob is left untouched for now. To replace it with
machine->fdt, since we're migrating spapr->fdt_blob, we would need to
migrate machine->fdt as well. This is something that we would like to to
do keep our code simpler but it's also a work we'll leave for later.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-14-danielhb413@gmail.com>
---
hw/ppc/spapr.c | 3 +++
hw/ppc/spapr_hcall.c | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 8bbaf4f8a4..f79ac85ca1 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1713,6 +1713,9 @@ static void spapr_machine_reset(MachineState *machine)
spapr->fdt_initial_size = spapr->fdt_size;
spapr->fdt_blob = fdt;
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
+
/* Set up the entry state */
first_ppc_cpu->env.gpr[5] = 0;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index a8d4a6bcf0..891206e893 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1256,6 +1256,14 @@ target_ulong do_client_architecture_support(PowerPCCPU *cpu,
spapr->fdt_initial_size = spapr->fdt_size;
spapr->fdt_blob = fdt;
+ /*
+ * Set the machine->fdt pointer again since we just freed
+ * it above (by freeing spapr->fdt_blob). We set this
+ * pointer to enable support for the 'dumpdtb' QMP/HMP
+ * command.
+ */
+ MACHINE(spapr)->fdt = fdt;
+
return H_SUCCESS;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 37/38] hw/riscv: set machine->fdt in sifive_u_machine_init()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (35 preceding siblings ...)
2022-10-17 19:20 ` [PULL 36/38] hw/ppc: set machine->fdt in spapr machine Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 38/38] hw/riscv: set machine->fdt in spike_board_init() Daniel Henrique Barboza
2022-10-18 20:01 ` [PULL 00/38] ppc queue Stefan Hajnoczi
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza, Alistair Francis,
Bin Meng, Palmer Dabbelt, Alistair Francis,
Philippe Mathieu-Daudé
This will enable support for 'dumpdtb' QMP/HMP command for the sifive_u
machine.
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-15-danielhb413@gmail.com>
---
hw/riscv/sifive_u.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e4c814a3ea..b139824aab 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -634,6 +634,9 @@ static void sifive_u_machine_init(MachineState *machine)
start_addr_hi32 = (uint64_t)start_addr >> 32;
}
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = s->fdt;
+
/* reset vector */
uint32_t reset_vec[12] = {
s->msel, /* MSEL pin state */
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PULL 38/38] hw/riscv: set machine->fdt in spike_board_init()
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (36 preceding siblings ...)
2022-10-17 19:20 ` [PULL 37/38] hw/riscv: set machine->fdt in sifive_u_machine_init() Daniel Henrique Barboza
@ 2022-10-17 19:20 ` Daniel Henrique Barboza
2022-10-18 20:01 ` [PULL 00/38] ppc queue Stefan Hajnoczi
38 siblings, 0 replies; 40+ messages in thread
From: Daniel Henrique Barboza @ 2022-10-17 19:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, stefanha, Daniel Henrique Barboza, Palmer Dabbelt,
Alistair Francis, Bin Meng, Philippe Mathieu-Daudé
This will enable support for the 'dumpdtb' QMP/HMP command for the spike
machine.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-16-danielhb413@gmail.com>
---
hw/riscv/spike.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 5ba34543c8..1e1d752c00 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -40,6 +40,8 @@
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
+#include <libfdt.h>
+
static const MemMapEntry spike_memmap[] = {
[SPIKE_MROM] = { 0x1000, 0xf000 },
[SPIKE_HTIF] = { 0x1000000, 0x1000 },
@@ -304,6 +306,10 @@ static void spike_board_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
machine->ram_size, s->fdt);
+
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = s->fdt;
+
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
memmap[SPIKE_MROM].base,
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PULL 00/38] ppc queue
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
` (37 preceding siblings ...)
2022-10-17 19:20 ` [PULL 38/38] hw/riscv: set machine->fdt in spike_board_init() Daniel Henrique Barboza
@ 2022-10-18 20:01 ` Stefan Hajnoczi
38 siblings, 0 replies; 40+ messages in thread
From: Stefan Hajnoczi @ 2022-10-18 20:01 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-ppc, stefanha, Daniel Henrique Barboza
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2022-10-18 20:07 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-10-17 19:19 [PULL 00/38] ppc queue Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 01/38] MAINTAINERS: step back from PPC Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 02/38] target/ppc: restore powerpc_excp_booke doorbell interrupts Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 03/38] ppc440_bamboo: Remove unnecessary memsets Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 04/38] ppc4xx: Introduce Ppc4xxSdramBank struct Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 05/38] ppc4xx_sdram: Get rid of the init RAM hack Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 06/38] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 07/38] ppc440_bamboo: Add missing 4 MiB valid memory size Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 08/38] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 09/38] ppc4xx_sdram: QOM'ify Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 10/38] ppc4xx_sdram: Drop extra zeros for readability Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 11/38] ppc440_sdram: Split off map/unmap of sdram banks for later reuse Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 12/38] ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 13/38] ppc440_sdram: Get rid of the init RAM hack Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 14/38] ppc440_sdram: Rename local variable for readability Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 15/38] ppc4xx_sdram: Rename functions to prevent name clashes Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 16/38] ppc440_sdram: Move RAM size check to ppc440_sdram_init Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 17/38] ppc440_sdram: QOM'ify Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 18/38] ppc440_uc.c: Move some macros to ppc4xx.h Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 19/38] ppc440_uc.c: Remove unneeded parenthesis Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 20/38] hw/ppc/meson: Allow e500 boards to be enabled separately Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 21/38] hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 22/38] docs/system/ppc/ppce500: Add heading for networking chapter Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 23/38] hw/ppc/e500: Reduce usage of sysbus API Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 24/38] hw/ppc/mpc8544ds: Rename wrongly named method Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 25/38] hw/ppc/mpc8544ds: Add platform bus Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 26/38] hw/ppc/e500: Remove if statement which is now always true Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 27/38] target/ppc: Fix xvcmp* clearing FI bit Daniel Henrique Barboza
2022-10-17 19:19 ` [PULL 28/38] hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 29/38] qmp/hmp, device_tree.c: introduce dumpdtb Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 30/38] hw/nios2: set machine->fdt in nios2_load_dtb() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 31/38] hw/ppc: set machine->fdt in bamboo_load_device_tree() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 32/38] hw/ppc: set machine->fdt in sam460ex_load_device_tree() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 33/38] hw/ppc: set machine->fdt in xilinx_load_device_tree() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 34/38] hw/ppc: set machine->fdt in pegasos2_machine_reset() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 35/38] hw/ppc: set machine->fdt in pnv_reset() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 36/38] hw/ppc: set machine->fdt in spapr machine Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 37/38] hw/riscv: set machine->fdt in sifive_u_machine_init() Daniel Henrique Barboza
2022-10-17 19:20 ` [PULL 38/38] hw/riscv: set machine->fdt in spike_board_init() Daniel Henrique Barboza
2022-10-18 20:01 ` [PULL 00/38] ppc queue Stefan Hajnoczi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).