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[149.6.153.187]) by smtp.gmail.com with ESMTPSA id m21-20020ac866d5000000b0039cbd3e4ed1sm4188301qtp.6.2022.10.19.08.06.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 08:06:17 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 0/4] target/i386: support x86_64-v3 for user mode applications Date: Wed, 19 Oct 2022 17:06:12 +0200 Message-Id: <20221019150616.929463-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.256, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The v3 ISA for x86_64 includes F16C and FMA instructions in addition to AVX2 that was just committed for QEMU 7.2. This small series implements these two features and terminates my excursion into x86 TCG. :) Patch 1 is a bugfix for the new decoder (sob). Patch 2 introduces a common function to convert an x86 2-bit rounding mode (as specified in FSTCW, STMXCSR and VROUND instructions). Since the same operand is used by the F16C instruction VCVTPS2PH, it is time to reduce the code duplication instead of adding more. Patches 3 and 4 is the actual implementation, which includes all of helpers, decoding, TCG op emission and tests. Output from QEMU matches that from native x86. Paolo Bonzini (4): target/i386: decode-new: avoid out-of-bounds access to xmm_regs[-1] target/i386: introduce function to set rounding mode from FPCW or MXCSR bits target/i386: implement F16C instructions target/i386: implement FMA instructions target/i386/cpu.c | 8 +- target/i386/cpu.h | 3 + target/i386/ops_sse.h | 152 +++++++++++++++++++------------ target/i386/ops_sse_header.h | 34 +++++++ target/i386/tcg/decode-new.c.inc | 46 ++++++++++ target/i386/tcg/decode-new.h | 3 + target/i386/tcg/emit.c.inc | 60 +++++++++++- target/i386/tcg/fpu_helper.c | 60 +++++------- tests/tcg/i386/test-avx.c | 17 ++++ tests/tcg/i386/test-avx.py | 8 +- 10 files changed, 289 insertions(+), 102 deletions(-) -- 2.37.3