From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 03/31] tcg/s390x: Use register pair allocation for div and mulu2
Date: Thu, 20 Oct 2022 21:52:14 +1000 [thread overview]
Message-ID: <20221020115242.2301066-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221020115242.2301066-1-richard.henderson@linaro.org>
Previously we hard-coded R2 and R3.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-con-set.h | 4 ++--
tcg/s390x/tcg-target-con-str.h | 8 +------
tcg/s390x/tcg-target.c.inc | 43 +++++++++++++++++++++++++---------
3 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 426dd92e51..00ba727b70 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -29,8 +29,8 @@ C_O1_I2(v, v, v)
C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, r, 0)
C_O1_I4(r, r, ri, rI, 0)
-C_O2_I2(b, a, 0, r)
-C_O2_I3(b, a, 0, 1, r)
+C_O2_I2(o, m, 0, r)
+C_O2_I3(o, m, 0, 1, r)
C_O2_I4(r, r, 0, 1, rA, r)
C_O2_I4(r, r, 0, 1, ri, r)
C_O2_I4(r, r, 0, 1, r, r)
diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h
index 8bb0358ae5..76446aecae 100644
--- a/tcg/s390x/tcg-target-con-str.h
+++ b/tcg/s390x/tcg-target-con-str.h
@@ -11,13 +11,7 @@
REGS('r', ALL_GENERAL_REGS)
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
REGS('v', ALL_VECTOR_REGS)
-/*
- * A (single) even/odd pair for division.
- * TODO: Add something to the register allocator to allow
- * this kind of regno+1 pairing to be done more generally.
- */
-REGS('a', 1u << TCG_REG_R2)
-REGS('b', 1u << TCG_REG_R3)
+REGS('o', 0xaaaa) /* odd numbered general regs */
/*
* Define constraint letters for constants:
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 33becd7694..47aaba7667 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2258,10 +2258,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_div2_i32:
- tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RR, DR, args[1], args[4]);
break;
case INDEX_op_divu2_i32:
- tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, DLR, args[1], args[4]);
break;
case INDEX_op_shl_i32:
@@ -2515,17 +2523,30 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_div2_i64:
- /* ??? We get an unnecessary sign-extension of the dividend
- into R3 with this definition, but as we do in fact always
- produce both quotient and remainder using INDEX_op_div_i64
- instead requires jumping through even more hoops. */
- tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
+ /*
+ * ??? We get an unnecessary sign-extension of the dividend
+ * into op0 with this definition, but as we do in fact always
+ * produce both quotient and remainder using INDEX_op_div_i64
+ * instead requires jumping through even more hoops.
+ */
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, DSGR, args[1], args[4]);
break;
case INDEX_op_divu2_i64:
- tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, DLGR, args[1], args[4]);
break;
case INDEX_op_mulu2_i64:
- tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, MLGR, args[1], args[3]);
break;
case INDEX_op_shl_i64:
@@ -3220,10 +3241,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_div2_i64:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
- return C_O2_I3(b, a, 0, 1, r);
+ return C_O2_I3(o, m, 0, 1, r);
case INDEX_op_mulu2_i64:
- return C_O2_I2(b, a, 0, r);
+ return C_O2_I2(o, m, 0, r);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
--
2.34.1
next prev parent reply other threads:[~2022-10-20 14:19 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 11:52 [PATCH 00/31] tcg: Support for Int128 with helpers Richard Henderson
2022-10-20 11:52 ` [PATCH 01/31] tcg: Tidy tcg_reg_alloc_op Richard Henderson
2022-10-20 11:52 ` [PATCH 02/31] tcg: Introduce paired register allocation Richard Henderson
2022-10-20 11:52 ` Richard Henderson [this message]
2022-10-20 11:52 ` [PATCH 04/31] tcg/arm: Use register pair allocation for qemu_{ld, st}_i64 Richard Henderson
2022-10-20 11:52 ` [PATCH 05/31] meson: Move CONFIG_TCG_INTERPRETER to config_host Richard Henderson
2022-10-20 11:52 ` [PATCH 06/31] tcg: Remove TCG_TARGET_STACK_GROWSUP Richard Henderson
2022-10-20 15:25 ` Philippe Mathieu-Daudé
2022-10-20 11:52 ` [PATCH 07/31] accel/tcg: Set cflags_next_tb in cpu_common_initfn Richard Henderson
2022-10-20 11:52 ` [PATCH 08/31] target/sparc: Avoid TCGV_{LOW,HIGH} Richard Henderson
2022-10-20 11:52 ` [PATCH 09/31] tcg: Move TCG_{LOW,HIGH} to tcg-internal.h Richard Henderson
2022-10-20 14:52 ` Philippe Mathieu-Daudé
2022-10-20 11:52 ` [PATCH 10/31] tcg: Add temp_subindex to TCGTemp Richard Henderson
2022-10-20 14:57 ` Philippe Mathieu-Daudé
2022-10-20 11:52 ` [PATCH 11/31] tcg: Allocate TCGTemp pairs in host memory order Richard Henderson
2022-10-20 15:01 ` Philippe Mathieu-Daudé
2022-10-20 21:33 ` Richard Henderson
2022-10-20 11:52 ` [PATCH 12/31] tcg: Move TCG_TYPE_COUNT outside enum Richard Henderson
2022-10-20 15:03 ` Philippe Mathieu-Daudé
2022-10-20 11:52 ` [PATCH 13/31] tcg: Introduce tcg_type_size Richard Henderson
2022-10-20 11:52 ` [PATCH 14/31] tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind Richard Henderson
2022-10-20 11:52 ` [PATCH 15/31] tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 Richard Henderson
2022-10-20 15:12 ` Philippe Mathieu-Daudé
2022-10-20 21:39 ` Richard Henderson
2022-10-20 11:52 ` [PATCH 16/31] tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 Richard Henderson
2022-10-20 11:52 ` [PATCH 17/31] tcg: Use TCG_CALL_ARG_EVEN for TCI special case Richard Henderson
2022-10-20 11:52 ` [PATCH 18/31] tcg: Reorg function calls Richard Henderson
2022-10-20 11:52 ` [PATCH 19/31] tcg: Move ffi_cif pointer into TCGHelperInfo Richard Henderson
2022-10-20 11:52 ` [PATCH 20/31] tcg: Add TCGHelperInfo argument to tcg_out_call Richard Henderson
2022-10-20 15:41 ` Philippe Mathieu-Daudé
2022-10-20 11:52 ` [PATCH 21/31] tcg: Define TCG_TYPE_I128 and related helper macros Richard Henderson
2022-10-20 11:52 ` [PATCH 22/31] tcg: Add TCG_CALL_{RET,ARG}_NORMAL_4 Richard Henderson
2022-10-20 11:52 ` [PATCH 23/31] tcg: Allocate objects contiguously in temp_allocate_frame Richard Henderson
2022-10-20 11:52 ` [PATCH 24/31] tcg: Introduce tcg_out_addi_ptr Richard Henderson
2022-10-20 11:52 ` [PATCH 25/31] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Richard Henderson
2022-10-20 11:52 ` [PATCH 26/31] tcg: Introduce tcg_target_call_oarg_reg Richard Henderson
2022-10-20 11:52 ` [PATCH 27/31] tcg: Add TCG_CALL_RET_BY_VEC Richard Henderson
2022-10-20 11:52 ` [PATCH 28/31] include/qemu/int128: Use Int128 structure for TCI Richard Henderson
2022-10-20 11:52 ` [PATCH 29/31] tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128 Richard Henderson
2022-10-20 11:52 ` [PATCH 30/31] tcg: Add temp allocation for TCGv_i128 Richard Henderson
2022-10-20 11:52 ` [PATCH 31/31] tcg: Add tcg_gen_extr_i128_i64, tcg_gen_concat_i64_i128 Richard Henderson
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