* Re: [PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12
2022-10-22 9:58 [PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Richard Henderson
@ 2022-10-23 12:00 ` LIU Zhiwei
2022-10-25 0:21 ` Alistair Francis
2022-10-25 1:30 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: LIU Zhiwei @ 2022-10-23 12:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Alistair.Francis, qemu-riscv, palmer
On 2022/10/22 17:58, Richard Henderson wrote:
> We were matching a signed 13-bit range, not a 12-bit range.
> Expand the commentary within the function and be explicit
> about all of the ranges.
>
> Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1cdaf7b57b..2a84c57bec 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
> if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
> + /*
> + * Sign extended from 12 bits: [-0x800, 0x7ff].
> + * Used for most arithmetic, as this is the isa field.
> + */
> + if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
> + /*
> + * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
> + * Used for subtraction, where a constant must be handled by ADDI.
> + */
> + if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
> + /*
> + * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
> + * Used by addsub2, which may need the negative operation,
> + * and requires the modified constant to be representable.
> + */
> + if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
> return 1;
> }
> return 0;
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12
2022-10-22 9:58 [PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Richard Henderson
2022-10-23 12:00 ` LIU Zhiwei
@ 2022-10-25 0:21 ` Alistair Francis
2022-10-25 1:30 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-10-25 0:21 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, Alistair.Francis, qemu-riscv, palmer, LIU Zhiwei
On Sat, Oct 22, 2022 at 8:19 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We were matching a signed 13-bit range, not a 12-bit range.
> Expand the commentary within the function and be explicit
> about all of the ranges.
>
> Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1cdaf7b57b..2a84c57bec 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
> if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
> + /*
> + * Sign extended from 12 bits: [-0x800, 0x7ff].
> + * Used for most arithmetic, as this is the isa field.
> + */
> + if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
> + /*
> + * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
> + * Used for subtraction, where a constant must be handled by ADDI.
> + */
> + if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
> + /*
> + * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
> + * Used by addsub2, which may need the negative operation,
> + * and requires the modified constant to be representable.
> + */
> + if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
> return 1;
> }
> return 0;
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12
2022-10-22 9:58 [PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Richard Henderson
2022-10-23 12:00 ` LIU Zhiwei
2022-10-25 0:21 ` Alistair Francis
@ 2022-10-25 1:30 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-10-25 1:30 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, Alistair.Francis, qemu-riscv, palmer, LIU Zhiwei
On Sat, Oct 22, 2022 at 8:19 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We were matching a signed 13-bit range, not a 12-bit range.
> Expand the commentary within the function and be explicit
> about all of the ranges.
>
> Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1cdaf7b57b..2a84c57bec 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
> if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
> + /*
> + * Sign extended from 12 bits: [-0x800, 0x7ff].
> + * Used for most arithmetic, as this is the isa field.
> + */
> + if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
> + /*
> + * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
> + * Used for subtraction, where a constant must be handled by ADDI.
> + */
> + if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
> return 1;
> }
> - if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
> + /*
> + * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
> + * Used by addsub2, which may need the negative operation,
> + * and requires the modified constant to be representable.
> + */
> + if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
> return 1;
> }
> return 0;
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread