From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
richard.henderson@linaro.org, bin.meng@windriver.com,
lzw194868@alibaba-inc.com,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [PATCH 1/1] tcg/riscv: Fix base regsiter for qemu_ld/st
Date: Sun, 23 Oct 2022 20:41:48 +0800 [thread overview]
Message-ID: <20221023124148.6283-1-zhiwei_liu@linux.alibaba.com> (raw)
When guest base is zero, we should use addr_regl as base regiser instead of
the initial register TCG_REG_TMP0. Besides, we can remove the
unnecessary use of base register.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
tcg/riscv/tcg-target.c.inc | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 81a83e45b1..946da1bb72 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1158,7 +1158,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
#else
unsigned a_bits;
#endif
- TCGReg base = TCG_REG_TMP0;
data_regl = *args++;
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
@@ -1169,24 +1168,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
#if defined(CONFIG_SOFTMMU)
tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, TCG_REG_TMP0, opc, is_64);
add_qemu_ldst_label(s, 1, oi,
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
+ tcg_out_ext32u(s, addr_regl, addr_regl);
}
a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, true, addr_regl, a_bits);
}
if (guest_base != 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ tcg_out_opc_reg(s, OPC_ADD, addr_regl, TCG_GUEST_BASE_REG, addr_regl);
}
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, addr_regl, opc, is_64);
#endif
}
@@ -1230,7 +1228,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
#else
unsigned a_bits;
#endif
- TCGReg base = TCG_REG_TMP0;
data_regl = *args++;
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
@@ -1241,24 +1238,23 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
#if defined(CONFIG_SOFTMMU)
tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
+ tcg_out_qemu_st_direct(s, data_regl, data_regh, TCG_REG_TMP0, opc);
add_qemu_ldst_label(s, 0, oi,
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
+ tcg_out_ext32u(s, addr_regl, addr_regl);
}
a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, false, addr_regl, a_bits);
}
if (guest_base != 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ tcg_out_opc_reg(s, OPC_ADD, addr_regl, TCG_GUEST_BASE_REG, addr_regl);
}
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
+ tcg_out_qemu_st_direct(s, data_regl, data_regh, addr_regl, opc);
#endif
}
--
2.25.1
next reply other threads:[~2022-10-24 5:04 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-23 12:41 LIU Zhiwei [this message]
2022-10-23 15:42 ` [PATCH 1/1] tcg/riscv: Fix base regsiter for qemu_ld/st Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221023124148.6283-1-zhiwei_liu@linux.alibaba.com \
--to=zhiwei_liu@linux.alibaba.com \
--cc=Alistair.Francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=lzw194868@alibaba-inc.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).